From: "Noddy" Newsgroups: comp.arch.fpga Subject: Power supply caps on PCB Date: Mon, 10 Jun 2002 12:57:14 +0200 Organization: Rhodes University, Grahamstown, South Africa Lines: 11 Message-ID: <1023706297.365340@turtle.ru.ac.za> NNTP-Posting-Host: turtle.ru.ac.za X-Trace: hippo.ru.ac.za 1023706297 73424 146.231.128.8 (10 Jun 2002 10:51:37 GMT) X-Complaints-To: usenet@hippo.ru.ac.za NNTP-Posting-Date: Mon, 10 Jun 2002 10:51:37 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Cache-Post-Path: turtle.ru.ac.za!phat@big-ears.phys.ru.ac.za X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out.nuthinbutnews.com!propagator-sterling!news-in.nuthinbutnews.com!newsfeed.nyc.globix.net!infeed.is.co.za!feeder.is.co.za!146.231.128.1.MISMATCH!hippo.ru.ac.za!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18250 Hi, I know that one should place 0.1uF and 0.01uF caps on all power supply pins on the FPGA... does this include both Vcco and Vccint, or can one get away with just Vccint and then put only 0.1uF on Vcco. I am seriously running out of room on my PCB, and increasing the PCB size is not an option! adrian ###### From: "Arash Salarian" Newsgroups: comp.arch.fpga References: <1023706297.365340@turtle.ru.ac.za> Subject: Re: Power supply caps on PCB Date: Mon, 10 Jun 2002 14:43:59 +0200 Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 NNTP-Posting-Host: metpc38.epfl.ch Message-ID: <3d049f19@epflnews.epfl.ch> X-Trace: epflnews.epfl.ch 1023713049 metpc38.epfl.ch (10 Jun 2002 14:44:09 +0200) Organization: EPFL Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!epflnews.epfl.ch Xref: chonsp.franklin.ch comp.arch.fpga:18248 "Noddy" wrote in message news:1023706297.365340@turtle.ru.ac.za... > Hi, > > I know that one should place 0.1uF and 0.01uF caps on all power supply pins > on the FPGA... does this include both Vcco and Vccint, or can one get away > with just Vccint and then put only 0.1uF on Vcco. I am seriously running out > of room on my PCB, and increasing the PCB size is not an option! > > adrian > > It's "vital" to put those caps if you need to get correct results from your board ;) And for the capacitors, follow exactly the directions from the data-sheets of your device. Unless you're not going to analyze your PCB with something like Hyperlynx, you'd better be carefull to follow what is suggested in the data-sheet as choosing the right capacitor and it's placement is not a trivial job. Regards Arash ###### Message-ID: <3D04C79F.27B05F2F@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Mon, 10 Jun 2002 15:37:04 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1023723424 192.65.17.17 (Mon, 10 Jun 2002 09:37:04 MDT) NNTP-Posting-Date: Mon, 10 Jun 2002 09:37:04 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18268 Are you running 400 outputs at 24mA fast TTL? 16 outputs at 2mA LVCMOS? The output slew - translated into current draw during the risetime - is what determines how much local decoupling demand you have on the Vcco. If you have fewer and slower outputs, the output slew could be less of a contribution than the FPGA internals connected to that voltage, but the instantaneous current needs are a good place to start. So... what's your slew, what's the load capacitance you're driving, how many signals do you have? You can figure out the voltage fluctuations based on both capacitance and series resonance frequency of the capacitors. If you have limited board space and need the decoupling, there are more expensive capacitor alternatives than the standard surface mount parts. Suppliers such as AVX (Kyocera) have special caps that can get a bit pricey but with good connections to the planes and good localization you can change the "rule of thumb" and get the decoupling you need. Without some form of simple analysis, stick to the rule of thumb. Noddy wrote: > Hi, > > I know that one should place 0.1uF and 0.01uF caps on all power supply pins > on the FPGA... does this include both Vcco and Vccint, or can one get away > with just Vccint and then put only 0.1uF on Vcco. I am seriously running out > of room on my PCB, and increasing the PCB size is not an option! > > adrian ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Wed, 12 Jun 2002 11:58:16 -0400 Organization: Arius, Inc Lines: 53 Message-ID: <3D076F98.280FB310@yahoo.com> References: <1023706297.365340@turtle.ru.ac.za> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYmWDIox5AqkamKi2kw/P25Q2F7bSxRUEz26lYfOe7KOrsSFy5DANgu X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 12 Jun 2002 15:58:01 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18353 Noddy wrote: > > Hi, > > I know that one should place 0.1uF and 0.01uF caps on all power supply pins > on the FPGA... does this include both Vcco and Vccint, or can one get away > with just Vccint and then put only 0.1uF on Vcco. I am seriously running out > of room on my PCB, and increasing the PCB size is not an option! > > adrian My experience is that there is a lot of "voodoo" floating around when it comes to supply bypassing. I have NEVER seen adequate justification for using both 0.1 uF and 0.01 uF caps on the same supply rail. I know the argument that the smaller caps have a higher self resonant frequency (SRF), but that does not hold water. The SRF is higher, but the SRF is not what we care about. The important spec is the impedance at the frequency of interest. If you go to the cap manufacturer's web site and download the docs, you will see that the impedance curves for different value caps are nearly identical at the frequencies of interest. The larger caps have lower impedance below SRF and of course the SRF point is the minimum. So at the point of SRF for the smaller cap, the impedance is lower. But above SRF, which is where most of the noise on a board lies, the impedance is nearly the same. Above SRF the impedance is much more impacted by the cap size and shape. So using two sizes of caps is not warranted. Try to use one cap on each power pin with as short a lead as possible. The longer the lead, the worse the added inductance and increased impedance. But if the power pins are very close and more caps just can't be squeezed in, I use one cap for two or even three pins. The main thing is to keep the traces short to keep down the parasitic inductance. Oh, you don't need tantalum caps for each chip either. They only provide effective bypassing at freqs below 1 MHz or so. At these freqs the location on the board is not an issue since the ground and power planes have a very low impedance. So there is little reason to use 10 tantalums of 10 uF instead of one 100 uF part. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3D07813B.46CF94AB@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 Date: Wed, 12 Jun 2002 17:13:31 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1023902011 192.65.17.17 (Wed, 12 Jun 2002 11:13:31 MDT) NNTP-Posting-Date: Wed, 12 Jun 2002 11:13:31 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18349 For minimum "impedance at the frequency of interest," the SRF *is* what we care about (along with the equivalent series resistance). If you use a cap with a higher SRF, the impedance will be higher than you could otherwise achieve. If you use a cap with a lower SRF you are - once again - losing out on the impedance because of the inductive effect. The different packages tend to allow either deeper curves (lower impedance across the frequency range around the SRF) and/or wider "bottoms" where the impedance is comfortably low. We could just add capacitors until there's no more room on our boards and the paralleled impedances at the frequency of interest might be near where we want them. A judicious choice of caps "near" the chip (1/10 wavelength for the frequency of interest, perhaps) - not for each power/ground pin pair - might be a best fit. Might. Plane inductances to the caps and to the devices do play a part. It really is voodoo. rickman wrote: > I know the > argument that the smaller caps have a higher self resonant frequency > (SRF), but that does not hold water. The SRF is higher, but the SRF is > not what we care about. The important spec is the impedance at the > frequency of interest. If you go to the cap manufacturer's web site and > download the docs, you will see that the impedance curves for different > value caps are nearly identical at the frequencies of interest. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Thu, 13 Jun 2002 11:58:03 -0400 Organization: Arius, Inc Lines: 77 Message-ID: <3D08C10B.E26EAA6D@yahoo.com> References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaaXaHSUNBrkfDRSQ5xswZWjkP2lVEbwKv5ccCr0+5EUHHZMIerpGXe X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 13 Jun 2002 15:58:04 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18363 I don't mean to be argumentative, but I might not understand what you are saying. John_H wrote: > > For minimum "impedance at the frequency of interest," the SRF *is* what we care > about (along with the equivalent series resistance). If you use a cap with a > higher SRF, the impedance will be higher than you could otherwise achieve. If you > use a cap with a lower SRF you are - once again - losing out on the impedance > because of the inductive effect. You make it sound like you are trying to create a low impedance at a single frequency. All of my experience has indicated that you need to handle noise at a wide range of frequencies above the clock rate(s). So trying to place the narrow SRF at a single point is of little or no value. Further, the fact that a cap is inductive at a given frequency is not an issue. The impedance can still be quite low and in fact you will want to put the SRF near the middle of the frequency range you need to silence. So half the work will be done in the range where the cap is inductive. > The different packages tend to allow either > deeper curves (lower impedance across the frequency range around the SRF) and/or > wider "bottoms" where the impedance is comfortably low. Again this sounds like you are targeting the SRF to a narrow freq range. How do you determine where to put the SRF and how do you pick your caps to match that. Further, if you are trying to match the SRF to the design, how do you accomodate the parasitic inductance and capacitance. Won't that throw off the SRF? > We could just add capacitors until there's no more room on our boards and the > paralleled impedances at the frequency of interest might be near where we want > them. A judicious choice of caps "near" the chip (1/10 wavelength for the > frequency of interest, perhaps) - not for each power/ground pin pair - might be a > best fit. Might. Plane inductances to the caps and to the devices do play a > part. You can put your caps near the "chip" if you are just trying to lower the impedance of the ground/power planes. But if you are addressing the needs of the chip, then you should keep the caps near the power/ground pins. If I remember correctly, the issue is the area of the loop including the cap, the traces, the chip leads and the power distribution on the chip which determines the inductance of the connection to the cap. > It really is voodoo. If you say that again, I'll tell Dr. Howard Johnson on you. Howard Johnson, Howard Johnson, Howard Johnson! There, now look out! > rickman wrote: > > > I know the > > argument that the smaller caps have a higher self resonant frequency > > (SRF), but that does not hold water. The SRF is higher, but the SRF is > > not what we care about. The important spec is the impedance at the > > frequency of interest. If you go to the cap manufacturer's web site and > > download the docs, you will see that the impedance curves for different > > value caps are nearly identical at the frequencies of interest. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3D08D2D0.5C243B54@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 119 Date: Thu, 13 Jun 2002 17:13:52 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1023988432 192.65.17.17 (Thu, 13 Jun 2002 11:13:52 MDT) NNTP-Posting-Date: Thu, 13 Jun 2002 11:13:52 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.cwix.com!sjc-peer.news.verio.net!news.verio.net!news.sanjose1.Level3.net!Level3.net!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18402 There's so many aspects to "clean decoupling design" that it's hard to communicate well what I do understand. I communicate what I don't understand even worse ;-) rickman wrote: > I don't mean to be argumentative, but I might not understand what you > are saying. The conversation is good, no negatives seen from my end. > John_H wrote: > > > > For minimum "impedance at the frequency of interest," the SRF *is* what we care > > about (along with the equivalent series resistance). If you use a cap with a > > higher SRF, the impedance will be higher than you could otherwise achieve. If you > > use a cap with a lower SRF you are - once again - losing out on the impedance > > because of the inductive effect. > > You make it sound like you are trying to create a low impedance at a > single frequency. All of my experience has indicated that you need to > handle noise at a wide range of frequencies above the clock rate(s). So > trying to place the narrow SRF at a single point is of little or no > value. Further, the fact that a cap is inductive at a given frequency > is not an issue. The impedance can still be quite low and in fact you > will want to put the SRF near the middle of the frequency range you need > to silence. So half the work will be done in the range where the cap is > inductive. The wide range of frequencies is, indeed, very important. I had kept close to my engineering heart the "truth" that more capacitance is most often a good thing, that low capacitance values were silly. If I throw together a dozen 1uF ceramic caps, I end up with a nice low impedance at the SRF but not so very low a decade or two above or below. One graph I'm looking at shows an SRF of about 7MHz for a 1uF 1206. The impedance at 7MHz is about 0.1 Ohm each. The impedance drops to 1ohm around 250kHz and 150MHz. While these values aren't bad, consider the current demands for 150MHz: 1/12 Ohm (12 1uF caps in parallel, ignoring other parasitics for the moment) will keep the voltage tolerance within 100mV for 1.2A surges. Maybe this is sufficient, but one cap with an SRF around 150MHz would give you performance nearly as good at 150MHz. The 7MHz filtering in the 12 cap configuration above is probably significant overkill at 8.3 milliOhm. A mix would allow a low overall impedance floor without overkill. > > The different packages tend to allow either > > deeper curves (lower impedance across the frequency range around the SRF) and/or > > wider "bottoms" where the impedance is comfortably low. > > Again this sounds like you are targeting the SRF to a narrow freq > range. How do you determine where to put the SRF and how do you pick > your caps to match that. Further, if you are trying to match the SRF to > the design, how do you accomodate the parasitic inductance and > capacitance. Won't that throw off the SRF? The parasitic inductance will throw the numbers off. It won't throw them off by much if the cap is within a fraction of a "wavelength of interest" on a good plane and the caps and power/ground pins have good connections to the planes. The "swiss cheese effect" of getting power to the center pins of a BGA with its array of holes has been shown to be manageable - it doesn't throw too much extra inductance into the situation at realiztic frequencies. The caps need to be selected with a nice "spread" across the frequencies you're working with. An SRF at 1MHz and another at 100MHz will actually give you problems - a resonance - at 10MHz, reducing the effects of even the one type of capacitor. If the SRF values are kept somewhat close, the resonance shouldn't be a big issue (evaluate "somewhat?" I don't have a good value to suggest, but a decade is well beyond what I'd like to use). My clock frequency is a major design consideration. The clocks have harmonics and the data gives a spread below that frequency as well. Since bulk caps contribute to the lower frequency end, I'd concentrate on frequencies at the clock and above for solid selection. > > We could just add capacitors until there's no more room on our boards and the > > paralleled impedances at the frequency of interest might be near where we want > > them. A judicious choice of caps "near" the chip (1/10 wavelength for the > > frequency of interest, perhaps) - not for each power/ground pin pair - might be a > > best fit. Might. Plane inductances to the caps and to the devices do play a > > part. > > You can put your caps near the "chip" if you are just trying to lower > the impedance of the ground/power planes. But if you are addressing the > needs of the chip, then you should keep the caps near the power/ground > pins. If I remember correctly, the issue is the area of the loop > including the cap, the traces, the chip leads and the power distribution > on the chip which determines the inductance of the connection to the > cap. The chip needs very low impedance to ground. If you can't mount your cap on the same side of the board as the chip, you have to go through a via anyway, encountering loop inductance. If you can mount the cap on the same side of the board but have to use more track to connect, the narrow line gives you loop inductance. When you have the cap and the pins both connected to a plane - even the swiss cheese - the inductance is manageable. One cap per power/ground pin pair isn't helping out much except for paralleling the impedances. > > It really is voodoo. > > If you say that again, I'll tell Dr. Howard Johnson on you. Howard > Johnson, Howard Johnson, Howard Johnson! There, now look out! :-X > > rickman wrote: > > > > > I know the > > > argument that the smaller caps have a higher self resonant frequency > > > (SRF), but that does not hold water. The SRF is higher, but the SRF is > > > not what we care about. The important spec is the impedance at the > > > frequency of interest. If you go to the cap manufacturer's web site and > > > download the docs, you will see that the impedance curves for different > > > value caps are nearly identical at the frequencies of interest. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3D092B0D.E5C0DE0D@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0915B1.77F1@designtools.co.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 62 Date: Thu, 13 Jun 2002 23:30:19 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1024011019 192.65.17.17 (Thu, 13 Jun 2002 17:30:19 MDT) NNTP-Posting-Date: Thu, 13 Jun 2002 17:30:19 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18450 The "notch" isn't a 20dB dip in a 1% bandwidth as notch filters would. The SRF gives the bottom of a somewhat wide bottom. My point is that - rather than paralleling a bunch of these "bathtubs" to get an overall "bathtub" curve so that the ends provide a low enough impedance - one should get the SRFs lined up across a wide enough coverage that the overall impedance floor is much wider at a target impedance. A 10:1 impedance for the 1uF cap I mentioned is about 250kHz to 150 MHz. If the minimum impedance on the chosen caps are low and the SRFs are distributed, the overall effect is greater wideband stiffness. Load-step response is addressed by spreading the SRFs across a range of frequencies. The clock has harmonics and the data tends to downspread, including those harmonics. There's a time domain for the step and a frequency domain for the impedances that need to line up to each other. The balance can be struck without "one 0.1uF and one 0.01uF cap per power/ground pin pair." The single-point spectrum isn't my concern as much as "covering holes." Make sure your impedance at all frequencies is low. If the impedance could be improved across a frequency band that isn't stiff enough, add a cap that covers that hole. The tolerances and tempcos will move the bottom around a little, but compared to the 2x bottom of around 2-20MHz, (0.2 ohm @ 2MHz, 0.1 ohm @ 7 MHz, 0.2 ohm at 20 MHz), several percent changes won't skew a decade of good impedance. Jim Granville wrote: > John_H wrote: > > > The wide range of frequencies is, indeed, very important. I had kept close to my > > engineering heart the "truth" that more capacitance is most often a good thing, that low > > capacitance values were silly. If I throw together a dozen 1uF ceramic caps, I end up > > with a nice low impedance at the SRF but not so very low a decade or two above or > > below. One graph I'm looking at shows an SRF of about 7MHz for a 1uF 1206. The > > impedance at 7MHz is about 0.1 Ohm each. The impedance drops to 1ohm around 250kHz and > > 150MHz. While these values aren't bad, consider the current demands for 150MHz: 1/12 > > Ohm (12 1uF caps in parallel, ignoring other parasitics for the moment) will keep the > > voltage tolerance within 100mV for 1.2A surges. > > Sudden load step-response is very important. The Pentium power supplies > know all > about this, and bigger FPGA ones should too. > > > Maybe this is sufficient, but one cap > > with an SRF around 150MHz would give you performance nearly as good at 150MHz. > > Not sure you can move from load step, to this SRF comment - a load step > cannot have > a single-point 150Mhz spectrum ? > > > The 7MHz > > filtering in the 12 cap configuration above is probably significant overkill at 8.3 > > milliOhm. A mix would allow a low overall impedance floor without overkill. > > I think where SRF _can_ help, is not so much in total lowering, but in > a > 'focus on area of complaint' - eg a marine radio telephone user at > 156MHz etc. > > The tolerances and tempco's are such that the notch will move about a > bit anyway... > > -jg ###### Message-ID: <3D093998.656B@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0915B1.77F1@designtools.co.nz> <3D092B0D.E5C0DE0D@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 29 Date: Fri, 14 Jun 2002 12:32:24 +1200 NNTP-Posting-Host: 203.79.98.34 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1024014840 203.79.98.34 (Fri, 14 Jun 2002 12:34:00 NZST) NNTP-Posting-Date: Fri, 14 Jun 2002 12:34:00 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!216.227.56.88.MISMATCH!DirecTVinternet!DirecTV-DSL!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18431 John_H wrote: > > The "notch" isn't a 20dB dip in a 1% bandwidth as notch filters would. The SRF gives the > bottom of a somewhat wide bottom. My point is that - rather than paralleling a bunch of these > "bathtubs" to get an overall "bathtub" curve so that the ends provide a low enough impedance - > one should get the SRFs lined up across a wide enough coverage that the overall impedance > floor is much wider at a target impedance. A 10:1 impedance for the 1uF cap I mentioned is > about 250kHz to 150 MHz. If the minimum impedance on the chosen caps are low and the SRFs are > distributed, the overall effect is greater wideband stiffness. > > Load-step response is addressed by spreading the SRFs across a range of frequencies. The > clock has harmonics and the data tends to downspread, including those harmonics. There's a > time domain for the step and a frequency domain for the impedances that need to line up to > each other. The balance can be struck without "one 0.1uF and one 0.01uF cap per power/ground > pin pair." > > The single-point spectrum isn't my concern as much as "covering holes." Make sure your > impedance at all frequencies is low. If the impedance could be improved across a frequency > band that isn't stiff enough, add a cap that covers that hole. > > The tolerances and tempcos will move the bottom around a little, but compared to the 2x bottom > of around 2-20MHz, (0.2 ohm @ 2MHz, 0.1 ohm @ 7 MHz, 0.2 ohm at 20 MHz), several percent > changes won't skew a decade of good impedance. Sounds right to me. Anyone got any practical experience with SRF spread & deployment, on real PCBs ? -jg ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: 14 Jun 2002 08:58:42 +0100 Organization: TRW Conekt Lines: 25 Sender: Thompsm@977845-DT Message-ID: References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0915B1.77F1@designtools.co.nz> <3D092B0D.E5C0DE0D@mail.com> <3D093998.656B@designtools.co.nz> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1024041520 6006143 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18415 Jim Granville writes: > Anyone got any practical experience with SRF spread & deployment, on > real PCBs ? > My last design (2 Altera 10KE100s and a TI C6711 amongst other things) has a power distribution system designed in just such a way as to keep the imppedance flattish and beneath a target impedance (as suggested in http://groups.yahoo.com/group/si-list/files/Signal%20Integrity%20Documents/Published%20SI%20Papers%20from%20Sun/cpmt_1999.pdf - apologies for a the long link!) Seems to work well, although I haven;t had chance to get any actual numbers from it - other than the noise on the various power planes (as viewed on a Tek LogiScope @ up to 2Gs/sec) is much less than the 5% tolerance. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Fri, 14 Jun 2002 12:25:04 -0400 Organization: Arius, Inc Lines: 81 Message-ID: <3D0A18E0.E567931A@yahoo.com> References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbnZbakKJU8GI32B2AC2izBW/GiY2/1fF05Gra5ByuubEQeNFZld+Z9 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 14 Jun 2002 16:25:12 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18453 I won't argue that any of your recommendations are bad, but they don't play together that I can tell. In one place you say that a cap with a SRF of 7 MHz is not good at 150 MHz which will require another cap with an SRF of 150 MHz. Later you say that this will cause a resonance somewhere in the middle so you try to keep the SRFs within a decade. John_H wrote: > below. One graph I'm looking at shows an SRF of about 7MHz for a 1uF 1206. The > impedance at 7MHz is about 0.1 Ohm each. The impedance drops to 1ohm around 250kHz and > 150MHz. While these values aren't bad, consider the current demands for 150MHz: 1/12 > Ohm (12 1uF caps in parallel, ignoring other parasitics for the moment) will keep the > voltage tolerance within 100mV for 1.2A surges. Maybe this is sufficient, but one cap > with an SRF around 150MHz would give you performance nearly as good at 150MHz. The 7MHz > frequencies. The caps need to be selected with a nice "spread" across the frequencies > you're working with. An SRF at 1MHz and another at 100MHz will actually give you > problems - a resonance - at 10MHz, reducing the effects of even the one type of > capacitor. If the SRF values are kept somewhat close, the resonance shouldn't be a big > issue (evaluate "somewhat?" I don't have a good value to suggest, but a decade is well > beyond what I'd like to use). My clock frequency is a major design consideration. The As you say, you are looking to keep the impedance below a given value across a wide range of frequencies. If we use your example, you can use 12 caps each with 1 ohm and get 1/12 ohms keeping the voltage noise below 100 mV with up to 1.2 Amp surges. My rational for matching caps to pins is based on the idea the the pin is the limiting impedance and resistance element. The pin sets the limit on the current a chip can draw and the surges that can be supported. The current is split among enough pins to keep each pin current below this threshold. Matching caps to pins then matches impedance to the individual power points, i.e. a chip with 4 power pins will draw about 10 times less current than one with 40 power pins and so needs 10 times fewer caps. Or just consider that the current surge in a single pin will always be supplied by the cap with it. > The chip needs very low impedance to ground. If you can't mount your cap on the same > side of the board as the chip, you have to go through a via anyway, encountering loop > inductance. If you can mount the cap on the same side of the board but have to use > more track to connect, the narrow line gives you loop inductance. When you have the cap > and the pins both connected to a plane - even the swiss cheese - the inductance is > manageable. One cap per power/ground pin pair isn't helping out much except for > paralleling the impedances. The issue of connecting the caps to the pins is not a bad as you make it. If you connect the chips to the power planes you use vias, when you connect caps to the power planes you use vias, so the situation is no different than connecting the caps directly to the chip pins. This can use a single via per pin rather than the two vias with the other approach and add less parasitic inductance. In the many discussions here about this issue, one person has pointed out that if you do a detailed analysis of the impedances, currents and frequencies, you will find that the power plane does most of the decoupling at the frequencies you really care about (harmonics > 400 MHz). So often the best caps you use are really just providing bulk capacitance. Some day I will build one of our boards with no decoupling caps and see how well it works. Then if needed I will add them a few at a time to see what it really takes to make it work. I think the bottom line is that this is largely voodoo and a little experimentation will replace a lot of analysis. Now if I only had a temperature chamber to do the testing in since I believe this is exacerbated by cold. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3D0A2898.5C4130F@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 15 Date: Fri, 14 Jun 2002 17:32:08 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1024075928 192.65.17.17 (Fri, 14 Jun 2002 11:32:08 MDT) NNTP-Posting-Date: Fri, 14 Jun 2002 11:32:08 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18448 rickman wrote: > I won't argue that any of your recommendations are bad, but they don't > play together that I can tell. In one place you say that a cap with a > SRF of 7 MHz is not good at 150 MHz which will require another cap with > an SRF of 150 MHz. Later you say that this will cause a resonance > somewhere in the middle so you try to keep the SRFs within a decade. Spot coverage without consideration for the whole picture will introduce potential problems; I didn't intend to recommend adding a single cap to the dozen with the low SRF. If the SRFs are distributed, the coverage is superb. I was trying to point out that a single cap can do the work of a dozen when you're far enough away from those dozen caps' SRF. It could be a mistake to only add the one cap at the higher SRF to complement the dozen. It would be more effective to have fewer caps across the frequency range than a quantity of single value caps. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Mon, 17 Jun 2002 00:19:56 -0400 Organization: Arius, Inc Lines: 49 Message-ID: <3D0D636C.B9610F06@yahoo.com> References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> <3D0A2898.5C4130F@mail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbK3tTDr3PDhSAOgN8Ek6VfrhNwes5ZJUt7IuV14F6eHJEdTat8RfM/ X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 17 Jun 2002 04:19:37 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18505 John_H wrote: > > rickman wrote: > > > I won't argue that any of your recommendations are bad, but they don't > > play together that I can tell. In one place you say that a cap with a > > SRF of 7 MHz is not good at 150 MHz which will require another cap with > > an SRF of 150 MHz. Later you say that this will cause a resonance > > somewhere in the middle so you try to keep the SRFs within a decade. > > Spot coverage without consideration for the whole picture will introduce potential problems; > I didn't intend to recommend adding a single cap to the dozen with the low SRF. If the SRFs > are distributed, the coverage is superb. I was trying to point out that a single cap can do > the work of a dozen when you're far enough away from those dozen caps' SRF. It could be a > mistake to only add the one cap at the higher SRF to complement the dozen. It would be more > effective to have fewer caps across the frequency range than a quantity of single value caps. But how do you deal with the anti resonance? One of the other posts gives a link to a lengthly discussion of power supply bypassing and shows how using caps with different SRFs gives a HIGHER impedance at points between the SRFs. Seems to me that it can be very tricky to get this right. The other issue I have is with the use of 1206 caps for bypassing. Size is one parameter that does affect impedance at high frequencies, unlike capacitance. So why use a 1 uF cap in a 1206 package with a low SRF when a 0.1 uF cap in an 0603 package will work better at all frequencies above the SRF? I don't think the freqs much below SRF are important for these caps. If your clocks are above 40 MHz, for example, then your switching noise will start at 80 MHz and go well up beyond 500 MHz. The lower frequency noise by contrast is small and will be dealt with by the bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So the band of interest is covered. Am I missing something? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: allan_herriman.hates.spam@agilent.com (Allan Herriman) Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Mon, 17 Jun 2002 10:13:03 GMT Organization: Agilent Technologies Lines: 64 Message-ID: <3d0db20f.26023780@netnews.agilent.com> References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> <3D0A2898.5C4130F@mail.com> <3D0D636C.B9610F06@yahoo.com> NNTP-Posting-Host: cswreg.cos.agilent.com X-Trace: cswtrans.cos.agilent.com 1024308785 19728 130.29.154.45 (17 Jun 2002 10:13:05 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Mon, 17 Jun 2002 10:13:05 +0000 (UTC) X-Newsreader: Forte Free Agent 1.21/32.243 Cache-Post-Path: cswreg.cos.agilent.com!unknown@hpiw0398.aus.agilent.com X-Cache: nntpcache 2.3.3 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18490 On Mon, 17 Jun 2002 00:19:56 -0400, rickman wrote: >John_H wrote: >> >> rickman wrote: >> >> > I won't argue that any of your recommendations are bad, but they don't >> > play together that I can tell. In one place you say that a cap with a >> > SRF of 7 MHz is not good at 150 MHz which will require another cap with >> > an SRF of 150 MHz. Later you say that this will cause a resonance >> > somewhere in the middle so you try to keep the SRFs within a decade. >> >> Spot coverage without consideration for the whole picture will introduce potential problems; >> I didn't intend to recommend adding a single cap to the dozen with the low SRF. If the SRFs >> are distributed, the coverage is superb. I was trying to point out that a single cap can do >> the work of a dozen when you're far enough away from those dozen caps' SRF. It could be a >> mistake to only add the one cap at the higher SRF to complement the dozen. It would be more >> effective to have fewer caps across the frequency range than a quantity of single value caps. > >But how do you deal with the anti resonance? One of the other posts >gives a link to a lengthly discussion of power supply bypassing and >shows how using caps with different SRFs gives a HIGHER impedance at >points between the SRFs. Seems to me that it can be very tricky to get >this right. There are two mechanisms for reducing the impedance peak at "anti resonance" : 1. Have some loss. The impedance only goes to infinity in an ideal lossless system. In real life you have a load (which looks a bit like a shunt resistor) and the capacitors have ESR, so the impedance peaks are much lower. 2. Keep the ratio of the capacitor values down. I have heard that 10:1 (e.g. 100n, 10n, 1n, 100p) can give adequate results. I have read papers that used lower ratios though (e.g. E3 series, 10, 4.7, 2.2 etc.). A lower ratio will produce lower peaks for a given amount of loss. (I just said that - I don't have a proof.) You can model both effects quite easily in Spice. But getting accurate values for the parasitic parameters can be tricky. >The other issue I have is with the use of 1206 caps for bypassing. Size >is one parameter that does affect impedance at high frequencies, unlike >capacitance. So why use a 1 uF cap in a 1206 package with a low SRF >when a 0.1 uF cap in an 0603 package will work better at all frequencies >above the SRF? I don't think the freqs much below SRF are important for >these caps. If your clocks are above 40 MHz, for example, then your >switching noise will start at 80 MHz and go well up beyond 500 MHz. The >lower frequency noise by contrast is small and will be dealt with by the >bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So >the band of interest is covered. > >Am I missing something? Most tantalums and OS-CONs that I've used havn't been effective much above 1MHz, so you need those 1u ceramics to fill the gap. (Either that, or you need a lot of 100n caps - but you probably need a lot of them anyway.) Regards, Allan. ###### From: John_H Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Mon, 17 Jun 2002 07:15:05 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3D0DEEE9.CE1507BD@mail.com> X-Mailer: Mozilla 4.73 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> <3D0A2898.5C4130F@mail.com> <3D0D636C.B9610F06@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 68 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out.nuthinbutnews.com!propagator-sterling!news-in.nuthinbutnews.com!feed.textport.net!sn-xit-04!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18503 rickman wrote: > > But how do you deal with the anti resonance? One of the other posts > gives a link to a lengthly discussion of power supply bypassing and > shows how using caps with different SRFs gives a HIGHER impedance at > points between the SRFs. Seems to me that it can be very tricky to get > this right. "Anti resonance" isn't a problem is the SRFs are "close enough." In the same sense that two 1uF caps with 3% differences in SRFs won't give you a poor impedance at the 1.5% midpoint, in caps with values where the inductance (for the low SRF) and capacitance (for the high SRF) are not the predominant part of the impedance, the ESR "bottom" will allow a clean transition. If you have to build an absolute minimum decoupling scheme, simulation is your friend. > The other issue I have is with the use of 1206 caps for bypassing. Size > is one parameter that does affect impedance at high frequencies, unlike > capacitance. So why use a 1 uF cap in a 1206 package with a low SRF > when a 0.1 uF cap in an 0603 package will work better at all frequencies > above the SRF? I don't think the freqs much below SRF are important for > these caps. If your clocks are above 40 MHz, for example, then your > switching noise will start at 80 MHz and go well up beyond 500 MHz. The > lower frequency noise by contrast is small and will be dealt with by the > bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > the band of interest is covered. > > Am I missing something? All you are missing is that I pulled the 1206 curves for illustration from a graph comparing different caps. I didn't try to suggest any particular bypassing scheme in this thread but have been trying to talk about the mess of decoupling generically. Look at the impedance curves of your caps. Look at your *impedance* needs across the frequencies based on you *current draw* at those frequencies, usually the response to worst case time-domain current fluctuations at the system clock rate. I haven't spoken about power supply response time here which is also a large part of the lower frequency response. The original question was what to do about a design with *no room* for more caps. While I do advocate smaller packages for lower impedances, I don't suggest that the costs for "special" caps are necessarily worth the advantage. Package costs for an 0603 isn't much different than that for a 1206. An 0306 package is an even better consideration for comparable capacitance but this style of cap isn't terribly common. You could go to 0201 caps but the bulk capacitance can't hit as high a value and many people 1) don't like to mix cap sizes in their manufacturing and 2) don't want to deal with devices below a "manageable" size. Smaller is (typically) better. If there is virtually no board space left for decoupling, a better decoupling scheme could be implemented with some unusual - and costly - alternative to two-terminal discreetes. If you can develop a good decoupling methodology with the less expensive alternatives, do it! > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3D0E2D50.C7589606@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> <3D0A2898.5C4130F@mail.com> <3D0D636C.B9610F06@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 37 Date: Mon, 17 Jun 2002 19:41:20 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1024339287 62.254.210.251 (Mon, 17 Jun 2002 19:41:27 BST) NNTP-Posting-Date: Mon, 17 Jun 2002 19:41:27 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newspeer1-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18480 Falk Brunner wrote: > "rickman" schrieb im Newsbeitrag > these caps. If > your clocks are > > > above 40 MHz, for example, then your > > switching noise will start at 80 MHz and go well up beyond 500 MHz. The > > lower frequency noise by contrast is small and will be dealt with by the > > bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > > the band of interest is covered. > > Warning, be carefull. > The clock speed is NOT the thing that matters. Its the switching speed of > the device. The FlipFlops will switch @ 1 MHz just as fast as @ 100 MHz. The > decoupling must handle the same ammout of work (regarding the high speed > decoupling, not low speed) > > -- > MfG > Falk This subject comes up regularly and, although there's a fair amount of light, there's also quite a lot of heat. Does anyone know of any experimental [looking at the power/gnd pins of an FPGA/ASIC] or IBIS/SPICE modelling of this stuff with a real PCB, real FPGA doing its thing, and with real life Cap models ? Lets say a heavy example: e.g. a burst of 8x72-bit words with alternating all 1's & all 0's to a DDR DRAM clocking @ 133MHz and all the data pins are on the same ``side'' [maybe even the same bank] of the FPGA. ... then do the same modelling with all the Caps removed. ###### From: "cfk" Newsgroups: comp.arch.fpga References: <1023706297.365340@turtle.ru.ac.za> <3D076F98.280FB310@yahoo.com> <3D07813B.46CF94AB@mail.com> <3D08C10B.E26EAA6D@yahoo.com> <3D08D2D0.5C243B54@mail.com> <3D0A18E0.E567931A@yahoo.com> <3D0A2898.5C4130F@mail.com> <3D0D636C.B9610F06@yahoo.com> <3d0db20f.26023780@netnews.agilent.com> Subject: Re: Power supply caps on PCB Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: NNTP-Posting-Host: 64.163.39.188 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1024537687 ST000 64.163.39.188 (Wed, 19 Jun 2002 21:48:07 EDT) NNTP-Posting-Date: Wed, 19 Jun 2002 21:48:07 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: SCSYQNONVRWEBFH[OZK@_TDAYZOZ@GXOXB]T]_MIJQR@EPIB_VUKAH_[MTX\IS[K[NGYJJFNOFZR_G[BUNTAOQLFE^TEHRPI]PZZRP_BMDSFQFL_]CBHXRWCMDCUZAZN@D_AKMNLEI]MWHCSXL^]NNC__CZFGSGHYYXWPFG@SCAVA]\FT\@B\RDGENSUQS^M Date: Thu, 20 Jun 2002 01:48:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!netnews.com!nntp.abs.net!uunet!dca.uu.net!ash.uu.net!prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!d1adee5f!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18592 > > >The other issue I have is with the use of 1206 caps for bypassing. Size > >is one parameter that does affect impedance at high frequencies, unlike > >capacitance. So why use a 1 uF cap in a 1206 package with a low SRF > >when a 0.1 uF cap in an 0603 package will work better at all frequencies > >above the SRF? I don't think the freqs much below SRF are important for > >these caps. If your clocks are above 40 MHz, for example, then your > >switching noise will start at 80 MHz and go well up beyond 500 MHz. The > >lower frequency noise by contrast is small and will be dealt with by the > >bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > >the band of interest is covered. > > > >Am I missing something? > There is another issue also. Smaller packages, 0603 versus 1206 for instance, most likely will need a ceramic dielectric with a higher dielectric constant. NPO dielectric has the best RF characteristics of commonly used ceramic dielectrics. X7R is worse and Z5U is terrible. Try to get the highest capacitance with the highest quality of dielectric. That means, given two capacitors one in 1206 but NPO and the other in 0603 but X7R or Z5U, go with the NPO in the larger package. To confirm this, look at the curves of loss versus frequency of the ceramic dielectrics in the manufacturers data sheets sometime. Charles ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB Date: Thu, 20 Jun 2002 20:13:40 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <9o55huco95o2f894uu5kogotukajmorhdb@4ax.com> References: <1023706297.365340@turtle.ru.ac.za> X-Newsreader: Forte Agent 1.91/32.564 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 32 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!sn-xit-03!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18688 On Mon, 10 Jun 2002 12:57:14 +0200, "Noddy" wrote: >Hi, > >I know that one should place 0.1uF and 0.01uF caps on all power supply pins >on the FPGA... does this include both Vcco and Vccint, or can one get away >with just Vccint and then put only 0.1uF on Vcco. I am seriously running out >of room on my PCB, and increasing the PCB size is not an option! > >adrian > > I've done some pretty serious TDR testing of multilayer boards with different bypass caps installed. Most of my boards have a solid ground plane and a solid Vcc plane separated by a thin (0.005 inch or so) dielectric. Sometimes the power plane is chopped up: say, +5 mostly but a few islands of 3.3 or whatever for FPGAs. I generally use four bypass caps *per FPGA*. At high frequencies, the planes themselves are the cap, and the ceramic caps just help out at lower frequencies and are the gross charge storage reservoir. Actual cap placement doesn't seem to matter as long as the planes are solid, the dielectric is thin, and the caps are somewhere - basicly anywhere - on the planes. 0.1 uf 0805 or 0603 is probably as good as any. I've done lots of boards with way too many bypass caps, but so far I've never done a multilayer board that had too few. John ###### Message-ID: <3D134651.4E9D4D56@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Power supply caps on PCB References: <1023706297.365340@turtle.ru.ac.za> <9o55huco95o2f894uu5kogotukajmorhdb@4ax.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 38 Date: Fri, 21 Jun 2002 15:29:22 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1024673362 192.65.17.17 (Fri, 21 Jun 2002 09:29:22 MDT) NNTP-Posting-Date: Fri, 21 Jun 2002 09:29:22 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18689 Have you done EMI compliance testing on your designs? I'm wondering about the link between under/over bypassed designs and emissions. John Larkin wrote: > On Mon, 10 Jun 2002 12:57:14 +0200, "Noddy" > wrote: > > >Hi, > > > >I know that one should place 0.1uF and 0.01uF caps on all power supply pins > >on the FPGA... does this include both Vcco and Vccint, or can one get away > >with just Vccint and then put only 0.1uF on Vcco. I am seriously running out > >of room on my PCB, and increasing the PCB size is not an option! > > > >adrian > > > > > > I've done some pretty serious TDR testing of multilayer boards with > different bypass caps installed. Most of my boards have a solid ground > plane and a solid Vcc plane separated by a thin (0.005 inch or so) > dielectric. Sometimes the power plane is chopped up: say, +5 mostly > but a few islands of 3.3 or whatever for FPGAs. I generally use four > bypass caps *per FPGA*. At high frequencies, the planes themselves are > the cap, and the ceramic caps just help out at lower frequencies and > are the gross charge storage reservoir. Actual cap placement doesn't > seem to matter as long as the planes are solid, the dielectric is > thin, and the caps are somewhere - basicly anywhere - on the planes. > > 0.1 uf 0805 or 0603 is probably as good as any. > > I've done lots of boards with way too many bypass caps, but so far > I've never done a multilayer board that had too few. > > John