From: Michael Boehnel Newsgroups: comp.arch.fpga Subject: FPGA destruction possible? Date: Mon, 03 Jun 2002 12:39:45 +0200 Organization: ITI Lines: 13 Message-ID: <3CFB4771.F64A2370@iti.tu-graz.ac.at> NNTP-Posting-Host: fitipc074.tu-graz.ac.at Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fstgss02.tu-graz.ac.at 1023100494 18 129.27.146.74 (3 Jun 2002 10:34:54 GMT) X-Complaints-To: news@TUGraz.at NNTP-Posting-Date: 3 Jun 2002 10:34:54 GMT X-Mailer: Mozilla 4.71 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newscore.univie.ac.at!aconews-feed.univie.ac.at!news.tu-graz.ac.at!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18044 Hello! Is it possible to kill (thermically destroy) an FPGA by a highly optimized design (hand-placed; high-density; litte unrelated logic) assuming that interface lines are OK/room temperature? Did anybody observe such a behavior? Regards Michael ###### From: Prager Roman Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Organization: FREQUENTIS Lines: 23 Distribution: world Message-ID: References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> User-Agent: tin/1.4.1-19991201 ("Polish") (UNIX) (Linux/2.2.17 (i686)) Date: Mon, 03 Jun 2002 13:01:13 GMT NNTP-Posting-Host: 213.47.210.150 X-Complaints-To: abuse@news.chello.at X-Trace: news.chello.at 1023109273 213.47.210.150 (Mon, 03 Jun 2002 15:01:13 CEST) NNTP-Posting-Date: Mon, 03 Jun 2002 15:01:13 CEST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!newsrouter.chello.at!news.chello.at.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18050 Michael Boehnel wrote: > Hello! > Is it possible to kill (thermically destroy) an FPGA by a highly > optimized design (hand-placed; high-density; litte unrelated logic) > assuming that interface lines are OK/room temperature? Of course it is possible, at least with higher integrated FPGAs. Modern FPGAs can easily integrate the switching power for a few Gigabit per second, even if not 'highly optimized'. So the definitely need some cooling. Without cooling they go the same way like any other highspeed processor. Roman > Did anybody observe such a behavior? > Regards > Michael ###### From: johne@vcd.hp.com (John Eaton) Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Date: 4 Jun 2002 00:48:37 GMT Organization: Hewlett Packard Vancouver Site Lines: 25 Message-ID: References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> NNTP-Posting-Host: hpvcljte.vcd.hp.com X-Trace: news.vcd.hp.com 1023151717 3340 15.252.35.41 (4 Jun 2002 00:48:37 GMT) X-Complaints-To: news@news.vcd.hp.com NNTP-Posting-Date: 4 Jun 2002 00:48:37 GMT X-Newsreader: TIN [version 1.2 PL2.9] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!news-west.eli.net!news.vcd.hp.com!johne Xref: chonsp.franklin.ch comp.arch.fpga:18094 Falk Brunner (Falk.Brunner@gmx.de) wrote: : Hmm, no. The IOs of FPGAs are really though guys, even a short for hours : doest damage them too much, I heard. : But for a medium sized (lets say 200k gates) FPGA, its hard to overheat them : with a normal design, unless you turn them into a 10.000 stage shift : register and clock them with 200 MHz. I did this with a Spartan-II 100, : draws ~2.7 W, gets real hot in a PQ208 but doesnt melt (at least not after : 30s of my testing) : With the big guys (1M gates++), there are good chances to fry the FPGA, : since power density is much bigger. I have it on good authority that connecting a 3.3 volt 1M gate part to a flakey connector that shorts I/O pads to 5 volts WILL destroy the FPGA. And in the true interest of science the folks that performed that little experiment then verified that it was reproduceable. John Eaton ###### From: Michael Boehnel Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Date: Tue, 04 Jun 2002 13:05:53 +0200 Organization: ITI Lines: 26 Message-ID: <3CFC9F11.FFAEB946@iti.tu-graz.ac.at> References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> NNTP-Posting-Host: fitipc074.tu-graz.ac.at Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fstgss02.tu-graz.ac.at 1023188473 12602 129.27.146.74 (4 Jun 2002 11:01:13 GMT) X-Complaints-To: news@TUGraz.at NNTP-Posting-Date: 4 Jun 2002 11:01:13 GMT X-Mailer: Mozilla 4.71 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!aconews-feed.univie.ac.at!news.tu-graz.ac.at!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18100 Hello, Falk! Falk Brunner wrote: > ;-)))) Nice phrase. (My design is too good for the technology nowadays ) > If you have a good (optimized) design, wouldnt it dissipate LESS power?? Depends on what you optimize. If you optimize for performance (higher clock frequency) and FPGA utilization (higher density) you inevitable dissipate much power. And FPGAs (in opposition to ASICs) do not provide low-power techniques such as voltage scaling. > Hmm, no. The IOs of FPGAs are really though guys, even a short for hours > doest damage them too much, I heard. > But for a medium sized (lets say 200k gates) FPGA, its hard to overheat them > with a normal design, unless you turn them into a 10.000 stage shift > register and clock them with 200 MHz. I did this with a Spartan-II 100, > draws ~2.7 W, gets real hot in a PQ208 but doesnt melt (at least not after > 30s of my testing) 30s is not a very long testing time :-) Regards, Michael ###### Message-ID: <3CFCB668.877D8D09@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 55 Date: Tue, 04 Jun 2002 12:42:30 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1023194550 68.15.41.165 (Tue, 04 Jun 2002 08:42:30 EDT) NNTP-Posting-Date: Tue, 04 Jun 2002 08:42:30 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.freenet.de!newsfeed.stueberl.de!cox.net!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18087 Falk Brunner wrote: > "Michael Boehnel" schrieb im Newsbeitrag > news:3CFB4771.F64A2370@iti.tu-graz.ac.at... > > Hello! > > > > Is it possible to kill (thermically destroy) an FPGA by a highly > > optimized design (hand-placed; high-density; litte unrelated logic) > > ;-)))) Nice phrase. (My design is too good for the technology nowadays ) > If you have a good (optimized) design, wouldnt it dissipate LESS power?? Floorplanning does reduce power for a given clock rate, however the decreased propagation times can lead to higher possible clock rates. It is possible to overheat the larger parts with a dense high performance design. The average user won't get to that point though. I have one design on the bench that has to have heatsinks on V2000E's, but that is a design that is being internally clocked at 160 MHz, is 85% full, and has some 70% of the LUTs used as SRL16's. The bottom line is that it is possible to make the bigger parts pretty hot, but you'll have to work at it to do it. > > > > assuming that interface lines are OK/room temperature? > > > > Did anybody observe such a behavior? > > Hmm, no. The IOs of FPGAs are really though guys, even a short for hours > doest damage them too much, I heard. > But for a medium sized (lets say 200k gates) FPGA, its hard to overheat them > with a normal design, unless you turn them into a 10.000 stage shift > register and clock them with 200 MHz. I did this with a Spartan-II 100, > draws ~2.7 W, gets real hot in a PQ208 but doesnt melt (at least not after > 30s of my testing) > With the big guys (1M gates++), there are good chances to fry the FPGA, > since power density is much bigger. > > -- > MfG > Falk -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3CFCB71F.9A543939@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> <3CFC9F11.FFAEB946@iti.tu-graz.ac.at> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 32 Date: Tue, 04 Jun 2002 12:45:34 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1023194734 68.15.41.165 (Tue, 04 Jun 2002 08:45:34 EDT) NNTP-Posting-Date: Tue, 04 Jun 2002 08:45:34 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!newspeer1-gui.server.ntli.net!ntli.net!cox.net!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18081 I have seen floorplanning and design optimization for performance reduce power fairly consistently by around 15-20%. Of course, it also reduces propagation delays which means you can turn the clock up, losing any gains on overall power. Where you do save is power per transition. Michael Boehnel wrote: > Hello, Falk! > > Falk Brunner wrote: > > > ;-)))) Nice phrase. (My design is too good for the technology nowadays ) > > If you have a good (optimized) design, wouldnt it dissipate LESS power?? > > Depends on what you optimize. If you optimize for performance (higher clock > frequency) and FPGA utilization (higher density) you inevitable dissipate much > power. And FPGAs (in opposition to ASICs) do not provide low-power techniques > such as voltage scaling. > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: Michael Boehnel Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Date: Tue, 04 Jun 2002 16:52:40 +0200 Organization: ITI Lines: 44 Message-ID: <3CFCD438.185BA55@iti.tu-graz.ac.at> References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> <3CFCB668.877D8D09@andraka.com> NNTP-Posting-Host: fitipc074.tu-graz.ac.at Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fstgss02.tu-graz.ac.at 1023202081 633 129.27.146.74 (4 Jun 2002 14:48:01 GMT) X-Complaints-To: news@TUGraz.at NNTP-Posting-Date: 4 Jun 2002 14:48:01 GMT X-Mailer: Mozilla 4.71 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!colt.net!peernews2.colt.net!fr.colt.net!isdnet!newscore.univie.ac.at!aconews-feed.univie.ac.at!news.tu-graz.ac.at!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18098 First, thanks to all for the interesting feedbacks!! Ray Andraka wrote: > Floorplanning does reduce power for a given clock rate, however the decreased > propagation times can lead to higher possible clock rates. It is possible to > overheat the larger parts with a dense high performance design. The average > user won't get to that point though. I have one design on the bench that has to > have heatsinks on V2000E's, but that is a design that is being internally > clocked at 160 MHz, is 85% full, and has some 70% of the LUTs used as SRL16's. > The bottom line is that it is possible to make the bigger parts pretty hot, but > you'll have to work at it to do it. I am currently investigating a switch design which uses many LUTs as SRL16's, target XCV-600E-6 (package HQ240). 86% of LUT used (25% as SRL16). 99% of slices used, unrelated logic about 10%. But clock rate is below 50 MHz. So the conditions are much lighter than you describe. But the design operates permanently with maximum throughput (about GBit/s). What I am more concerned about than by optimization is what techniques and (software)tools to use to detect hot spots. With a DSP I can be sure, that if no overclocking takes place, no special care has to be taken whatever program I use. The DSP is designed for a special operating frequency (@ room temperature). The temperature problem is left to the DSP manufacturer and is tested by benchmarks. Further, temperature can be measured and the processor halted in case of overtemperature. How can FPGA manufacturers guarantee me, that no hot-spots destroy the device? Is there something such as a worst case design which is used to test the FPGA? AFAIK power estimation tools (such as the one provided with Xilinx Fnd ISE) only estimate the average power and can not be used to model thermal behavior for certain regions precisely (please correct me if I am wrong). Is it enough to take the average power to dimension the heat sink or can single hot spots still damage the silicon? Is the only way to take a thermal camera and a radiation thermometer to measure the prototype? Maybe for many designs, thermal conditions are not an issue. But as FPGA designs get smaller and faster it could be for more users. Regards, Michael ###### Message-ID: <3CFD12EE.840A8204@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 26 Date: Tue, 04 Jun 2002 20:20:14 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1023218417 62.254.210.251 (Tue, 04 Jun 2002 20:20:17 BST) NNTP-Posting-Date: Tue, 04 Jun 2002 20:20:17 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newspeer1-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18070 Falk Brunner wrote: > "John Eaton" schrieb im Newsbeitrag > news:adh2p5$38c$1@news.vcd.hp.com... > > > > I have it on good authority that connecting a 3.3 volt 1M gate part to a > > flakey connector that shorts I/O pads to 5 volts WILL destroy the FPGA. > > > > > > And in the true interest of science the folks that performed that little > > experiment then verified that it was reproduceable. > > So they are real scientists. They have reproducable results ;-) > More serious, I think overvoltage was not the question here, was it? > > -- > MfG > Falk This is a different type of destruction than overheating the die. If the "experimental" connections were to the 5V power source then 5 - clamp diode drop - VCCO = 5 - 0.7 - 3.3 = 1V across sweet FA resistance => melted IO pads ... unless the bond wires acted as fuses first. ###### Message-ID: <3CFD3DE7.77B6AC79@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> <3CFCB668.877D8D09@andraka.com> <3CFCD438.185BA55@iti.tu-graz.ac.at> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 60 Date: Tue, 04 Jun 2002 22:20:35 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1023229235 68.15.41.165 (Tue, 04 Jun 2002 18:20:35 EDT) NNTP-Posting-Date: Tue, 04 Jun 2002 18:20:35 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed1.cidera.com!Cidera!netnews.com!nntp.abs.net!news-out.visi.com!hermes.visi.com!cox.net!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18091 At clock rates below 50 MHz in a 600E, I doubt you will have any problems. Michael Boehnel wrote: > First, thanks to all for the interesting feedbacks!! > > Ray Andraka wrote: > > > Floorplanning does reduce power for a given clock rate, however the decreased > > propagation times can lead to higher possible clock rates. It is possible to > > overheat the larger parts with a dense high performance design. The average > > user won't get to that point though. I have one design on the bench that has to > > have heatsinks on V2000E's, but that is a design that is being internally > > clocked at 160 MHz, is 85% full, and has some 70% of the LUTs used as SRL16's. > > The bottom line is that it is possible to make the bigger parts pretty hot, but > > you'll have to work at it to do it. > > I am currently investigating a switch design which uses many LUTs as SRL16's, target > XCV-600E-6 (package HQ240). > 86% of LUT used (25% as SRL16). 99% of slices used, unrelated logic about 10%. But > clock rate is below 50 MHz. So the conditions are much lighter than you describe. > But the design operates permanently with maximum throughput (about GBit/s). > > What I am more concerned about than by optimization is what techniques and > (software)tools to use to detect hot spots. With a DSP I can be sure, that if no > overclocking takes place, no special care has to be taken whatever program I use. > The DSP is designed for a special operating frequency (@ room temperature). The > temperature problem is left to the DSP manufacturer and is tested by benchmarks. > Further, temperature can be measured and the processor halted in case of > overtemperature. > > How can FPGA manufacturers guarantee me, that no hot-spots destroy the device? Is > there something such as a worst case design which is used to test the FPGA? AFAIK > power estimation tools (such as the one provided with Xilinx Fnd ISE) only estimate > the average power and can not be used to model thermal behavior for certain regions > precisely (please correct me if I am wrong). Is it enough to take the average power > to dimension the heat sink or can single hot spots still damage the silicon? > > Is the only way to take a thermal camera and a radiation thermometer to measure the > prototype? > > Maybe for many designs, thermal conditions are not an issue. But as FPGA designs get > smaller and faster it could be for more users. > > Regards, > > Michael -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: johne@vcd.hp.com (John Eaton) Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Date: 5 Jun 2002 16:04:09 GMT Organization: Hewlett Packard Vancouver Site Lines: 36 Message-ID: References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> NNTP-Posting-Host: hpvcljte.vcd.hp.com X-Trace: news.vcd.hp.com 1023293049 12690 15.252.35.41 (5 Jun 2002 16:04:09 GMT) X-Complaints-To: news@news.vcd.hp.com NNTP-Posting-Date: 5 Jun 2002 16:04:09 GMT X-Newsreader: TIN [version 1.2 PL2.9] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!news-west.eli.net!news.vcd.hp.com!johne Xref: chonsp.franklin.ch comp.arch.fpga:18166 Falk Brunner (Falk.Brunner@gmx.de) wrote: : "John Eaton" schrieb im Newsbeitrag : news:adh2p5$38c$1@news.vcd.hp.com... : > : > I have it on good authority that connecting a 3.3 volt 1M gate part to a : > flakey connector that shorts I/O pads to 5 volts WILL destroy the FPGA. : > : > : > And in the true interest of science the folks that performed that little : > experiment then verified that it was reproduceable. : So they are real scientists. They have reproducable results ;-) : More serious, I think overvoltage was not the question here, was it? ------------------------------------------------- It was latch up. Some 3.3 volt outputs were shorted to +5 and sent the whole chip into melt down mode. We also have a new crop of software engineers who don't fully understand how to handle breadboards. You have to really babysit them and be ready to kill the power the INSTANT you hear,see,smell,taste or feel anything odd. The new guys will power them up and then run back to their cube and log in remotely to a debug session. About 1/2 hour later somebody will walk by and ask them if they know that their breadboards on fire. John Eaton ###### From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> Subject: Re: FPGA destruction possible? Lines: 29 Organization: Virtual Computer Corporation X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.3018.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.3018.1300 Message-ID: NNTP-Posting-Host: 64.168.191.90 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1023296731 ST000 64.168.191.90 (Wed, 05 Jun 2002 13:05:31 EDT) NNTP-Posting-Date: Wed, 05 Jun 2002 13:05:31 EDT X-UserInfo1: FKPGG_SEPRR[RRP[OBCD^VX@WB]^PCPDLXUNNHXIJYWZUYICD^RAQBKZQTZTX\_I[^G_KGFNON[ZOE_AZNVO^\XGGNTCIRPIJH[@RQKBXLRZ@CD^HKANYVW@RLGEZEJN@\_WZJBNZYYKVIOR]T]MNMG_Z[YVWSCH_Q[GPC_A@CARQVXDSDA^M]@DRVUM@RBM Date: Wed, 05 Jun 2002 17:05:31 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!netnews.com!nntp.abs.net!newshub.northeast.verio.net!verio!newspeer.monmouth.com!newscon02.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!2ac7f5fa!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18150 There was a paper on FPGA viruses at FPL in 99 (I think) that went into this kind of thing.. One of the best way to do this is to build and bunch of ring oscillators. Just link a bunch of inverters in a circle and you'll get a good chip fryer. When we were building boards with the 6200 part one customer did just that with a home grown tool, and blew up the device in no time. One of the cases where to much knowledge can hurt you when it come to having the fully documented bit stream information. Of course later on that tool was able to evolve the "best" 16 bit sorter. Steve Casselman "Michael Boehnel" wrote in message news:3CFB4771.F64A2370@iti.tu-graz.ac.at... > Hello! > > Is it possible to kill (thermically destroy) an FPGA by a highly > optimized design (hand-placed; high-density; litte unrelated logic) > assuming that interface lines are OK/room temperature? > > Did anybody observe such a behavior? > > Regards > > Michael > > ###### Message-ID: <3CFE555F.9A026E43@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 46 Date: Wed, 05 Jun 2002 19:15:59 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1023300964 62.254.210.251 (Wed, 05 Jun 2002 19:16:04 BST) NNTP-Posting-Date: Wed, 05 Jun 2002 19:16:04 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.stueberl.de!newspeer1-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:18143 John Eaton wrote: > Falk Brunner (Falk.Brunner@gmx.de) wrote: > : "John Eaton" schrieb im Newsbeitrag > : news:adh2p5$38c$1@news.vcd.hp.com... > : > > : > I have it on good authority that connecting a 3.3 volt 1M gate part to a > : > flakey connector that shorts I/O pads to 5 volts WILL destroy the FPGA. > : > > : > > : > And in the true interest of science the folks that performed that little > : > experiment then verified that it was reproduceable. > > : So they are real scientists. They have reproducable results ;-) > : More serious, I think overvoltage was not the question here, was it? > > ------------------------------------------------- > > It was latch up. Some 3.3 volt outputs were shorted to +5 and sent the > whole chip into melt down mode. > > We also have a new crop of software engineers who don't fully understand > how to handle breadboards. You have to really babysit them and be ready to > kill the power the INSTANT you hear,see,smell,taste or feel anything odd. > > The new guys will power them up and then run back to their cube and log > in remotely to a debug session. About 1/2 hour later somebody will walk > by and ask them if they know that their breadboards on fire. > > John Eaton Hmmm! Perhaps as part of their training they should have the breadboard in their cubes until they can convince management that they can distinguish between the smells of (a) expensive FPGAs reverting to melted sand + burning FR4 epoxy, (b) newly arrived pizza. Dousing the cube with a dry power extinguisher on event (a), if repeated often enough, should have the required effect - in a Pavlovian kind of way [the pizza will taste *really* bad]. They might, of course, reply that its not their fault as the VC/C++ debugger doesn't seem to have a ``breadboard on fire'' trap/breakpoint whereas it does, so I've been lead to believe, have a ``next pizza'' timer. ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: FPGA destruction possible? Date: Thu, 06 Jun 2002 07:58:37 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3CFB4771.F64A2370@iti.tu-graz.ac.at> X-Complaints-To: newsabuse@supernews.com Lines: 18 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:18176 >It was latch up. Some 3.3 volt outputs were shorted to +5 and sent the >whole chip into melt down mode. I used to think that latch up was instant death for a chip. But recently I've been working with a chip/board/setup that latches up frequently enough that I'm getting an interesting education. The chip takes about 30 amps at 2.8 V. Usually the overcurrent trips, and everything is fine after a short timeout. Sometimes we have that jumpered off. The chip has a big heat sink, but not that big. It gets pretty hot if you leave it on for more than a few seconds. But it doesn't melt or smoke and runs again after it cools off. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.