From: angusthompson@hotmail.com (Angus Thompson) Newsgroups: comp.arch.fpga Subject: Routing in a 6200-like sea of gates Date: 22 May 2002 05:03:46 -0700 Organization: http://groups.google.com/ Lines: 17 Message-ID: <6f3a4943.0205220403.376ca445@posting.google.com> NNTP-Posting-Host: 128.16.6.124 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1022069026 18990 127.0.0.1 (22 May 2002 12:03:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 22 May 2002 12:03:46 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!iad-peer.news.verio.net!news.verio.net!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17771 Hi all, I have been thinking about using a simulated sea-of-gates FPGA architecture for some design experiments. I want to keep the architecture as simple as possible. I was thinking about using a sea of 4 input LUTs, each of the four inputs being driven by the output from one of the 4 surrounding LUTs, as I can easily map this to a real FPGA. However as there is only 1 layer of logic no signal can cross another, which really limits what combinational logic you can make. I understand the Xilinx 6200 had a similar architecture. I suppose the longer lines could be used to cross signals, but it doesn't seem reasonable to have such a serious limitation for an FPGA. Is there anyone out there who did designs with the 6200 that can tell me what I'm missing? Cheers, Angus ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Routing in a 6200-like sea of gates Date: Wed, 22 May 2002 11:12:28 -0700 Organization: Xilinx, Inc. Lines: 34 Message-ID: <3CEBDF8C.485C09F3@xilinx.com> References: <6f3a4943.0205220403.376ca445@posting.google.com> NNTP-Posting-Host: 149.199.34.29 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (Windows NT 5.0; U) X-Accept-Language: en To: Angus Thompson Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.usenet-edu.net!usenet-edu.net!proxad.net!wanadoo.fr!opentransit.net!cpk-news-hub1.bbnplanet.com!nycmny1-snh1.gtei.net!news.gtei.net!newsfeed.mathworks.com!wn3feed!wn2feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17683 Angus, I do not know what "turns you on". I personally would not be interested in experimenting with a dead architecture. The XC6200 is no longer available. It died for lack of commercial interest. There was a lot of academic interest, but that does not pay our bills :-(. So you an make theoretical experiments, but do not expect to be able to verify them on silicon, let alone extrapolate them to realistic hardware in the future. Just a friendly warning... Peter Alfke, Xilinx Applications ===================================== Angus Thompson wrote: > Hi all, > > I have been thinking about using a simulated sea-of-gates FPGA > architecture for some design experiments. I want to keep the > architecture as simple as possible. I was thinking about using a sea > of 4 input LUTs, each of the four inputs being driven by the output > from one of the 4 surrounding LUTs, as I can easily map this to a real > FPGA. However as there is only 1 layer of logic no signal can cross > another, which really limits what combinational logic you can make. > > I understand the Xilinx 6200 had a similar architecture. I suppose the > longer lines could be used to cross signals, but it doesn't seem > reasonable to have such a serious limitation for an FPGA. Is there > anyone out there who did designs with the 6200 that can tell me what > I'm missing? > > Cheers, Angus ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: Routing in a 6200-like sea of gates Date: Wed, 22 May 2002 19:31:52 +0000 (UTC) Organization: Unknown Lines: 21 Message-ID: References: <6f3a4943.0205220403.376ca445@posting.google.com> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1022095912 77373 128.32.247.226 (22 May 2002 19:31:52 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Wed, 22 May 2002 19:31:52 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub.sdsu.edu!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17747 In article <6f3a4943.0205220403.376ca445@posting.google.com>, Angus Thompson wrote: >I understand the Xilinx 6200 had a similar architecture. I suppose the >longer lines could be used to cross signals, but it doesn't seem >reasonable to have such a serious limitation for an FPGA. Is there >anyone out there who did designs with the 6200 that can tell me what >I'm missing? I think the 6200 had a few farther interconnects, but it was generally low. In order to be "safe" in the event of misconfiguration, all switching was muxes, so that it was impossible to create a configuration which would drive a wire both high and low. The net result was the interconnect was very poor and inflexible, and thus found little commercial interest. It got a lot of academic interest because the reconfiguration mechanisms were very powerful, and it was safe so a bad reconfiguration wouldn't burn the chip. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Routing in a 6200-like sea of gates Date: 22 May 2002 23:00:49 +0200 Organization: My own Private Self Lines: 62 Message-ID: <6ulmabdhj2.fsf@chonsp.franklin.ch> References: <6f3a4943.0205220403.376ca445@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1022101249 1244 10.0.3.2 (22 May 2002 21:00:49 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 22 May 2002 21:00:49 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:17789 nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) writes: > In article <6f3a4943.0205220403.376ca445@posting.google.com>, > Angus Thompson wrote: > >I understand the Xilinx 6200 had a similar architecture. Sort of. It had far more selection ability. It had 4 outputs (one to each direction) which could all be derived from inputs (one via processing element, the others just pass through switches. It also had 8 inputs (neighbor and long distance from each direction). - X1, X2, X3 are selected from Inputs N, S, E, W or the 4 longs - F is generated from X1, X2, X3 by processing element - Nout, Sout, Eout, Wout are selected from N, S, E, W or F > >I suppose the > >longer lines could be used to cross signals, but it doesn't seem > >reasonable to have such a serious limitation for an FPGA. Long lines were just for faster signal propagation. Crossing was done in the output 4 selection muxes. > >Is there > >anyone out there who did designs with the 6200 that can tell me what > >I'm missing? The XC62xx data sheet? I once found a copy at: http://www.vcc.com/Papers/6200.pdf VCC was once the manufacturer of an XC6216 based prototyping board. > low. In order to be "safe" in the event of misconfiguration, all > switching was muxes, so that it was impossible to create a > configuration which would drive a wire both high and low. This also reduced the amount of config bits memory. > The net result was the interconnect was very poor and inflexible, and > thus found little commercial interest. Looks like that to me also. The Atmel AT600 looks like a far more flexible SoG architecture. > It got a lot of academic interest because the reconfiguration > mechanisms were very powerful, and it was safe so a bad > reconfiguration wouldn't burn the chip. Not to mention, that the entire bitstream description was published in the data sheet. Academics like fully documented stuff, that gives them full flexibility of designing their systems from ground up. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domain