From: Stephanie McBader Newsgroups: comp.arch.fpga Subject: Bidirectional DONE? Date: Thu, 16 May 2002 15:13:36 +0200 Organization: Centro Servizi Interbusiness Lines: 20 Message-ID: <3CE3B080.CBAB2AEC@neuricam.com> NNTP-Posting-Host: host210-pool801687.interbusiness.it Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.72 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsmi-us.news.garr.it!newsbo.news.garr.it!NewsITBone-GARR!newsfeed.cineca.it!newsfeed.nettuno.it!server-b.cs.interbusiness.it!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17546 Hi, Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE pin is bidirectional. Does that mean that the logic configured inside the FPGA will be able to read it? i.e., would a controller implemented in the FPGA be able to read the value of DONE & say, remains in reset until DONE is asserted? Thanks! Stephanie McBader Researcher/Design Engineer NeuriCam S.p.A Via S M Maddalena 12 38100 Trento TN, Italy Tel: +39-0461-260552 Fax: +39-0461-260617 ###### From: "Joze Dedic" Newsgroups: comp.arch.fpga Subject: Re: Bidirectional DONE? Date: Thu, 16 May 2002 17:21:30 +0200 Organization: ARNES Lines: 31 Message-ID: References: <3CE3B080.CBAB2AEC@neuricam.com> NNTP-Posting-Host: lniv5.fe.uni-lj.si X-Trace: planja.arnes.si 1021562373 26950 193.2.66.101 (16 May 2002 15:19:33 GMT) X-Complaints-To: abuse@arnes.si NNTP-Posting-Date: Thu, 16 May 2002 15:19:33 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!kanja.arnes.si!planja.arnes.si!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17554 FPGA does not work until it is fully configured (i.e. until DONE is high) - until then all the output drivers are off, and all FFs are held in reset...This pin is used (probably only) because of (programmed) timing sequence after DONE is high (enable outputs, release set or reset...) have a nice day, jOc "Stephanie McBader" wrote in message news:3CE3B080.CBAB2AEC@neuricam.com... > Hi, > > Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE > pin is bidirectional. Does that mean that the logic configured inside > the FPGA will be able to read it? > > i.e., would a controller implemented in the FPGA be able to read the > value of DONE & say, remains in reset until DONE is asserted? > > Thanks! > > Stephanie McBader > Researcher/Design Engineer > NeuriCam S.p.A > Via S M Maddalena 12 > 38100 Trento TN, Italy > Tel: +39-0461-260552 > Fax: +39-0461-260617 > > ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Bidirectional DONE? Date: Thu, 16 May 2002 08:41:33 -0700 Organization: Xilinx Lines: 34 Message-ID: <3CE3D32C.1F877C05@xilinx.com> References: <3CE3B080.CBAB2AEC@neuricam.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.79 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17510 Stephanie, Internally, when in chains of FPGAs, the DONE pin of the master waits to see the DONE pin of the last slave go high (hence it is an input in that mode). Basically, no user logic can operate until DONE goes high, so I don't see why you need this. As soon as DONE goes high, all initial register values, FF states, BRAM contents, etc are all present, and on the next user supplied system logic clock, everything starts marching along. Austin Stephanie McBader wrote: > Hi, > > Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE > pin is bidirectional. Does that mean that the logic configured inside > the FPGA will be able to read it? > > i.e., would a controller implemented in the FPGA be able to read the > value of DONE & say, remains in reset until DONE is asserted? > > Thanks! > > Stephanie McBader > Researcher/Design Engineer > NeuriCam S.p.A > Via S M Maddalena 12 > 38100 Trento TN, Italy > Tel: +39-0461-260552 > Fax: +39-0461-260617 ###### From: "cfk" Newsgroups: comp.arch.fpga References: <3CE3B080.CBAB2AEC@neuricam.com> <3CE3D32C.1F877C05@xilinx.com> Subject: Re: Bidirectional DONE? Lines: 49 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: NNTP-Posting-Host: 64.163.39.188 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1021750746 ST000 64.163.39.188 (Sat, 18 May 2002 15:39:06 EDT) NNTP-Posting-Date: Sat, 18 May 2002 15:39:06 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: T[OUB]KDUCRQRW@YKBH\OQMAPJYRUWPHDY^L\UQHWIWDUWYADNVOPCKZBL\NX_KHV^GY[KVMG^ZPNHSCZNS[^UXFJVWYXVXKBH[XRWWBBDTN@AX\JSBVH]_@T\EKJHBMZ\_WZJFNRY]YWKSPED_U^NC\HSZ\WS[KEAYI@DO@\K@BP\LD[\GTMPLDFVU]ASJM Date: Sat, 18 May 2002 19:39:06 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!d1adee5f!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17650 Actually, I have a similar need, so let me pose the original posters question in a different way. It is sometimes necessary to have user logic initialize in a known state from power up. Perhaps the GSR signal might be more appropriate (I can see it used in some modules in unisim), but so far, I have been unable to get past "unresolved reference to GSR or glbl.GSR" either in my ISE or Modelsim. I have tried compiling glbl.v in (I am working in verilog) to no avail. So, how does one find a way to let some user code run once?? Charles "Austin Lesea" wrote in message news:3CE3D32C.1F877C05@xilinx.com... > Stephanie, > > Internally, when in chains of FPGAs, the DONE pin of the master waits to > see the DONE pin of the last slave go high (hence it is an input in that > mode). > > Basically, no user logic can operate until DONE goes high, so I don't see > why you need this. As soon as DONE goes high, all initial register > values, FF states, BRAM contents, etc are all present, and on the next > user supplied system logic clock, everything starts marching along. > > Austin > > Stephanie McBader wrote: > > > Hi, > > > > Xilinx FPGA datasheets (both Virtex & Spartan) indicate that the DONE > > pin is bidirectional. Does that mean that the logic configured inside > > the FPGA will be able to read it? > > > > i.e., would a controller implemented in the FPGA be able to read the > > value of DONE & say, remains in reset until DONE is asserted? > > > > Thanks! > > > > Stephanie McBader > > Researcher/Design Engineer > > NeuriCam S.p.A > > Via S M Maddalena 12 > > 38100 Trento TN, Italy > > Tel: +39-0461-260552 > > Fax: +39-0461-260617 > ###### From: hmurray@suespammers.org (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Bidirectional DONE? Date: Sat, 18 May 2002 22:13:57 -0000 Message-ID: X-Newsreader: xrn 9.02 Sender: murray@glypnod (Hal Murray) References: <3CE3B080.CBAB2AEC@neuricam.com> <3CE3D32C.1F877C05@xilinx.com> X-Complaints-To: newsabuse@supernews.com Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!freenix!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!glypnod!hmurray Xref: chonsp.franklin.ch comp.arch.fpga:17582 >Actually, I have a similar need, so let me pose the original posters >question in a different way. It is sometimes necessary to have user logic >initialize in a known state from power up. Perhaps the GSR signal might be >more appropriate (I can see it used in some modules in unisim), but so far, This gets discussed here occasionally. An important thing to consider is that the timing on GSR is very slow. It's essentially an asynchronous signal. (Been there. Don't need another lesson.) Best suggestion is to have a local FF that gets reset by GSR and use it to reset your state machine. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.