Newsgroups: comp.arch.fpga From: leotran@_*worldnet.att.net (Loi Tran) Subject: Xilinx IOBUF? X-Newsreader: News Xpress 2.01 Lines: 7 Message-ID: Date: Sun, 05 May 2002 21:17:25 GMT NNTP-Posting-Host: 12.86.236.233 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1020633445 12.86.236.233 (Sun, 05 May 2002 21:17:25 GMT) NNTP-Posting-Date: Sun, 05 May 2002 21:17:25 GMT Organization: AT&T Worldnet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!wn14eed!worldnet.att.net!135.173.83.55!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17247 I need someone to explain to me which IBUF/OBUFs I should be using for 5V CMOS interfacing. The part I'm using is XC2S200PQ208-5. I would appreciate any and all help that comes my way. Thank you. LT ###### Message-ID: <3CD5CB1E.D0EAF1A9@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? References: Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 27 Date: Mon, 06 May 2002 00:15:42 GMT NNTP-Posting-Host: 209.179.193.243 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 1020644142 209.179.193.243 (Sun, 05 May 2002 17:15:42 PDT) NNTP-Posting-Date: Sun, 05 May 2002 17:15:42 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!feed.newsfeeds.com!news-out.visi.com!hermes.visi.com!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17243 Loi, the highest Vccio for that part is 3.3 V. The inputs are 5-V tolerant, so there is no problem receiving data from a 5-V CMOS device. The Spartan-II outputs can, obviously, not actively pull higher than their own supply voltage, which might be as low as 3.0 V. If the device you are driving has CMOS-type ( not TTL-type) input thresholds, this interface is marginal at best, most likely unreliable. Your solution can be to 3-state the Spartan-II outputs and use an external pull-up resistor to 5V. That is a reliable albeit slow interface, sensitive to capacitive loading when the pull-up resistor is a few hundred ohms. If you are interested in higher speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask me for it. Peter Alfke, Xilinx Applications ( writing from home) peter@xilinx.com Loi Tran wrote: > I need someone to explain to me which IBUF/OBUFs I should be using for 5V CMOS > interfacing. The part I'm using is XC2S200PQ208-5. I would appreciate any > and all help that comes my way. > > Thank you. > > LT ###### Message-ID: <3CD5CB91.CCF98CBF@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? References: Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 27 Date: Mon, 06 May 2002 00:17:26 GMT NNTP-Posting-Host: 209.179.193.243 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 1020644246 209.179.193.243 (Sun, 05 May 2002 17:17:26 PDT) NNTP-Posting-Date: Sun, 05 May 2002 17:17:26 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!newsfeed.sjc.globix.net!hub1.meganetnews.com!hub1.nntpserver.com!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17246 Loi, the highest Vccio for that part is 3.3 V. The inputs are 5-V tolerant, so there is no problem receiving data from a 5-V CMOS device. The Spartan-II outputs can, obviously, not actively pull higher than their own supply voltage, which might be as low as 3.0 V. If the device you are driving has CMOS-type ( not TTL-type) input thresholds, this interface is marginal at best, most likely unreliable. Your solution can be to 3-state the Spartan-II outputs and use an external pull-up resistor to 5V. That is a reliable albeit slow interface, sensitive to capacitive loading when the pull-up resistor is a few hundred ohms. If you are interested in higher speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask me for it. Peter Alfke, Xilinx Applications ( writing from home) peter@xilinx.com Loi Tran wrote: > I need someone to explain to me which IBUF/OBUFs I should be using for 5V CMOS > interfacing. The part I'm using is XC2S200PQ208-5. I would appreciate any > and all help that comes my way. > > Thank you. > > LT ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? Date: Sun, 05 May 2002 18:32:26 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3CD5CB1E.D0EAF1A9@earthlink.net> X-Newsreader: Forte Agent 1.91/32.564 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 15 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!tethys.csu.net!nntp!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17260 On Mon, 06 May 2002 00:15:42 GMT, Peter Alfke wrote: >That is a reliable albeit slow interface, sensitive to capacitive loading when >the pull-up resistor is a few hundred ohms. If you are interested in higher >speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask >me for it. OK, Peter, what is the trick circuit? John ###### Message-ID: <3CD5F763.8BF179E5@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? References: <3CD5CB1E.D0EAF1A9@earthlink.net> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 38 Date: Mon, 06 May 2002 03:24:34 GMT NNTP-Posting-Host: 209.179.192.120 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1020655474 209.179.192.120 (Sun, 05 May 2002 20:24:34 PDT) NNTP-Posting-Date: Sun, 05 May 2002 20:24:34 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!news-xfer.newsread.com!netaxs.com!newsread.com!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!3ab61c21!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17239 It's a bit tedious in words: Put an external pull-up to 5 V on the pin. Drive the output signal as usual. Now comes the trick: Drive the output T signal ( Tristate active High) with an AND of the internal data signal AND the input signal coming from your output. (Remember, any pin is always an input) When you drive a Low output, the buffer is active (T is Low). When you start driving a High output, the buffer remains active until the output pin is crossing the threshold. Then the AND goes true, and the output goes 3-state. That means you got an active (<10 Ohm) output helping you on the way up. Obviously, it is in your interest to delay the input signal from reaching the AND gate too soon. You cannot get any help >3.3 V, but you may get a much faster rise time for the first 2 to 2.5 V, and that reduces the rising delay significantly. The falling delay is short anyway. Peter Alfke, Xilinx Applications ============================ John Larkin wrote: > On Mon, 06 May 2002 00:15:42 GMT, Peter Alfke > wrote: > > >That is a reliable albeit slow interface, sensitive to capacitive loading when > >the pull-up resistor is a few hundred ohms. If you are interested in higher > >speed, there is a trick circuit that eliminates 90% of the capacitive delay. Ask > >me for it. > > OK, Peter, what is the trick circuit? > > John ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? Date: Sun, 05 May 2002 21:22:33 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <7n0cdukrvfjbvqd2spgf8ao4v4u1h1ougf@4ax.com> References: <3CD5CB1E.D0EAF1A9@earthlink.net> <3CD5F763.8BF179E5@earthlink.net> X-Newsreader: Forte Agent 1.91/32.564 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 45 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17261 On Mon, 06 May 2002 03:24:34 GMT, Peter Alfke wrote: >It's a bit tedious in words: >Put an external pull-up to 5 V on the pin. >Drive the output signal as usual. >Now comes the trick: > >Drive the output T signal ( Tristate active High) with an AND of the internal data >signal AND the input signal coming from your output. (Remember, any pin is always an >input) > >When you drive a Low output, the buffer is active (T is Low). >When you start driving a High output, the buffer remains active until the output pin >is crossing the threshold. Then the AND goes true, and the output goes 3-state. >That means you got an active (<10 Ohm) output helping you on the way up. >Obviously, it is in your interest to delay the input signal from reaching the AND >gate too soon. > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > >The falling delay is short anyway. > >Peter Alfke, Xilinx Applications >============================ Peter, thanks; we'll keep that in mind. I guess you know the 'Shannon's Circuit' PECL driver trick: pull the signal up at the PECL load with a line-matched terminator to Vh = 4.2 volts maybe; FPGA tristate open becomes PECL high. To make a low, enable the tristate output and make a TTL high, which will be 3.3 volts = PECL low. This is very fast. The gotcha is that the FPGA 3.3 volt supply may have to *sink* current if you do this a lot. The other direction, PECL to FPGA, is not as nice. John ###### Newsgroups: comp.arch.fpga From: leotran@_*worldnet.att.net (Loi Tran) Subject: Re: Xilinx IOBUF? References: <3CD5CB1E.D0EAF1A9@earthlink.net> <3CD5F763.8BF179E5@earthlink.net> X-Newsreader: News Xpress 2.01 Lines: 37 Message-ID: Date: Mon, 06 May 2002 13:08:04 GMT NNTP-Posting-Host: 12.86.235.218 X-Complaints-To: abuse@worldnet.att.net X-Trace: bgtnsc05-news.ops.worldnet.att.net 1020690484 12.86.235.218 (Mon, 06 May 2002 13:08:04 GMT) NNTP-Posting-Date: Mon, 06 May 2002 13:08:04 GMT Organization: AT&T Worldnet Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!nf3.bellglobal.com!wn1feed!worldnet.att.net!135.173.83.55!bgtnsc05-news.ops.worldnet.att.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17248 Peter, Thanks for the help. One more question. What's the range of value the pullup you recommend for that circuit? I was thinking about 10K would be sufficient. Thanks again. LT In article <3CD5F763.8BF179E5@earthlink.net>, palfke@earthlink.net wrote: >It's a bit tedious in words: >Put an external pull-up to 5 V on the pin. >Drive the output signal as usual. >Now comes the trick: > >Drive the output T signal ( Tristate active High) with an AND of the internal > data >signal AND the input signal coming from your output. (Remember, any pin is > always an >input) > >When you drive a Low output, the buffer is active (T is Low). >When you start driving a High output, the buffer remains active until the > output pin >is crossing the threshold. Then the AND goes true, and the output goes 3-state. >That means you got an active (<10 Ohm) output helping you on the way up. >Obviously, it is in your interest to delay the input signal from reaching the > AND >gate too soon. > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > >The falling delay is short anyway. > >Peter Alfke, Xilinx Applications ###### Message-ID: <3CD69992.7736D6AE@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? References: <3CD5CB1E.D0EAF1A9@earthlink.net> <3CD5F763.8BF179E5@earthlink.net> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 45 Date: Mon, 06 May 2002 14:56:22 GMT NNTP-Posting-Host: 216.244.42.72 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1020696982 216.244.42.72 (Mon, 06 May 2002 07:56:22 PDT) NNTP-Posting-Date: Mon, 06 May 2002 07:56:22 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!3ab61c21!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17238 10k would give you a very slow final rise to 5 V. 470 Ohm to 1 kilohm is much better, limited by the output sink capability. Peter Alfke ================== Loi Tran wrote: > Peter, > > Thanks for the help. One more question. What's the range of value the pullup > you recommend for that circuit? I was thinking about 10K would be sufficient. > > Thanks again. > > LT > > In article <3CD5F763.8BF179E5@earthlink.net>, palfke@earthlink.net wrote: > >It's a bit tedious in words: > >Put an external pull-up to 5 V on the pin. > >Drive the output signal as usual. > >Now comes the trick: > > > >Drive the output T signal ( Tristate active High) with an AND of the internal > > data > >signal AND the input signal coming from your output. (Remember, any pin is > > always an > >input) > > > >When you drive a Low output, the buffer is active (T is Low). > >When you start driving a High output, the buffer remains active until the > > output pin > >is crossing the threshold. Then the AND goes true, and the output goes 3-state. > >That means you got an active (<10 Ohm) output helping you on the way up. > >Obviously, it is in your interest to delay the input signal from reaching the > > AND > >gate too soon. > > > >You cannot get any help >3.3 V, but you may get a much faster rise time for the > >first 2 to 2.5 V, and that reduces the rising delay significantly. > > > >The falling delay is short anyway. > > > >Peter Alfke, Xilinx Applications ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Xilinx IOBUF? Date: Mon, 06 May 2002 10:12:56 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3CD5CB1E.D0EAF1A9@earthlink.net> <3CD5F763.8BF179E5@earthlink.net> X-Newsreader: Forte Agent 1.91/32.564 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!freenix!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17259 On Mon, 06 May 2002 03:24:34 GMT, Peter Alfke wrote: > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > What might really be interesting would be to add a small series inductor. With mainly capacitive loading, the initial rising edge can theoretically overshoot to twice the FPGA supply voltage, at which time the tristate could be switched off, leaving the line high. In real life, this could probably extend your trick another volt or so. John