From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Virtex Evolution ( Deltas ) Date: Tue, 30 Apr 2002 16:18:21 -0700 Organization: Xilinx Lines: 185 Message-ID: <3CCF263D.2F8E59CE@xilinx.com> References: <3CC690B0.114551AA@uci.agh.edu.pl> <3CC7153D.4A0F8E01@xilinx.com> <3CC81CD4.77D0D197@yahoo.com> <3CC9F615.CE9E00E9@andraka.com> <3CCAC96C.4D206812@yahoo.com> <3CCB0E96.F6A13286@yahoo.com> <3CCB3BBF.16F50BB3@earthlink.net> <3CCC78BE.BB66E90B@andraka.com> <3CCC863A.E66DD3BB@earthlink.net> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------6C63926D593ED40C753EEF66" X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!wn14eed!wn1feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17009 --------------6C63926D593ED40C753EEF66 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit > Ray Andraka wrote: > > > A summary sheet listing the deltas (in detail) from the previous family would > > probably make a lot of people happy. As promised last weekend, here it is: Changes from Virtex-II to Virtex-II Pro Virtex-II Pro adds dedicated logic, 4 to 16 Multi-Gigabit Transceivers and 0 to 4 PowerPC microprocessors per chip. Each MGT takes the place of one BlockRAM at the top or bottom of the chip. Each PPC, (with caches, MMU and wide interfaces) takes the space of 128 CLBs plus 8 BlockRAMs The rest of the architecture is unchanged; same CLBs, IOBs, BlockRAMs, multipliers, DCMs, and the same routing structure. Same I/O interface capabilities, including on-chip termination. All circuits are re-laid out for the new 130 nm technology with nine layers of metal. (Virtex-II uses eight layers.) Same Vccint of 1.5 V, but Vccaux changed from 3.3 V to 2.5 V Each MGT has its own supply and ground pins. No bitstream or package-pin-out compatibility with other families. Nomenclature is different. Here are the approximate logic equivalents, ignoring MGT and microprocessor capabilities. XC2VP2 ~ XC2V250 XC2VP4 ~ XC2V500 XC2VP7 ~ XC2V1000 XC2VP20 ~ XC2V2000 XC2VP50 ~ XC2V4000 Changes from Virtex-E to Virtex-II Virtex-II is a major redesign of the Virtex architecture. The CLB has now 8 LUTs ( 4 slices) from 4 LUTs and 2 slices in Virtex and Virtex-E. The BlockRAM is >4 times bigger, and has x9, x18, and x36 option The BlockRAM has 3 options for read during write ( read first, write first, don't read) There is a dedicated 18 x 18 (max) 2-s complement multiplier close to each BlockRAM The DLL has grown to be a Digital Clock Manager with options for more multiply and devide ratios, simultaneous multipliy and divide ( frequency synthesis) and programmable phase delay. Support for many I/O standards is added, and there is an option for on-chip termination ( serial or parallel) Virtex-II uses 180 nm micron technology with 8 layers of metal.. The internal logic uses Vccint = 1.5 V, Vccaux is 3.3 V, Vccio is 1.5...3.3 V Virtex-II is not directly 5-V compatible ( needs external current-limiting resistor) Virtex-II (and Virtex-II Pro) have eliminated the large power-on inrush current. Viretx-II is not bitstream or package-pin-out compatibe with other families. Changes from Virtex to Virtex-E Virtex-E is a minor change, mainly a shrink for higher speed and cost reduction. The basic architecture is identical to Virtex, but the family now extends to larger sizes. Additional I/O standards are supported, notably LVDS ( with 2 pins per signal). There are eight DLLs, vs four in Virtex. I/O pins are 3-V tolerant, but need a 100 Ohm external resistor for 5-V tolerance. Not 5-V PCI compatible ( use Virtex or Spartan-II instead). Change in the banking rules. LVTTL, LVCMOS2, and PCI inputs are powered from Vccio. Vccint is 1.8 V, instead of 2.5 V for Virtex. This is due to 180 nm processing technology. Virtex-E is not bitstream compatibel with other families. Virtex-E is almost package-pin-out compatible with Virtex, see pin-out documentation for details. ============================================= This is not a substitute for studying the data sheets. Please e-mail me if you find any errors or omissions peter@xilinx.com --------------6C63926D593ED40C753EEF66 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit
Ray Andraka wrote:

> A summary sheet listing the deltas (in detail) from the previous family would
> probably make a lot of people happy.

As promised last weekend, here it is:
 

Changes from Virtex-II to Virtex-II Pro

Virtex-II Pro adds dedicated logic, 4 to 16 Multi-Gigabit Transceivers and 0 to 4 PowerPC microprocessors per chip. Each MGT takes the place of one BlockRAM at the top or bottom of the chip. Each PPC, (with caches, MMU and wide interfaces) takes the space of 128 CLBs plus 8 BlockRAMs

The rest of the architecture is unchanged; same CLBs, IOBs, BlockRAMs, multipliers, DCMs, and the same routing structure.
Same I/O interface capabilities, including on-chip termination.

All circuits are re-laid out for the new 130 nm technology with nine layers of metal.  (Virtex-II uses eight layers.)

Same Vccint of 1.5 V, but Vccaux changed from 3.3 V to 2.5 V
Each MGT has its own supply and ground pins.

No bitstream or package-pin-out compatibility with other families.

Nomenclature is different. Here are the approximate logic equivalents, ignoring MGT and microprocessor capabilities.

XC2VP2  ~ XC2V250
XC2VP4 ~ XC2V500
XC2VP7 ~ XC2V1000
XC2VP20 ~ XC2V2000
XC2VP50 ~ XC2V4000
 
 

Changes from Virtex-E to Virtex-II

Virtex-II is a major redesign of the Virtex architecture.

The CLB has now 8 LUTs ( 4 slices) from 4 LUTs and 2 slices in Virtex and Virtex-E.
The BlockRAM is >4 times bigger, and has  x9, x18, and x36 option
The BlockRAM has 3 options for read during write ( read first, write first, don't read)
There is a dedicated 18 x 18 (max) 2-s complement multiplier close to each BlockRAM
The DLL has grown to be a Digital Clock Manager with options for more multiply and devide ratios, simultaneous multipliy and divide ( frequency synthesis) and programmable phase delay.
Support for many I/O standards is added, and there is an option for on-chip termination ( serial or parallel)

Virtex-II uses 180 nm micron technology with 8 layers of metal..

The internal logic uses Vccint = 1.5 V, Vccaux is 3.3 V, Vccio is 1.5...3.3 V
Virtex-II is not directly 5-V compatible ( needs external current-limiting resistor)
Virtex-II (and Virtex-II Pro) have eliminated the large power-on inrush current.

Viretx-II is not bitstream or package-pin-out compatibe with other families.
 

Changes from Virtex to Virtex-E

Virtex-E is a minor change, mainly a shrink for higher speed and cost reduction.
The basic architecture is identical to Virtex, but the family now extends to larger sizes.
Additional I/O standards are supported, notably LVDS ( with 2 pins per signal).
There are eight DLLs, vs four in Virtex.

I/O pins are 3-V tolerant, but need a 100 Ohm external resistor for 5-V tolerance.
Not 5-V PCI compatible ( use Virtex or Spartan-II instead).
Change in the banking rules.  LVTTL, LVCMOS2, and PCI inputs are powered from Vccio.

Vccint is 1.8 V, instead of 2.5 V for Virtex. This is due to 180 nm processing technology.

Virtex-E is not bitstream compatibel with other families.
Virtex-E is almost package-pin-out compatible with Virtex, see pin-out documentation for details.
=============================================
This is not a substitute for studying the data sheets.
Please e-mail me if you find any errors or omissions
peter@xilinx.com

 
  --------------6C63926D593ED40C753EEF66-- ###### From: news@rtrussell.co.uk Newsgroups: comp.arch.fpga Subject: Re: Virtex Evolution ( Deltas ) Date: 2 May 2002 12:25:30 GMT Organization: British Broadcasting Corporation, UK Lines: 13 Message-ID: References: <3CC690B0.114551AA@uci.agh.edu.pl> <3CC7153D.4A0F8E01@xilinx.com> <3CC81CD4.77D0D197@yahoo.com> <3CC9F615.CE9E00E9@andraka.com> <3CCAC96C.4D206812@yahoo.com> <3CCB0E96.F6A13286@yahoo.com> <3CCB3BBF.16F50BB3@earthlink.net> <3CCC78BE.BB66E90B@andraka.com> <3CCC863A.E66DD3BB@earthlink.net> <3CCF263D.2F8E59CE@xilinx.com> NNTP-Posting-Host: 132.185.128.19 X-Trace: nntp0.reith.bbc.co.uk 1020342330 14973 132.185.128.19 (2 May 2002 12:25:30 GMT) X-Complaints-To: news@bbc.co.uk NNTP-Posting-Date: 2 May 2002 12:25:30 GMT X-BBC-Trace: MTMyLjE4NS4xMjguMTk= User-Agent: tin/1.4.3-20000502 ("Marian") (UNIX) (SunOS/5.8 (sun4u)) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!news.f.de.plusline.net!news-fra1.dfn.de!news0.de.colt.net!peernews2.colt.net!colt.net!kibo.news.demon.net!demon!lnewspeer01.lnd.ops.eu.uu.net!emea.uu.net!bbc!nntp0.reith.bbc.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:17132 Peter Alfke wrote: : Changes from Virtex to Virtex-E : Virtex-E is a minor change, mainly a shrink for higher speed and cost reduction. : The basic architecture is identical to Virtex, but the family now extends to : larger sizes. You don't mention the additional Block RAMs - not a 'minor' change as far as my applications are concerned ! Richard. http://www.rtrussell.co.uk/