From: "akhar" Newsgroups: comp.arch.fpga Subject: new to fpga's need insight Lines: 23 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: Date: Sat, 13 Apr 2002 01:39:37 -0700 NNTP-Posting-Host: 24.200.34.3 X-Complaints-To: abuse@videotron.ca X-Trace: weber.videotron.net 1018676524 24.200.34.3 (Sat, 13 Apr 2002 01:42:04 EDT) NNTP-Posting-Date: Sat, 13 Apr 2002 01:42:04 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!wesley.videotron.net!weber.videotron.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16484 Hello, I have been looking around on the net for more information but it seems quite obscure (not totally but a bit) I am interested in learning more about FPGA's and how to program them. I have found www.fpgacpu.org to be quite interesting but no quite clear at least with what I know from the FPGA's. I wanted to know : - what is the native language to program an FPGA ( I saw that I can use C but I have not found the compiler , Can I use another language?(lisp,scheme, java,Smalltalk)) - Are there limits to what I can program? (I would like to use them to program neural networks) - Is it possible to use OO paradigms? - what is the best recommended starter kit (altera's or xilinx's) - how do I know the number of gates I'll need for a project/application That's most of it I think Best Regards Stephane ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: 13 Apr 2002 14:54:41 +0200 Organization: My own Private Self Lines: 95 Message-ID: <6ud6x3zrla.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1018702481 486 10.0.3.2 (13 Apr 2002 12:54:41 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 13 Apr 2002 12:54:41 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:16493 "akhar" writes: > - what is the native language to program an FPGA ( I saw that I can use C > but I have not found the compiler , Can I use another language?(lisp,scheme, > java,Smalltalk)) Well there exist no such thing as an "native" language. What there exist are 4 entirely different approaches to programming and a few languages or tools for each: - high level code: Verilog, VHDL, AHDL, CUPL, Handel-C, ... - high level schematic (drawing): whatever format the tool wants - low level schematic: mainly FPGA Editor (only for Xilinx chips) - low level code: JBits, cnets, PamDC, ... Generally: - Low level means that you select individual FPGA features, comparable with assembly language programming. - High level means you write logic formulas and they are compiled, somewhat like high level programming. - Code means an ASCII source files that are assembled/compiled. - Schematic means some an drawing/CAD style program. As for C: there exists high level (Handel-C) and low level (cnets and PamDC) tools that use C as language. Handel-C tries to actually compile C expressions to FPGAs. cnets and PamDC use C as "driver" language to drive an library of "place this type of function here" calls. As for other languages like Lisp, Scheme, etc: forget them. Even Handel-C is at the limit of what is possible presently. And gets lots of flak for not being up to it yet. > - Are there limits to what I can program? (I would like to use them to > program neural networks) For one: Chip size. Remember the days when computers had 100k to 1M of RAM, and no virtual memory? All them "out of memory" errors. FPGA programming will remind you of that. Get a bigger chip... More importantly though: FPGAs are not sequencial "do this, do that" programming like processors. FPGAs are more "place this function here, place that there" with data traveling from one unit to the next and all units working all the time. So programming is splitting your problem into units and placing them so that data travels fast. So traditional languages are not what you want. You want an "layout descriptor" language. > - Is it possible to use OO paradigms? No. Totally useless. OO is all about managing sequential access to data. An FPGA is about as OO as an layout of machines on an factory floor! Each Unit is one instance of one class of processing (and not just a class for data objects to be instantiated), and data is not in instanciated objects that direct computation, but rather as stream of packets that travel (and need to be directed) to the proper units. So this is nearer to traditional "we know what data to expect" programming. > - what is the best recommended starter kit (altera's or xilinx's) Roughly equal. That is why both firms are roughly same size. Altera seems to win on complexer logic, Xilinx on faster Arithmetic. And whose tools are better, that is an ongoing but low-intensity holy war :-). For your neural networks (many small units with arithmetic and connecting to near neighbors) I would recommend Xilinx. > - how do I know the number of gates I'll need for a project/application Forget gates. They are an near-useless marketing number. Count Logic units (so called LUTs). Basically one LUT can compute any 1-bit function of 4 bits of input. And its associated FF can facultatively store one bit of data (the output bit) before sending it further. See the manufacturesrs data sheet for the range of LUT sizes they make. Usually in the few-100 to few-10000 range. To give an example: Xilinx XC2S200, for $50, is 4700 LUT/FF units. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: "akhar" Newsgroups: comp.arch.fpga References: <6ud6x3zrla.fsf@chonsp.franklin.ch> Subject: Re: new to fpga's need insight Lines: 109 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: Date: Sat, 13 Apr 2002 10:05:20 -0700 NNTP-Posting-Host: 24.200.34.3 X-Complaints-To: abuse@videotron.ca X-Trace: weber.videotron.net 1018706868 24.200.34.3 (Sat, 13 Apr 2002 10:07:48 EDT) NNTP-Posting-Date: Sat, 13 Apr 2002 10:07:48 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!wesley.videotron.net!weber.videotron.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16495 Thanks for the pointers, I looked up Handel C and found a lot of article talking about it but no official web site? is there one or is hcc the only compiler ? What sites do you recommend for learning how to program the FPGA's ? best regards Stephane "Neil Franklin" wrote in message news:6ud6x3zrla.fsf@chonsp.franklin.ch... > "akhar" writes: > > > - what is the native language to program an FPGA ( I saw that I can use C > > but I have not found the compiler , Can I use another language?(lisp,scheme, > > java,Smalltalk)) > > Well there exist no such thing as an "native" language. What there > exist are 4 entirely different approaches to programming and a few > languages or tools for each: > > - high level code: Verilog, VHDL, AHDL, CUPL, Handel-C, ... > - high level schematic (drawing): whatever format the tool wants > - low level schematic: mainly FPGA Editor (only for Xilinx chips) > - low level code: JBits, cnets, PamDC, ... > > Generally: > > - Low level means that you select individual FPGA features, comparable > with assembly language programming. > - High level means you write logic formulas and they are compiled, > somewhat like high level programming. > - Code means an ASCII source files that are assembled/compiled. > - Schematic means some an drawing/CAD style program. > > > As for C: there exists high level (Handel-C) and low level (cnets and > PamDC) tools that use C as language. Handel-C tries to actually compile > C expressions to FPGAs. cnets and PamDC use C as "driver" language to > drive an library of "place this type of function here" calls. > > As for other languages like Lisp, Scheme, etc: forget them. Even > Handel-C is at the limit of what is possible presently. And gets lots > of flak for not being up to it yet. > > > > - Are there limits to what I can program? (I would like to use them to > > program neural networks) > > For one: Chip size. Remember the days when computers had 100k to 1M > of RAM, and no virtual memory? All them "out of memory" errors. FPGA > programming will remind you of that. Get a bigger chip... > > More importantly though: FPGAs are not sequencial "do this, do that" > programming like processors. FPGAs are more "place this function here, > place that there" with data traveling from one unit to the next and > all units working all the time. So programming is splitting your > problem into units and placing them so that data travels fast. > > So traditional languages are not what you want. You want an "layout > descriptor" language. > > > > - Is it possible to use OO paradigms? > > No. Totally useless. > > OO is all about managing sequential access to data. An FPGA is about > as OO as an layout of machines on an factory floor! Each Unit is one > instance of one class of processing (and not just a class for data > objects to be instantiated), and data is not in instanciated objects > that direct computation, but rather as stream of packets that travel > (and need to be directed) to the proper units. > > So this is nearer to traditional "we know what data to expect" > programming. > > > > - what is the best recommended starter kit (altera's or xilinx's) > > Roughly equal. That is why both firms are roughly same size. Altera > seems to win on complexer logic, Xilinx on faster Arithmetic. And whose > tools are better, that is an ongoing but low-intensity holy war :-). > > For your neural networks (many small units with arithmetic and > connecting to near neighbors) I would recommend Xilinx. > > > > - how do I know the number of gates I'll need for a project/application > > Forget gates. They are an near-useless marketing number. > > Count Logic units (so called LUTs). Basically one LUT can compute any > 1-bit function of 4 bits of input. And its associated FF can facultatively > store one bit of data (the output bit) before sending it further. > > See the manufacturesrs data sheet for the range of LUT sizes they > make. Usually in the few-100 to few-10000 range. > > To give an example: Xilinx XC2S200, for $50, is 4700 LUT/FF units. > > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer > - Make your code truely free: put it into the public domain ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: 13 Apr 2002 16:50:37 +0200 Organization: My own Private Self Lines: 36 Message-ID: <6uvgavy7nm.fsf@chonsp.franklin.ch> References: <6ud6x3zrla.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1018709437 643 10.0.3.2 (13 Apr 2002 14:50:37 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 13 Apr 2002 14:50:37 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:16497 "akhar" writes: > I looked up Handel C and found a lot of article talking about it but no > official web site? is there one or is hcc the only compiler ? Sorry, I never looked into them. Only know their name from what has been discussed here on the group. They are at the top of the "high level code" approach, I am "low level code" style thinker and therefore programmer. I come from an El Eng background , using 74(LS)xx(x) chips. While you seem to be coming from an Comp Sci background used to HLLs. > What sites do > you recommend for learning how to program the FPGA's ? Caveat: sites selected for my own use, so perhaps not good your style. You could visit my computer and electronics links page: http://neil.franklin.ch/Links/comp_electro.html There scroll down to "FPGA CPU", as that was also for me the first FPGA oriented site I found. From there on there are quite a few links to (and into) various FPGA sites. The file is find-time ordered, so don't imply anything else from ordering. Most important (for me, low level code style) were the vendors data sheets. All the important ones have direct links in each vendors section, all fairly short after FPGA CPU. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domain ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: Sat, 13 Apr 2002 12:21:21 +0100 Message-ID: <1018729509.17070.1.nnrp-08.9e9832fa@news.demon.co.uk> References: NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 1018729509 nnrp-08:17070 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Lines: 20 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!easynet-tele!easynet.net!kibo.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16514 Start at optimagic.com and fpga-faq.com akhar wrote > Hello, I have been looking around on the net for more information but it > seems quite obscure (not totally but a bit) I am interested in learning more > about FPGA's and how to program them. I have found www.fpgacpu.org to be > quite interesting but no quite clear at least with what I know from the > FPGA's. I wanted to know : > - what is the native language to program an FPGA ( I saw that I can use C > but I have not found the compiler , Can I use another language?(lisp,scheme, > java,Smalltalk)) > - Are there limits to what I can program? (I would like to use them to > program neural networks) > - Is it possible to use OO paradigms? > - what is the best recommended starter kit (altera's or xilinx's) > - how do I know the number of gates I'll need for a project/application ###### Message-ID: <3CB870BC.91689545@attbi.com> From: Phil Hays Organization: phil-hays at above domain X-Mailer: Mozilla 4.78 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight References: <6ud6x3zrla.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 81 NNTP-Posting-Host: 12.230.124.133 X-Complaints-To: abuse@attbi.com X-Trace: sccrnsc02 1018720036 12.230.124.133 (Sat, 13 Apr 2002 17:47:16 GMT) NNTP-Posting-Date: Sat, 13 Apr 2002 17:47:16 GMT Date: Sat, 13 Apr 2002 17:47:16 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!wn14eed!wn3feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!sccrnsc02.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16516 akhar wrote: > Thanks for the pointers, > I looked up Handel C and found a lot of article talking about it but no > official web site? http://www.celoxica.com/home.htm > is there one or is hcc the only compiler ? Synopsys and Forte have SystemC to Verilog or VHDL compilers. SystemC is a "standard" library of C++ classes. Xilinx has a Java to Verilog compiler that is "freeware" until this summer: http://www.xilinx.com/ise/advanced/forge.htm http://www.synopsys.com/cgi-bin/sld/ltl1.cgi#f2 http://www.forteds.com/products/cynthesizer.html > What sites do > you recommend for learning how to program the FPGA's ? To do what? If you want high speed digital signal processing in the lowest cost possible FPGA, you may need different tools, attitudes and skills than if you want to emulate a ASIC, or emulate obsolete hardware, or communications equipment, or any of the various and sundry uses that FPGAs are put to. Some of the tools are useful for a narrow range of types of designs. For freeware tools, both Xilinx and Altera have fairly nice packages for starting with VHDL or Verilog: http://www.altera.com/products/software/sfw-quarwebmain.html http://www.xilinx.com/webpack/index.html > - Are there limits to what I can program? Of course. Large FPGAs have ten's of thousands of slices and hundreds of pins, and these limit the computation than can be done in a clock cycle and the amount of data than be input or output in a clock cycle. >(I would like to use them to program neural networks) Are you more interesting in learning about FPGAs, in learning about neural networks or is there an application of neural networks you are interested in? Also, is this learning or for a real product? If you are mostly interested in an application of neural nets, you have a need to speed it up relative to a software implementation, but don't need a fully optimized design, you might want to look at one of the HLL(HandelC, SystemC, Java). If you want to learn lots about FPGAs, you might want to start with a much lower level of abstraction (schematic or VHDL physical netlist) and learn about primitives, placement and other basics of FPGA design. > - what is the best recommended starter kit (altera's or xilinx's) I'd say Xilinx is somewhat ahead in general, this week. Altera is competitive, and has some advantages. > - how do I know the number of gates I'll need for a project/application Don't look at gate counts. The devices don't have "gates". The devices have small 4 input "Look Up Tables" LUTS, carry chains, multipliers and other special purpose logic, and larger memories, and some of these can be used for other purposes. The published gate counts make the assumption that you can use some large fraction of all of these: and real designs don't. I do estimation by trying to identify the resource that will be most used, and plan for the part that has enough of that resource. It's not easy. Usually, however, the design will be limited by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 flipflop (single bit storage). -- Phil Hays ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: Sat, 13 Apr 2002 16:25:31 -0500 Organization: None Lines: 91 Sender: kevinbraceusenet@hotmail.com Message-ID: References: NNTP-Posting-Host: 1cust114.tnt53.chi5.da.uu.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1018732557 7716 65.234.131.114 (13 Apr 2002 21:15:57 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Sat, 13 Apr 2002 21:15:57 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16505 akhar wrote: > > Hello, I have been looking around on the net for more information but it > seems quite obscure (not totally but a bit) I am interested in learning more > about FPGA's and how to program them. I have found www.fpgacpu.org to be > quite interesting but no quite clear at least with what I know from the > FPGA's. I wanted to know : > - what is the native language to program an FPGA ( I saw that I can use C > but I have not found the compiler , Can I use another language?(lisp,scheme, > java,Smalltalk)) I personally won't like to use the phrase "programming an FPGA." Although SRAM-based FPGAs have virtually unlimited programmability, I will rather call it, "Developing a circuit for an FPGA." If you want to seriously learn how to design circuits in which FPGAs can handle, learn Verilog or VHDL. I personally will recommend learning Verilog, and play around with a sample design that comes with free tools I will mention later. Besides http://www.fpgacpu.org, you can download free IP cores from Opencores.org (http://www.opencores.org), but be aware that the quality of the IP cores there isn't that great. > - Are there limits to what I can program? (I would like to use them to > program neural networks) Depends on the capacity of the FPGA. For FPGAs that cost less than $30, the gate density of FPGAs are still pretty small. For only that much of money, all you will likely get will be roughly about 50,000 ASIC (custom chip) gates. > - Is it possible to use OO paradigms? Although there might be attempts to bring such concepts into the FPGA world, I don't think it has worked too well, so you should forget about it. > - what is the best recommended starter kit (altera's or xilinx's) Well, I will become a partisan here. If you a newbie of designing circuits for an FPGA, I recommend downloading freely available design tools from various FPGA vendors. However, the tools from Xilinx and Altera are the ones that are useful in practice. I will personally recommend using Xilinx's free tools because Altera doesn't give you a free version of ModelSim (Yes, because it is free, the version distributed by Xilinx is somewhat crippled, but it still works at a reasonable speed as long as the design is not too big.), and there aren't too many vendors selling low cost Altera FPGA-based prototype boards. From my own experience, Xilinx's free tools seem to run more stable, faster, and requires less hardware resource than Altera's free tools. For low cost Xilinx FPGA-based prototype boards, check out Insight Electronics (http://www.insight-electronics.com) or Avnet (http://www.avnet.com) website. You can get one below $200. > - how do I know the number of gates I'll need for a project/application > > That's most of it I think > > Best Regards > > Stephane Design whatever you want to, and target the biggest chip that's available. Hopefully it will fit. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) ###### From: "akhar" Newsgroups: comp.arch.fpga References: <6ud6x3zrla.fsf@chonsp.franklin.ch> <3CB870BC.91689545@attbi.com> Subject: Re: new to fpga's need insight Lines: 105 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: Date: Sat, 13 Apr 2002 14:26:33 -0700 NNTP-Posting-Host: 24.200.34.3 X-Complaints-To: abuse@videotron.ca X-Trace: weber.videotron.net 1018722541 24.200.34.3 (Sat, 13 Apr 2002 14:29:01 EDT) NNTP-Posting-Date: Sat, 13 Apr 2002 14:29:01 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!wesley.videotron.net!weber.videotron.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16509 I am more concerned about optimising Neural network performances, so I think I will use one of the HLL's. It is the pulsed neural networks that interest me and since , from what I understand FPGA's are highly parrallel, they should be a match made in heaven. But in order to mmaximise performances I have to know a bit about how they work and what to do and not do. Basically my concerns are : storing values and changing then, and timing the computations. What I want to do is : - input the values in the first layer get a spike train (relative to time ) - feed it in the second layer and get a spike train -this is more sequential or try to emulate real neurons which would fire when ever they reached their treshold (ie neurons in the second layer can fire even if processing in the first layer hasn't been completed). You mention that the Xilinx java compiler will be free up til summer will the compiler "expire"? Many thanks for your help Stephane "Phil Hays" wrote in message news:3CB870BC.91689545@attbi.com... > akhar wrote: > > > Thanks for the pointers, > > I looked up Handel C and found a lot of article talking about it but no > > official web site? > > http://www.celoxica.com/home.htm > > > > is there one or is hcc the only compiler ? > > Synopsys and Forte have SystemC to Verilog or VHDL compilers. SystemC > is a "standard" library of C++ classes. Xilinx has a Java to Verilog > compiler that is "freeware" until this summer: > > http://www.xilinx.com/ise/advanced/forge.htm > > http://www.synopsys.com/cgi-bin/sld/ltl1.cgi#f2 > > http://www.forteds.com/products/cynthesizer.html > > > > What sites do > > you recommend for learning how to program the FPGA's ? > > To do what? If you want high speed digital signal processing in the > lowest cost possible FPGA, you may need different tools, attitudes and > skills than if you want to emulate a ASIC, or emulate obsolete hardware, > or communications equipment, or any of the various and sundry uses that > FPGAs are put to. Some of the tools are useful for a narrow range of > types of designs. For freeware tools, both Xilinx and Altera have > fairly nice packages for starting with VHDL or Verilog: > > http://www.altera.com/products/software/sfw-quarwebmain.html > > http://www.xilinx.com/webpack/index.html > > > > - Are there limits to what I can program? > > Of course. Large FPGAs have ten's of thousands of slices and hundreds > of pins, and these limit the computation than can be done in a clock > cycle and the amount of data than be input or output in a clock cycle. > > > >(I would like to use them to program neural networks) > > Are you more interesting in learning about FPGAs, in learning about > neural networks or is there an application of neural networks you are > interested in? Also, is this learning or for a real product? If you > are mostly interested in an application of neural nets, you have a need > to speed it up relative to a software implementation, but don't need a > fully optimized design, you might want to look at one of the > HLL(HandelC, SystemC, Java). If you want to learn lots about FPGAs, you > might want to start with a much lower level of abstraction (schematic or > VHDL physical netlist) and learn about primitives, placement and other > basics of FPGA design. > > > > - what is the best recommended starter kit (altera's or xilinx's) > > I'd say Xilinx is somewhat ahead in general, this week. Altera is > competitive, and has some advantages. > > > > - how do I know the number of gates I'll need for a project/application > > Don't look at gate counts. The devices don't have "gates". The devices > have small 4 input "Look Up Tables" LUTS, carry chains, multipliers and > other special purpose logic, and larger memories, and some of these can > be used for other purposes. The published gate counts make the > assumption that you can use some large fraction of all of these: and > real designs don't. I do estimation by trying to identify the resource > that will be most used, and plan for the part that has enough of that > resource. It's not easy. Usually, however, the design will be limited > by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 > flipflop (single bit storage). > > > -- > Phil Hays ###### Message-ID: <3CB8B277.44636726@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight References: <6ud6x3zrla.fsf@chonsp.franklin.ch> <3CB870BC.91689545@attbi.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 16 Date: Sat, 13 Apr 2002 22:34:40 GMT NNTP-Posting-Host: 209.179.198.254 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 1018737280 209.179.198.254 (Sat, 13 Apr 2002 15:34:40 PDT) NNTP-Posting-Date: Sat, 13 Apr 2002 15:34:40 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!news-xfer.newsread.com!netaxs.com!newsread.com!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16499 Phil Hays wrote: > > It's not easy. Usually, however, the design will be limited > by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 > flipflop (single bit storage). By definition, a slice is TWO LUTs and two flip-flops. But let'snot argue about the arcane reasons for this definition... Peter Alfke, Xilinx Applications ###### From: koziar.pete@orbital.com (Pete Koziar) Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: 15 Apr 2002 08:57:14 -0700 Organization: http://groups.google.com/ Lines: 120 Message-ID: <2951d198.0204150757.270a5313@posting.google.com> References: <6ud6x3zrla.fsf@chonsp.franklin.ch> <3CB870BC.91689545@attbi.com> NNTP-Posting-Host: 66.152.213.238 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1018886235 13685 127.0.0.1 (15 Apr 2002 15:57:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Apr 2002 15:57:15 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!freenix!isdnet!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16532 I'd start with something a lot simpler than an ANN! Even though the syntax you'd be dealing with is "C", you're not programming in "C" but using "C" syntax to specify an electronic circuit. In particular, you won't have an arithmetic logic unit unless you design one in. ANNs require multiplies and adds, as well as (at least an approximation to) the sigmoid function. All of these are non-trivial to implement in an FPGA. A good place to start is attending one of Xilinx's (or whomever's) classes on FPGAs. - Pete Koziar Principle Engineer VLU-120 Project Orbital Sciences/TMS "akhar" wrote in message news:... > I am more concerned about optimising Neural network performances, so I think > I will use one of the HLL's. It is the pulsed neural networks that interest > me and since , from what I understand FPGA's are highly parrallel, they > should be a match made in heaven. But in order to mmaximise performances I > have to know a bit about how they work and what to do and not do. Basically > my concerns are : storing values and changing then, and timing the > computations. What I want to do is : > - input the values in the first layer get a spike train (relative to time ) > - feed it in the second layer and get a spike train > -this is more sequential > or try to emulate real neurons which would fire when ever they reached their > treshold (ie neurons in the second layer can fire even if processing in the > first layer hasn't been completed). > > You mention that the Xilinx java compiler will be free up til summer will > the compiler "expire"? > > Many thanks for your help > > Stephane > "Phil Hays" wrote in message > news:3CB870BC.91689545@attbi.com... > > akhar wrote: > > > > > Thanks for the pointers, > > > I looked up Handel C and found a lot of article talking about it but no > > > official web site? > > > > http://www.celoxica.com/home.htm > > > > > > > is there one or is hcc the only compiler ? > > > > Synopsys and Forte have SystemC to Verilog or VHDL compilers. SystemC > > is a "standard" library of C++ classes. Xilinx has a Java to Verilog > > compiler that is "freeware" until this summer: > > > > http://www.xilinx.com/ise/advanced/forge.htm > > > > http://www.synopsys.com/cgi-bin/sld/ltl1.cgi#f2 > > > > http://www.forteds.com/products/cynthesizer.html > > > > > > > What sites do > > > you recommend for learning how to program the FPGA's ? > > > > To do what? If you want high speed digital signal processing in the > > lowest cost possible FPGA, you may need different tools, attitudes and > > skills than if you want to emulate a ASIC, or emulate obsolete hardware, > > or communications equipment, or any of the various and sundry uses that > > FPGAs are put to. Some of the tools are useful for a narrow range of > > types of designs. For freeware tools, both Xilinx and Altera have > > fairly nice packages for starting with VHDL or Verilog: > > > > http://www.altera.com/products/software/sfw-quarwebmain.html > > > > http://www.xilinx.com/webpack/index.html > > > > > > > - Are there limits to what I can program? > > > > Of course. Large FPGAs have ten's of thousands of slices and hundreds > > of pins, and these limit the computation than can be done in a clock > > cycle and the amount of data than be input or output in a clock cycle. > > > > > > >(I would like to use them to program neural networks) > > > > Are you more interesting in learning about FPGAs, in learning about > > neural networks or is there an application of neural networks you are > > interested in? Also, is this learning or for a real product? If you > > are mostly interested in an application of neural nets, you have a need > > to speed it up relative to a software implementation, but don't need a > > fully optimized design, you might want to look at one of the > > HLL(HandelC, SystemC, Java). If you want to learn lots about FPGAs, you > > might want to start with a much lower level of abstraction (schematic or > > VHDL physical netlist) and learn about primitives, placement and other > > basics of FPGA design. > > > > > > > - what is the best recommended starter kit (altera's or xilinx's) > > > > I'd say Xilinx is somewhat ahead in general, this week. Altera is > > competitive, and has some advantages. > > > > > > > - how do I know the number of gates I'll need for a project/application > > > > Don't look at gate counts. The devices don't have "gates". The devices > > have small 4 input "Look Up Tables" LUTS, carry chains, multipliers and > > other special purpose logic, and larger memories, and some of these can > > be used for other purposes. The published gate counts make the > > assumption that you can use some large fraction of all of these: and > > real designs don't. I do estimation by trying to identify the resource > > that will be most used, and plan for the part that has enough of that > > resource. It's not easy. Usually, however, the design will be limited > > by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 > > flipflop (single bit storage). > > > > > > -- > > Phil Hays ###### From: Phil James-Roxby Newsgroups: comp.arch.fpga Subject: Re: new to fpga's need insight Date: Mon, 15 Apr 2002 13:32:35 -0600 Organization: Xilinx, Inc. Lines: 51 Message-ID: <3CBB2AD3.D6B5FC16@xilinx.com> References: <6ud6x3zrla.fsf@chonsp.franklin.ch> <3CB870BC.91689545@attbi.com> NNTP-Posting-Host: 149.199.173.89 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (Windows NT 5.0; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!204.52.135.42!nntp1.hal-pc.org!attdl1!attdl2!attsl2!attdv2!attdv1!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16542 akhar wrote: > > I am more concerned about optimising Neural network performances, so I think > I will use one of the HLL's. It is the pulsed neural networks that interest > me and since , from what I understand FPGA's are highly parrallel, they > should be a match made in heaven. But in order to mmaximise performances I > have to know a bit about how they work and what to do and not do. Basically > my concerns are : storing values and changing then, and timing the > computations. What I want to do is : > - input the values in the first layer get a spike train (relative to time ) > - feed it in the second layer and get a spike train > -this is more sequential > or try to emulate real neurons which would fire when ever they reached their > treshold (ie neurons in the second layer can fire even if processing in the > first layer hasn't been completed). > > You mention that the Xilinx java compiler will be free up til summer will > the compiler "expire"? > > Many thanks for your help I still don't really understand what you want to do on the FPGA, but I will guess, state my assumption and make observations. You want to speed up the execution of a neural network over a software implementation. FPGA's are indeed parallel, so if you can fit it on a chip, and keep it fed with representative data, and consume the results, you are on a winner. I did exactly this many years ago using an Actel device - don't tell my current employers :-) Unsuprisingly, I/O costs swamped the speed up I got from parallel execution. So ask yourself the tough question, can I keep this super-hungry creature fed and deal with his droppings, or should I just do a software model. "Storing values and changing them" - what exactly do you mean here? Weights of some description? Similarly, timing the computation? From memory, the time between pulses in these types of networks is what determines the activity level - is this what you mean? Getting activity levels from a bit stream? When you finally get the structure you need, and are to integrate it in a system with I/O, then think FPGA. For now, I would model the behavior. Phil -- ------------------------------------------------------------ __ / /\/ Dr Phil James-Roxby Direct Dial: 303.544.5545 \ \ Sr. Staff Software Engineer Fax : 303.442.0198 / / Reconfigurable Logic Group \_\/\ Xilinx Labs @ Boulder, CO Phil.James-Roxby@xilinx.com ------------------------------------------------------------