From: gsletch@yahoo.com (Greg) Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: DDR SDRAM Controller Date: 12 Apr 2002 07:15:35 -0700 Organization: http://groups.google.com/ Lines: 16 Message-ID: <1c163be7.0204120615.1a3ac30c@posting.google.com> NNTP-Posting-Host: 47.234.0.52 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1018620935 20231 127.0.0.1 (12 Apr 2002 14:15:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 12 Apr 2002 14:15:35 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!propagator2-maxim!propagator-maxim!news-in.spamkiller.net!feed.newsfeeds.com!news-hog.berkeley.edu!ucberkeley!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16440 Hello, I have a question. Is it possible to do single reads and writes to a DDR SDRAM? I am designing a simple SDRAM controller and don't want to use the burst feature. I don't see how you could set the burst length to 1 in the mode register. It only offers 2,4,8 or full page. The remaining possibilities say "reserved". I am using a Micron part. Is it possible? I have taken a reference design written in VHDL, rewrote it in verilog and modified it to only handle single reads/writes. It originally supported a burst length of 4. I am getting ready to test it and beginning to wonder if it is possible and if so what the sequence to set if would be. Thanks, Greg ###### From: "name" Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: DDR SDRAM Controller Date: Fri, 12 Apr 2002 08:39:37 -0700 Organization: Compaq Systems Research Center Lines: 22 Message-ID: References: <1c163be7.0204120615.1a3ac30c@posting.google.com> NNTP-Posting-Host: srcdhcp96-147.pa.dec.com X-Trace: src-news-too.pa.dec.com 1018625979 485035 16.4.96.147 (12 Apr 2002 15:39:39 GMT) X-Complaints-To: usenet@src-news.pa.dec.com NNTP-Posting-Date: Fri, 12 Apr 2002 15:39:39 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!paloalto-snf1.gtei.net!news.gtei.net!news.compaq.com!src-news.pa.dec.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16413 Set the memory to full page mode and abort the operation after one cycle. "Greg" wrote in message news:1c163be7.0204120615.1a3ac30c@posting.google.com... > Hello, > > I have a question. Is it possible to do single reads and writes to a > DDR SDRAM? I am designing a simple SDRAM controller and don't want to > use the burst feature. I don't see how you could set the burst length > to 1 in the mode register. It only offers 2,4,8 or full page. The > remaining possibilities say "reserved". I am using a Micron part. Is > it > possible? I have taken a reference design written in VHDL, rewrote it > in verilog and modified it to only handle single reads/writes. It > originally supported a burst length of 4. I am getting ready to test > it and beginning to wonder if it is possible and if so what the > sequence to set if would be. > > Thanks, > Greg ###### Message-ID: <3CB700CE.2CD6379D@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: DDR SDRAM Controller References: <1c163be7.0204120615.1a3ac30c@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 Date: Fri, 12 Apr 2002 15:44:15 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1018626255 192.65.17.17 (Fri, 12 Apr 2002 09:44:15 MDT) NNTP-Posting-Date: Fri, 12 Apr 2002 09:44:15 MDT Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!uunet!dca.uu.net!ash.uu.net!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16454 One cycle is still 2 transfers, isn't it? I'd suggest that on the reads you ignore the word you don't want and on the writes use the DM bits to mask off the bytes. If you don't want to use the burst feature, why not design a single data rate SDRAM controller? You won't have better access times by going DDR, only better data transfer because of bursts. name wrote: > Set the memory to full page mode and abort the operation after one cycle. > > "Greg" wrote in message > news:1c163be7.0204120615.1a3ac30c@posting.google.com... > > Hello, > > > > I have a question. Is it possible to do single reads and writes to a > > DDR SDRAM? I am designing a simple SDRAM controller and don't want to > > use the burst feature. I don't see how you could set the burst length > > to 1 in the mode register. It only offers 2,4,8 or full page. The > > remaining possibilities say "reserved". I am using a Micron part. Is > > it > > possible? I have taken a reference design written in VHDL, rewrote it > > in verilog and modified it to only handle single reads/writes. It > > originally supported a burst length of 4. I am getting ready to test > > it and beginning to wonder if it is possible and if so what the > > sequence to set if would be. > > > > Thanks, > > Greg ###### From: spam_hater_7@email.com (Spam Hater) Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: DDR SDRAM Controller Message-ID: <3cb707c1.3910829@64.164.98.7> References: <1c163be7.0204120615.1a3ac30c@posting.google.com> X-Newsreader: Forte Free Agent 1.21/32.243 Lines: 36 NNTP-Posting-Host: 216.103.91.29 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr14.news.prodigy.com 1018628357 ST000 216.103.91.29 (Fri, 12 Apr 2002 12:19:17 EDT) NNTP-Posting-Date: Fri, 12 Apr 2002 12:19:17 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: SCSYQN_@OXWCRTXXLJIJOFTBTR\B@GXLN@GZ_GYO^BTJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Fri, 12 Apr 2002 16:19:17 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr14.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16444 For a DDR you -must- do an even number of data transfers. At 2 per clock, it's impossible not to. Think of it as 1,2,4 instead of 2,4,8. Be aware of odd address starts, and burst wrap. Use the DQM lines to block writes, ignore the reads. In my design I set the burst to max length, and terminated the burst when I was done. (Or ignored it if I had nothing else to do.) I did find a bug in the Micron model relating to DQM. Be careful. EMail me if you need more help. On 12 Apr 2002 07:15:35 -0700, gsletch@yahoo.com (Greg) wrote: >Hello, > >I have a question. Is it possible to do single reads and writes to a >DDR SDRAM? I am designing a simple SDRAM controller and don't want to >use the burst feature. I don't see how you could set the burst length >to 1 in the mode register. It only offers 2,4,8 or full page. The >remaining possibilities say "reserved". I am using a Micron part. Is >it >possible? I have taken a reference design written in VHDL, rewrote it >in verilog and modified it to only handle single reads/writes. It >originally supported a burst length of 4. I am getting ready to test >it and beginning to wonder if it is possible and if so what the >sequence to set if would be. > >Thanks, >Greg ###### From: spam_hater_7@email.com (Spam Hater) Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: DDR SDRAM Controller Message-ID: <3cb740e9.18545762@64.164.98.7> References: <1c163be7.0204120615.1a3ac30c@posting.google.com> X-Newsreader: Forte Free Agent 1.21/32.243 Lines: 9 NNTP-Posting-Host: 216.103.91.29 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr14.news.prodigy.com 1018644650 ST000 216.103.91.29 (Fri, 12 Apr 2002 16:50:50 EDT) NNTP-Posting-Date: Fri, 12 Apr 2002 16:50:50 EDT Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: SCSYQN_@OXWCRTXXLJIJOFTBTR\B@GXLN@GZ_GYO^BTJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Fri, 12 Apr 2002 20:50:50 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr14.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16489 DDR does not have full page mode. On Fri, 12 Apr 2002 08:39:37 -0700, "name" wrote: >Set the memory to full page mode and abort the operation after one cycle. >