From: muthu_nano@yahoo.co.in (Muthu) Newsgroups: comp.arch.fpga Subject: powerpc in virtex2pro Date: 12 Mar 2002 06:12:00 -0800 Organization: http://groups.google.com/ Lines: 10 Message-ID: <28c66cd3.0203120612.6792156a@posting.google.com> NNTP-Posting-Host: 202.54.64.9 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1015942321 26045 127.0.0.1 (12 Mar 2002 14:12:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 12 Mar 2002 14:12:01 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!out.nntp.be!propagator-SanJose!in.nntp.be!feed.cgocable.net!newsfeed-tor.nnrp.ca!newsfeed-tor.nnrp.ca!news.gv.tsc.tdk.com!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15207 Hi, The virtex2pro having 2 inbuild powerpc 405. Is it mean that, for any logic design the powerpc will be used to give the logic functionality? or If we need POwerpc we can use it? What is the special about having inbuild powerpc? Thanks and Regards, Muthu ###### Message-ID: <3C8E28D2.87C7162E@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 25 Date: Tue, 12 Mar 2002 16:12:22 GMT NNTP-Posting-Host: 209.179.193.212 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1015949542 209.179.193.212 (Tue, 12 Mar 2002 08:12:22 PST) NNTP-Posting-Date: Tue, 12 Mar 2002 08:12:22 PST Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Tue, 12 Mar 2002 08:12:23 PST (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.cwix.com!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15190 Muthu wrote: > What is the special about having inbuild powerpc? The advantage of built-in PowerPC microprocessor is that it connects very well to the logic fabric ( the CLBs, BlockRAMs, etc.) In Virtex-IIPro, each PPC has about 700 connections to the fabric, with several 64-wide busses. Obviously, you could use an external PPC, but that would not only mean an additional package, it would also mean many hundreds of FPGA pins being wasted on interfacing to the external PPC. More space, more power, less reliability, and most likely lower system performance. The tight and flexible connection between PPC and the logic is the biggest advantage. You can use the PPC for anything you want, from glorified state machine ( living off its two 16 Kbyte caches, to a full-fledged computer with its operating system residing in external RAM. This covers a very wider range. You can make many different trade-offs between hardware and software implementation, perhaps without ever changing the pc-board. Peter Alfke ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Fri, 15 Mar 2002 20:16:53 -0000 Message-ID: <1016228543.7477.1.nnrp-07.9e9832fa@news.demon.co.uk> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3C8E28D2.87C7162E@earthlink.net> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 1016228543 nnrp-07:7477 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Lines: 22 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15336 Peter Alfke wrote > The advantage of built-in PowerPC microprocessor is that it connects > very well to the logic fabric ( the CLBs, BlockRAMs, etc.) In > Virtex-IIPro, each PPC has about 700 connections to the fabric, with > several 64-wide busses. > Obviously, you could use an external PPC, but that would not only mean an > additional package, it would also mean many hundreds of FPGA pins being > wasted on interfacing to the external PPC. More space, more power, less > reliability, and most likely lower system performance. > The tight and flexible connection between PPC and the logic is the > biggest advantage. It looks as if the '405 consumes the space of 512 LUTs, ignoring any dedicated layers on the chip. 512 LUTs is midway between an XC2S30 and an XC2S50. But maybe the design was harder than a typical XC2S50 implementation :-) ###### From: "Cyrille de Brébisson" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Fri, 29 Mar 2002 14:26:33 -0700 Organization: SSO-IT, Hewlett-Packard Co. Lines: 25 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> NNTP-Posting-Host: l41dhcp101.boi.hp.com X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!sdd.hp.com!fc.hp.com!news.cup.hp.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15936 Hello, Actually, I have a related question. In our design we are using an ARM CPU. My question is: Can we put an ARM in the virtex 2 pro? Were can I find/buy an ARM cpu core source (or precompiled) file to program in my FPGA? Regards, Cyrille "Muthu" wrote in message news:28c66cd3.0203120612.6792156a@posting.google.com... > Hi, > > The virtex2pro having 2 inbuild powerpc 405. Is it mean that, for any > logic design the powerpc will be used to give the logic functionality? > or If we need POwerpc we can use it? > > What is the special about having inbuild powerpc? > > Thanks and Regards, > Muthu ###### Message-ID: <3CA54B02.A18049F2@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 8bit Lines: 28 Date: Sat, 30 Mar 2002 05:20:13 GMT NNTP-Posting-Host: 209.179.192.221 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1017465613 209.179.192.221 (Fri, 29 Mar 2002 21:20:13 PST) NNTP-Posting-Date: Fri, 29 Mar 2002 21:20:13 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!netnews.com!xfer02.netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15959 "Cyrille de Brébisson" wrote: > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? > Cyrille, the answer to both your questions is: No. The PowerPC in Virtex-II Pro is a "hard" implementation, packing the microprocessor with its caches and MMU into the smallest possible silicon area, <4 square millimeters. What you seem to be looking for is a "soft" implementation, using the programmable logic "fabric". That solution is impractical for something as complex as PowerPC or even ARM. It would take up an unreasonable portion of a large chip, and achieve mediocre performance at best. Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for efficient implementation in the Virtex architecture. It is not as fast and capable as PowerPC, but uses only ~900 slices. "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no flames... Peter Alfke, Xilinx Applications ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Sat, 30 Mar 2002 14:27:04 -0500 Organization: http://extra.newsguy.com Lines: 19 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> NNTP-Posting-Host: p-010.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews4 Xref: chonsp.franklin.ch comp.arch.fpga:15967 In article , cyrille_de-brebisson@hp.com says... > Hello, > > Actually, I have a related question. > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? In the interest of full disclosure... Xilinx doesn't do ARM, but Altera has an ARM hard core in their Excalibur series. I don't know anything more than what is on their web site though. Xilinx chose the right processor. ;-) ---- Keith IBM PowerPC Development (but nothing to do with Xilinx/IBM alliance) ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Sat, 30 Mar 2002 15:26:12 -0600 Organization: None Lines: 29 Sender: kevinbraceusenet@hotmail.com Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> NNTP-Posting-Host: 1cust94.tnt83.chi5.da.uu.net Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: newsreader.mailgate.org 1017523029 4899 67.195.65.94 (30 Mar 2002 21:17:09 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Sat, 30 Mar 2002 21:17:09 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15965 I read an article a few months ago about a startup developing yet another ARM clone (PicoTurbo exited the ARM clone business.). http://www.eetimes.com/story/OEG20020124S0111 What is the purpose of putting an ARM or its clone core into a Virtex-II Pro? Is it for an ASIC prototype? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) "Cyrille de Brébisson" wrote: > > Hello, > > Actually, I have a related question. > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? > > Regards, Cyrille > ###### From: Ron Huizen Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Mon, 01 Apr 2002 09:18:40 -0500 Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3CA86C40.21220550@bittware.com> Reply-To: rhuizen@bittware.com X-Mailer: Mozilla 4.7 [en]C-CCK-MCD {Sony} (Win98; U) X-Accept-Language: en MIME-Version: 1.0 References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Complaints-To: newsabuse@supernews.com Lines: 36 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15979 Peter, Are you saying that putting an ARM core into a Virtex II is not doable, or just not practical? Or are you only talking about the V2 Pro? --------- Ron Huizen BittWare Peter Alfke wrote: > > "Cyrille de Brébisson" wrote: > > > In our design we are using an ARM CPU. My question is: > > Can we put an ARM in the virtex 2 pro? > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > in my FPGA? > > > > Cyrille, > the answer to both your questions is: No. > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > microprocessor with its caches and MMU into the smallest possible silicon > area, <4 square millimeters. > What you seem to be looking for is a "soft" implementation, using the > programmable logic "fabric". > That solution is impractical for something as complex as PowerPC or even ARM. > It would take up an unreasonable portion of a large chip, and achieve mediocre > performance at best. > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > efficient implementation in the Virtex architecture. It is not as fast and > capable as PowerPC, but uses only ~900 slices. > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > flames... > > Peter Alfke, Xilinx Applications ###### Message-ID: <3CA88C7A.C421A0B1@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 8bit Lines: 52 Date: Mon, 01 Apr 2002 16:36:19 GMT NNTP-Posting-Host: 209.179.199.185 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1017678979 209.179.199.185 (Mon, 01 Apr 2002 08:36:19 PST) NNTP-Posting-Date: Mon, 01 Apr 2002 08:36:19 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news.stealth.net!news.stealth.net!204.127.161.2.MISMATCH!wn2feed!wn14eed!worldnet.att.net!207.217.77.102!newsfeed2.earthlink.net!newsfeed.earthlink.net!stamper.news.pas.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15980 There are hard cores and soft cores. Hard cores are specialized silicon areas that implement a fnction very efficiently, but only the manufacturer ( Xilinx, Altera, etc ) can do that. Soft macros use the logic fabric ( CLBs etc ), and any user can instantiate them anywhere. Soft macros consume more silicon area per function, and are slower, but more flexible. (eg MicroBlaze and Nios) IMHO, both PowerPC and ARM are too complex to be implemented as soft macros. Xilinx picked PowerPC as the hard core in Virtex-II Pro, Altera picked ARM for Excalibur, and, surprisingly enough, no microprocessor at all for Stratix, their future flagship... Peter Alfke =================== Ron Huizen wrote: > Peter, > > Are you saying that putting an ARM core into a Virtex II is not doable, > or just not practical? Or are you only talking about the V2 Pro? > > --------- > Ron Huizen > BittWare > > Peter Alfke wrote: > > > > "Cyrille de Brébisson" wrote: > > > > > In our design we are using an ARM CPU. My question is: > > > Can we put an ARM in the virtex 2 pro? > > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > > in my FPGA? > > > > > > > Cyrille, > > the answer to both your questions is: No. > > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > > microprocessor with its caches and MMU into the smallest possible silicon > > area, <4 square millimeters. > > What you seem to be looking for is a "soft" implementation, using the > > programmable logic "fabric". > > That solution is impractical for something as complex as PowerPC or even ARM. > > It would take up an unreasonable portion of a large chip, and achieve mediocre > > performance at best. > > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > > efficient implementation in the Virtex architecture. It is not as fast and > > capable as PowerPC, but uses only ~900 slices. > > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > > flames... > > > > Peter Alfke, Xilinx Applications ###### Message-ID: <3CA8CA64.2FBBBBCE@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 29 Date: Mon, 01 Apr 2002 22:00:20 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1017694828 62.254.210.251 (Mon, 01 Apr 2002 22:00:28 BST) NNTP-Posting-Date: Mon, 01 Apr 2002 22:00:28 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!colt.net!newspeer.clara.net!news.clara.net!peernews!peer.cwci.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:15995 "Keith R. Williams" wrote: > In article , cyrille_de-brebisson@hp.com > says... > > Hello, > > > > Actually, I have a related question. > > In our design we are using an ARM CPU. My question is: > > Can we put an ARM in the virtex 2 pro? > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > in my FPGA? > > In the interest of full disclosure... Xilinx doesn't do ARM, but Altera > has an ARM hard core in their Excalibur series. I don't know anything > more than what is on their web site though. > > Xilinx chose the right processor. ;-) > > Nah! It should have been one of the MIPS cores. - Speaking as someone for whom the bigger the MIPS world, the bigger my earnings. ###### Message-ID: <3CA8F96B.819ED3C@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA8CA64.2FBBBBCE@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 28 Date: Tue, 02 Apr 2002 00:20:32 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1017706832 68.15.41.165 (Mon, 01 Apr 2002 19:20:32 EST) NNTP-Posting-Date: Mon, 01 Apr 2002 19:20:32 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-out.visi.com!hermes.visi.com!cox.net!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16005 Rick Filipkiewicz wrote: > "Keith R. Williams" wrote: > > > Xilinx chose the right processor. ;-) > > > > > > Nah! It should have been one of the MIPS cores. > I voted for an RCA1802 knock off ;-) -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: gacalac@yahoo.com (Alan Calac) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: 1 Apr 2002 17:40:43 -0800 Organization: http://groups.google.com/ Lines: 34 Message-ID: <23b3c2e9.0204011740.4dd5843e@posting.google.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> NNTP-Posting-Host: 66.35.226.228 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1017711643 20740 127.0.0.1 (2 Apr 2002 01:40:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 2 Apr 2002 01:40:43 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16028 Microblase has an unofficial slogan too: "Half the size of Nios, and a quarter of the features". Xilinx certainly doesn't prefer this one, but it seems to be catching on with those who have used both processors. --------->Alan Peter Alfke wrote in message news:<3CA54B02.A18049F2@earthlink.net>... > "Cyrille de Brébisson" wrote: > > > In our design we are using an ARM CPU. My question is: > > Can we put an ARM in the virtex 2 pro? > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > in my FPGA? > > > > Cyrille, > the answer to both your questions is: No. > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > microprocessor with its caches and MMU into the smallest possible silicon > area, <4 square millimeters. > What you seem to be looking for is a "soft" implementation, using the > programmable logic "fabric". > That solution is impractical for something as complex as PowerPC or even ARM. > It would take up an unreasonable portion of a large chip, and achieve mediocre > performance at best. > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > efficient implementation in the Virtex architecture. It is not as fast and > capable as PowerPC, but uses only ~900 slices. > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > flames... > > Peter Alfke, Xilinx Applications ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Mon, 1 Apr 2002 22:29:28 -0500 Organization: http://extra.newsguy.com Lines: 23 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA8CA64.2FBBBBCE@algor.co.uk> NNTP-Posting-Host: p-507.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews3 Xref: chonsp.franklin.ch comp.arch.fpga:16031 In article <3CA8CA64.2FBBBBCE@algor.co.uk>, rick@algor.co.uk says... > > > "Keith R. Williams" wrote: > > Xilinx chose the right processor. ;-) > > > > > > Nah! It should have been one of the MIPS cores. Other people have other points of view. ;-) > > - Speaking as someone for whom the bigger the MIPS world, the bigger my earnings. Yep! My thoughts exactly! ;-) I may be looking to leverage some knowledge someday. Nice going Xilinx! ---- Keith ###### From: "Jan Gray" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Tue, 2 Apr 2002 06:04:03 -0800 Organization: Gray Research LLC Lines: 41 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CA88C7A.C421A0B1@earthlink.net> NNTP-Posting-Host: 04.2e.94.06 X-Server-Date: 2 Apr 2002 14:02:24 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!newsfeed1.cidera.com!Cidera!novia!novia!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsfeed0.news.atl.earthlink.net!news.atl.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16017 "Peter Alfke" wrote > IMHO, both PowerPC and ARM are too complex to be implemented as soft macros. Implementations of *integer subset*s of MIPS, ARM, and PowerPC architectures are not too complex to be implemented as soft cores. One can produce an integer MIPS-I soft core as "small" as MicroBlaze; and I have done a spreadhseet analysis/design study for an FPGA-optimized PowerPC Book I soft core that cost between 1200 and 2000 LUTs (1.3-2.2x the size of MicroBlaze), depending upon performance tradeoffs and whether or not you trap and emulate certain rare and expensive instructions. The only thing holding back fast (100 MHz) relatively compact (800-2000 LUTs) FPGA-optimized soft core implementations of subsetted commercial RISC instruction set architectures is the intellectual property landscape. I am surprised that certain processor IP companies, that lack a hard core programmable logic platform, and may therefore be losing certain design wins to ARM and PPC, have not yet launched soft FPGA-optimized processor core products. Perhaps they too think it infeasible or impractical. (My company would be pleased to demonstrate otherwise.) I predict that sooner-or-later all processor IP licensors will come to the realization that programmable logic has become the air that a great many of their designers breathe, and that eventually all processor IP licensors will offer or endorse FPGA-optimized soft processor core implementations of their ISAs. To not do so would be to surrender a quickly growing market segment to their competitors. I put that date around 2005. There is no defense against the ATTACK OF THE KILLER FPGAS! I also feel that binary translation (static or dynamic) will become important and then commonplace, both as a way to run legacy ISAs on streamlined FPGA-optimized cores, and as a way to run full ISAs on subsetted ISA implementations. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.org ###### From: Utku Ozcan Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Mon, 01 Apr 2002 17:00:10 +0300 Organization: Nortel Networks, Netas, Turkey, http://www.netas.com.tr Lines: 18 Message-ID: <3CA867EA.F4311D61@netas.com.tr> References: <28c66cd3.0203120612.6792156a@posting.google.com> NNTP-Posting-Host: 47.165.145.191 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable X-Mailer: Mozilla 4.61C-CCK-MCD [en] (X11; U; SunOS 5.6 sun4u) X-Accept-Language: en, tr Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!torn!qcarhaaa.nortelnetworks.com!bcarh189.ca.nortel.com!bcarh8ac.ca.nortel.com!bcarh8ab.ca.nortel.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16049 "Cyrille de Br=E9bisson" wrote: > Hello, > > Actually, I have a related question. > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to pro= gram > in my FPGA? > > Regards, Cyrille AFAIK Altera devices support ARM. Utku ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Tue, 02 Apr 2002 15:04:39 -0800 Organization: Xilinx Lines: 51 Message-ID: <3CAA3906.C7F98F3@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-out.spamkiller.net!news5.newsgroups.com!propagator-maxim!news-in.spamkiller.net!sfo2-feed1.news.algx.net!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!rcn!wn1feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16046 Ron, You can put any soft processor core you want in the Virtex II, or II Pro, as long as they are small enough to fit in the FPGA. Of course, there are royalty issues when using the ARM core. The PowerPC(tm IBM) license allows unlimited use of the PowerPC core in Virtex II Pro. And the license is free. MicroBlaze is also free. Austin Ron Huizen wrote: > Peter, > > Are you saying that putting an ARM core into a Virtex II is not doable, > or just not practical? Or are you only talking about the V2 Pro? > > --------- > Ron Huizen > BittWare > > Peter Alfke wrote: > > > > "Cyrille de Brébisson" wrote: > > > > > In our design we are using an ARM CPU. My question is: > > > Can we put an ARM in the virtex 2 pro? > > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > > in my FPGA? > > > > > > > Cyrille, > > the answer to both your questions is: No. > > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > > microprocessor with its caches and MMU into the smallest possible silicon > > area, <4 square millimeters. > > What you seem to be looking for is a "soft" implementation, using the > > programmable logic "fabric". > > That solution is impractical for something as complex as PowerPC or even ARM. > > It would take up an unreasonable portion of a large chip, and achieve mediocre > > performance at best. > > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > > efficient implementation in the Virtex architecture. It is not as fast and > > capable as PowerPC, but uses only ~900 slices. > > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > > flames... > > > > Peter Alfke, Xilinx Applications ###### From: crob714@yahoo.com (crob) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: 3 Apr 2002 09:43:57 -0800 Organization: http://groups.google.com/ Lines: 65 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> NNTP-Posting-Host: 66.35.226.228 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1017855837 29909 127.0.0.1 (3 Apr 2002 17:43:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 3 Apr 2002 17:43:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!isdnet!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16075 It's simple. If you want an ARM core, use Altera's Excalibur family. This is a cost-effective method if you want an ARM microprocessor connected directly to a PLD. As for the slogan, "Half the size and twice the speed of NIOS", leave this were it belongs, with the Marketing weenies. I have used the MicroBlaze microprocessor, and couldn't get close to the numbers claimed, go figure. I also noticed a SIGNIFICANT decrease in performance when I ran my code from external memory. C-ROB Austin Lesea wrote in message news:<3CAA3906.C7F98F3@xilinx.com>... > Ron, > > You can put any soft processor core you want in the Virtex II, or II Pro, as long as > they are small enough to fit in the FPGA. > > Of course, there are royalty issues when using the ARM core. > > The PowerPC(tm IBM) license allows unlimited use of the PowerPC core in Virtex II > Pro. And the license is free. MicroBlaze is also free. > > Austin > > Ron Huizen wrote: > > > Peter, > > > > Are you saying that putting an ARM core into a Virtex II is not doable, > > or just not practical? Or are you only talking about the V2 Pro? > > > > --------- > > Ron Huizen > > BittWare > > > > Peter Alfke wrote: > > > > > > "Cyrille de Brébisson" wrote: > > > > > > > In our design we are using an ARM CPU. My question is: > > > > Can we put an ARM in the virtex 2 pro? > > > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > > > in my FPGA? > > > > > > > > > > Cyrille, > > > the answer to both your questions is: No. > > > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > > > microprocessor with its caches and MMU into the smallest possible silicon > > > area, <4 square millimeters. > > > What you seem to be looking for is a "soft" implementation, using the > > > programmable logic "fabric". > > > That solution is impractical for something as complex as PowerPC or even ARM. > > > It would take up an unreasonable portion of a large chip, and achieve mediocre > > > performance at best. > > > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > > > efficient implementation in the Virtex architecture. It is not as fast and > > > capable as PowerPC, but uses only ~900 slices. > > > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > > > flames... > > > > > > Peter Alfke, Xilinx Applications ###### From: "jerry1111" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Wed, 3 Apr 2002 22:36:53 +0200 Organization: tp.internet - http://www.tpi.pl/ Lines: 25 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> NNTP-Posting-Host: pg81.bialystok.sdi.tpnet.pl Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Trace: news.tpi.pl 1017866055 5635 217.97.91.81 (3 Apr 2002 20:34:15 GMT) X-Complaints-To: usenet@tpi.pl NNTP-Posting-Date: Wed, 3 Apr 2002 20:34:15 +0000 (UTC) X-Priority: 3 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4910.0300 X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MSMail-Priority: Normal User-Agent: Hamster/1.3.23.4 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!newsfeed.hanau.net!news-fra1.dfn.de!news.man.poznan.pl!newsfeed.tpinternet.pl!news.tpi.pl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16086 Uzytkownik "crob" napisal w wiadomosci news:cb769f6b.0204030943.2d745fd@posting.google.com... > It's simple. If you want an ARM core, use Altera's Excalibur family. > This is a cost-effective method if you want an ARM microprocessor Cos effective? Altera's dealer told me that prices are starting from $1000 (in Poland) to $5000. I wanted to buy ARM kit two weeks ago. When he told me that kit costs $10k, and chips are starting from $1k - I stopped ;) > connected directly to a PLD. > > As for the slogan, "Half the size and twice the speed of NIOS", leave > this were it belongs, with the Marketing weenies. I have used the > MicroBlaze microprocessor, and couldn't get close to the numbers > claimed, go figure. I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. Interesting. Don't you know how it looks like in Nios? - my Nios is waiing for... taxes (those taxes which are applied to stuff when crossing national border - I don't know their name in English ;) jerry ###### Message-ID: <3CAB705D.68E9@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 21 Date: Thu, 04 Apr 2002 09:13:01 +1200 NNTP-Posting-Host: 203.79.98.196 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 1017869209 203.79.98.196 (Thu, 04 Apr 2002 09:26:49 NZST) NNTP-Posting-Date: Thu, 04 Apr 2002 09:26:49 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16100 jerry1111 wrote: > > Uzytkownik "crob" napisal w wiadomosci > news:cb769f6b.0204030943.2d745fd@posting.google.com... > > It's simple. If you want an ARM core, use Altera's Excalibur family. > > This is a cost-effective method if you want an ARM microprocessor > Cos effective? > Altera's dealer told me that prices are starting from $1000 (in Poland) > to $5000. I wanted to buy ARM kit two weeks ago. When he told > me that kit costs $10k, and chips are starting from $1k - I stopped ;) You have to need the speed, and tight coupling :-) At the other end of the scale, the lowest price spotted so far, for a ARM microcontroller (Off chip memory) is $4.95/10K from OKI See http://www.okisemi.com/html/docs/Intro-7830.html That's under x188 / x186 / eZ80 ... -jg ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Wed, 03 Apr 2002 13:24:38 -0800 Organization: Xilinx Lines: 80 Message-ID: <3CAB7316.36A88E60@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.cwix.com!wn2feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16087 C-ROB, Obviously, when one does a performance test, one does not go off chip to memory. It is much faster to execute out of BRAM, and show what the part is capable of doing. It would be like testing a Pentium IV with SDR 133 MHz RAM..... As for the difference when on-chip, I can only guess that you were doing something different from what was done for the benchmark. Did you open a hotline case at the time, and ask why? Austin crob wrote: > It's simple. If you want an ARM core, use Altera's Excalibur family. > This is a cost-effective method if you want an ARM microprocessor > connected directly to a PLD. > > As for the slogan, "Half the size and twice the speed of NIOS", leave > this were it belongs, with the Marketing weenies. I have used the > MicroBlaze microprocessor, and couldn't get close to the numbers > claimed, go figure. I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. > > C-ROB > > Austin Lesea wrote in message news:<3CAA3906.C7F98F3@xilinx.com>... > > Ron, > > > > You can put any soft processor core you want in the Virtex II, or II Pro, as long as > > they are small enough to fit in the FPGA. > > > > Of course, there are royalty issues when using the ARM core. > > > > The PowerPC(tm IBM) license allows unlimited use of the PowerPC core in Virtex II > > Pro. And the license is free. MicroBlaze is also free. > > > > Austin > > > > Ron Huizen wrote: > > > > > Peter, > > > > > > Are you saying that putting an ARM core into a Virtex II is not doable, > > > or just not practical? Or are you only talking about the V2 Pro? > > > > > > --------- > > > Ron Huizen > > > BittWare > > > > > > Peter Alfke wrote: > > > > > > > > "Cyrille de Brébisson" wrote: > > > > > > > > > In our design we are using an ARM CPU. My question is: > > > > > Can we put an ARM in the virtex 2 pro? > > > > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > > > > in my FPGA? > > > > > > > > > > > > > Cyrille, > > > > the answer to both your questions is: No. > > > > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > > > > microprocessor with its caches and MMU into the smallest possible silicon > > > > area, <4 square millimeters. > > > > What you seem to be looking for is a "soft" implementation, using the > > > > programmable logic "fabric". > > > > That solution is impractical for something as complex as PowerPC or even ARM. > > > > It would take up an unreasonable portion of a large chip, and achieve mediocre > > > > performance at best. > > > > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > > > > efficient implementation in the Virtex architecture. It is not as fast and > > > > capable as PowerPC, but uses only ~900 slices. > > > > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > > > > flames... > > > > > > > > Peter Alfke, Xilinx Applications ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Wed, 03 Apr 2002 13:55:01 -0800 Organization: Xilinx Lines: 13 Message-ID: <3CAB7A34.F16B1AC4@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: crob Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-fra1.dfn.de!news.tele.dk!small.news.tele.dk!204.71.34.15!news-out.cwix.com!newsfeed.cwix.com!wn2feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16090 crob wrote: > I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. No surprise, and an excellent argument for on-chip microprocessors running out of on-chip caches and BlockRAM, and having good connectivity to the FPGA fabric. Let me stop here, before I get into my Virtex-II Pro with PowerPC pitch... :-) Peter Alfke ###### From: "Jan Gray" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Wed, 3 Apr 2002 14:40:23 -0800 Organization: Gray Research LLC Lines: 36 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> NNTP-Posting-Host: 04.2e.94.06 X-Server-Date: 3 Apr 2002 22:38:46 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!t-online.de!deine.net!news-x2.support.nl!newspush.london1.eu.level3.net!level3eu!newsfeed.mathworks.com!wn3feed!worldnet.att.net!207.217.77.102!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsfeed0.news.atl.earthlink.net!news.atl.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16106 "Peter Alfke" wrote: > crob wrote: > > I also noticed a SIGNIFICANT decrease in > > performance when I ran my code from external memory. > > No surprise, and an excellent argument for on-chip microprocessors running out of on-chip caches > and BlockRAM, and having good connectivity to the FPGA fabric. If you're going to stay on chip, you might as well assume a 16-bit address space. Once you've done that, a <200 LUT 16-bit RISC MCU will often suffice. :-) If you're going to choose a 32-bit CPU because you want to use some of those great sprawling OSs and RTOSs and TCP/IP stacks and so forth, then it is likely that your application will not fit in on-chip RAM, and you should choose a microprocessor that provides at least an I-buffer, or I-cache, or branch target cache, lest your processor stall every instruction or branch. (Even if you have adequate bandwidth to off-chip instruction memory, the branch latency (nonsequential instruction fetch latency) will kill you.) A 20-50 MHz RISC CPU can get by with flow-through external SRAM. But at 125 MHz and up, plan to use an I-cache. The good news it is fairly simple to add an I-cache to an FPGA CPU core, assuming it already has an "instruction not ready signal". Of course, caches are also important to reduce core external bandwidth requirements. Using caches, you may be able to share a common memory interface with other cores, or may be able to use a 16-bit external memory data path instead of a 32-bit one. Jan Gray, Gray Research LLC ###### From: "B. Joshua Rosen" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Wed, 03 Apr 2002 18:08:41 -0500 Organization: Polybus Systems Corp Lines: 57 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> NNTP-Posting-Host: 65.200.172.65 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: fu-berlin.de 1017875322 29113052 65.200.172.65 (16 [78650]) X-Orig-Path: not-for-mail User-Agent: Pan/0.11.2 (Unix) X-Comment-To: "Peter Alfke" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fu-berlin.de!uni-berlin.de!65.200.172.65!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16105 In <3CAB7A34.F16B1AC4@xilinx.com>, Peter Alfke wrote: > crob wrote: > >> I also noticed a SIGNIFICANT decrease in >> performance when I ran my code from external memory. > > No surprise, and an excellent argument for on-chip microprocessors > running out of on-chip caches and BlockRAM, and having good connectivity > to the FPGA fabric. Let me stop here, before I get into my Virtex-II Pro > with PowerPC pitch... :-) > > Peter Alfke Xilinx has made some curious choices with the VirtexII Pro line and I was wondering if Peter would comment on some of them. First off let me say that the PPC was the right choice. Over the last few years the embedded processor of choice at all of the places that I have consulted to has been the 405. I also think that combining a 405 with an FPGA makes a lot of sense, it goes a long way towards being able to build a single chip customized embedded system without having to do an ASIC. Now for the things that I think were a little curious, 1) How come there isn't a dedicated DDR interface on the chip. I've never seen a PPC application that didn't require DRAM, a dedicated interface would be cheaper and higher performing than using valuable CLBs to build a soft interface. (If I'm mistaken about the lack of a dedicated DDR interface please let me know, I didn't see any mention of one when I read the spec). 2) I don't see the need for putting four processors on a die. In almost all cases a single 405 should be adequate, in a few case you could make good use of two but I don't think that you would ever need four. There should have been a wider choice of parts with a single 405 core. 3) There should also be a wider range of parts that have Rocket IO but no PPC. This is really a 2003 time frame issue when 3GIO starts to roll out, at that point Rocket IO will become very important. 4) On chip Flash RAM would be useful. An embedded PPC is going to require some Flash. Also it would be nice if the serial Flash RAM were on chip, I bet every one is sick of the extra part that most Xilinx designs require. 5) The IBM 405 chips include on board ethernet MACs, a PCI interface and an SDRAM interface, a version of that chip that also incorporates an FPGA and FLASH would be a good idea. In theory you could handle almost any embedded application with just that one chip plus an SDRAM or two. 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about offering versions of the Virtex II without the on board multipliers. The multipliers make sense for DSP applications but they are a waste of money and power for everything else. In my 12 years doing Xilinx designs I have never needed a multiplier. I've frequently needed a CAM so I wouldn't mind a few CAMs on board, but I'd rather have a cheaper part without the multiplers. ###### Message-ID: <3CAB93CD.A6AF92C@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 52 Date: Wed, 03 Apr 2002 23:44:11 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1017877451 192.65.17.17 (Wed, 03 Apr 2002 16:44:11 MST) NNTP-Posting-Date: Wed, 03 Apr 2002 16:44:11 MST Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newspeer.clara.net!news.clara.net!news2.euro.net!uunet!ash.uu.net!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16113 I'll put in my 2 cents worth on a few items below regarding the aspects I've come to appreciate... "B. Joshua Rosen" wrote: > 1) How come there isn't a dedicated DDR interface on the chip. I've never > seen a PPC application that didn't require DRAM, a dedicated interface > would be cheaper and higher performing than using valuable CLBs to build > a soft interface. (If I'm mistaken about the lack of a dedicated DDR > interface please let me know, I didn't see any mention of one when I read > the spec). > > 2) I don't see the need for putting four processors on a die. In almost > all cases a single 405 should be adequate, in a few case you could make > good use of two but I don't think that you would ever need four. There > should have been a wider choice of parts with a single 405 core. For both 1) and 2), the intent isn't exclusively to replace the processor in an embedded system, but to distribute the tasks. If you're dealing with an IP block that needs some intelligence, a single PPC could be used to take care of the somewhat complex - though limited - functionality needed. Why do almost all systems require a DRAM interface? Because there's just sooo much functionality pushed into a single general purpose machine. If you can distribute the processing and keep the code requirements small for some functional blocks, a main CPU could take care of the big tasks outside of the FPGA when performance wouldn't allow the little Virtex-II PPC to keep up with all the system demands. > 4) On chip Flash RAM would be useful. An embedded PPC is going to require > some Flash. Also it would be nice if the serial Flash RAM were on chip, > I bet every one is sick of the extra part that most Xilinx designs > require. I've been finding more ways to deal with external flash memory. I'd prefer to keep the FPGA cost constrained and get cheap generic flash rather than spending more for a process that isn't optimum for either the logic or the memory. > 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about > offering versions of the Virtex II without the on board multipliers. The > multipliers make sense for DSP applications but they are a waste of money > and power for everything else. In my 12 years doing Xilinx designs I have > never needed a multiplier. I've frequently needed a CAM so I wouldn't > mind a few CAMs on board, but I'd rather have a cheaper part without the > multiplers. Do you find yourself designing shifters? Both barrel shifters and straight shifters are nicely implemented in the multiplier blocks. Whether to align a SONET bit stream to the byte oriented frame or to insert/extract variable bit-width items into/from serial streams, shifters have been an important part of many of my designs. ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 08:35:42 -0800 Organization: Xilinx Lines: 171 Message-ID: <3CAC80DE.40E4D721@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------193D06CE66A59E9A26B27CC7" X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.cwix.com!wn2feed!wn3feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi_feed3!attbi.com!12.120.28.17!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16089 --------------193D06CE66A59E9A26B27CC7 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Joshua, Maybe I can comment, as I was on the VII Pro team, and the VII team. See below, Austin ---------------------snip---------------- > > > 1) How come there isn't a dedicated DDR interface on the chip. I've never > seen a PPC application that didn't require DRAM, a dedicated interface > would be cheaper and higher performing than using valuable CLBs to build > a soft interface. (If I'm mistaken about the lack of a dedicated DDR > interface please let me know, I didn't see any mention of one when I read > the spec). DDR is built out of the DDR FF in the IOB's and logic in the FPGA. DDR isn't the only standard, and customers have many other applications. DDR is neat, but too specific. > > > 2) I don't see the need for putting four processors on a die. In almost > all cases a single 405 should be adequate, in a few case you could make > good use of two but I don't think that you would ever need four. There > should have been a wider choice of parts with a single 405 core. We just don't know how customers will use all of this power. If 405ppc's are 'free', you can use one executing out of internal cache to handle the "error 404", and another running off internal cache to monitor QOS, etc. When electric motors were very expensive, a machine shop had one, and leather belts to every tool station. When fractional horsepower motors became inexpensive and ubiquitous, they were used everywhere, with no thought. If 405ppc are everywhere, you may dedicate them to tasks that seem horribly inefficient if you continue to think in terms of the one big expensive monster processor. > > > 3) There should also be a wider range of parts that have Rocket IO but no > PPC. This is really a 2003 time frame issue when 3GIO starts to roll out, > at that point Rocket IO will become very important. Stay tuned. > > > 4) On chip Flash RAM would be useful. An embedded PPC is going to require > some Flash. Also it would be nice if the serial Flash RAM were on chip, > I bet every one is sick of the extra part that most Xilinx designs > require. Flash requires a process that is usually two years behind the leading process. To do a flash capable FPGA would be to be obsolete on day 1 of the introduction. Not very exciting. > > 5) The IBM 405 chips include on board ethernet MACs, a PCI interface and > an SDRAM interface, a version of that chip that also incorporates an FPGA > and FLASH would be a good idea. In theory you could handle almost any > embedded application with just that one chip plus an SDRAM or two. MACs are soft cores to us. > > 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about > offering versions of the Virtex II without the on board multipliers. The > multipliers make sense for DSP applications but they are a waste of money > and power for everything else. In my 12 years doing Xilinx designs I have > never needed a multiplier. I've frequently needed a CAM so I wouldn't > mind a few CAMs on board, but I'd rather have a cheaper part without the > multiplers. Well, they take up a tiny amount of area, so the cost savings is washed out completely by having to make two parts, with lower volumes in each. --------------193D06CE66A59E9A26B27CC7 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Joshua,

Maybe I can comment, as I was on the VII Pro team, and the VII team.

See below,

Austin
 

---------------------snip----------------

 

1) How come there isn't a dedicated DDR interface on the chip. I've never
seen a PPC application that didn't require DRAM, a dedicated interface
would be cheaper and higher performing than using valuable CLBs to build
a soft interface. (If I'm mistaken about the lack of a dedicated DDR
interface please let me know, I didn't see any mention of one when I read
the spec).

DDR is built out of the DDR FF in the IOB's and logic in the FPGA.  DDR isn't the only standard, and customers have many other applications.  DDR is neat, but too specific.
 

2) I don't see the need for putting four processors on a die. In almost
all cases a single 405 should be adequate, in a few case you could make
good use of two but I don't think that you would ever need four. There
should have been a wider choice of parts with a single 405 core.

We just don't know how customers will use all of this power.  If 405ppc's are 'free', you can use one executing out of internal cache to handle the "error 404", and another running off internal cache to monitor QOS, etc.

When electric motors were very expensive, a machine shop had one, and leather belts to every tool station.  When fractional horsepower motors became inexpensive and ubiquitous, they were used everywhere, with no thought.

If 405ppc are everywhere, you may dedicate them to tasks that seem horribly inefficient if you continue to think in terms of the one big expensive monster processor.

 

3) There should also be a wider range of parts that have Rocket IO but no
PPC. This is really a 2003 time frame issue when 3GIO starts to roll out,
at that point Rocket IO will become very important.

Stay tuned.
 

4) On chip Flash RAM would be useful. An embedded PPC is going to require
some Flash. Also it would be nice if the serial Flash RAM were on chip,
I bet every one is sick of the extra part that most Xilinx designs
require.

Flash requires a process that is usually two years behind the leading process.  To do a flash capable FPGA would be to be obsolete on day 1 of the introduction.  Not very exciting.
 
5) The IBM 405 chips include on board ethernet MACs, a PCI interface and
an SDRAM interface, a version of that chip that also incorporates an FPGA
and FLASH would be a good idea. In theory you could handle almost any
embedded application with just that one chip plus an SDRAM or two.
MACs are soft cores to us.
 
6) This is a Virtex II issue, not just a Virtex II Pro issue. How about
offering versions of the Virtex II without the on board multipliers. The
multipliers make sense for DSP applications but they are a waste of money
and power for everything else. In my 12 years doing Xilinx designs I have
never needed a multiplier. I've frequently needed a CAM so I wouldn't
mind a few CAMs on board, but I'd rather have a cheaper part without the
multiplers.
Well, they take up a tiny amount of area, so the cost savings is washed out completely by having to make two parts, with lower volumes in each.
  --------------193D06CE66A59E9A26B27CC7-- ###### From: Lasse Langwadt Christensen Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 11:26:11 -0700 Organization: Cybercity Lines: 52 Message-ID: <3CAC9AC3.C181A79D@ieee.org> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> NNTP-Posting-Host: port36.cvx1-abc.ppp.cybercity.dk Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.cybercity.dk 1017944590 13885 217.157.84.37 (4 Apr 2002 18:23:10 GMT) X-Complaints-To: abuse@cybercity.dk NNTP-Posting-Date: Thu, 4 Apr 2002 18:23:10 +0000 (UTC) X-Mailer: Mozilla 4.7 [en-gb] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!newsfeed.online.be!zur.uu.net!ash.uu.net!news.cybercity.dk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16128 Peter Alfke wrote: > > "Cyrille de Brébisson" wrote: > > > In our design we are using an ARM CPU. My question is: > > Can we put an ARM in the virtex 2 pro? > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > in my FPGA? > > > > Cyrille, > the answer to both your questions is: No. > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > microprocessor with its caches and MMU into the smallest possible silicon > area, <4 square millimeters. > What you seem to be looking for is a "soft" implementation, using the > programmable logic "fabric". > That solution is impractical for something as complex as PowerPC or even ARM. > It would take up an unreasonable portion of a large chip, and achieve mediocre > performance at best. > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > efficient implementation in the Virtex architecture. It is not as fast and > capable as PowerPC, but uses only ~900 slices. > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > flames... > > Peter Alfke, Xilinx Applications you can definately put an ARM in an FPGA the last project I worked on, I did an a ASIC proto of a SoC with an ARM7-TDMI-S in a virtexE, rigth now I'm working on something similar but in a virtex2, so it can hopefully get more of the clock gating in the design working in the prototype. Size and performance will not be like a hard implementation, but for a prototype that doesn't really matter as long as the performance is enough and the design fits a chip you can buy. And if you need to there's things that could be changed to bettter fit and fpga, so performance could be increased, but for a prototype you don't what to do that unless you have to. But anyways, buying the source code for an ARM will probably cost you an arm ;) and a leg, -Lasse -- Lasse Langwadt Christensen, -- Aalborg, Danmark ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 4 Apr 2002 19:04:22 +0000 (UTC) Organization: Unknown Lines: 120 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1017947062 23387 128.32.247.226 (4 Apr 2002 19:04:22 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Thu, 4 Apr 2002 19:04:22 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.cwix.com!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16124 Additional view from a computer architect type: In article <3CAC80DE.40E4D721@xilinx.com>, Austin Lesea wrote: >> 1) How come there isn't a dedicated DDR interface on the chip. I've never >> seen a PPC application that didn't require DRAM, a dedicated interface >> would be cheaper and higher performing than using valuable CLBs to build >> a soft interface. (If I'm mistaken about the lack of a dedicated DDR >> interface please let me know, I didn't see any mention of one when I read >> the spec). > >DDR is built out of the DDR FF in the IOB's and logic in the FPGA. DDR isn't >the only standard, and customers have many other applications. DDR is neat, >but too specific. There is also a design pholosophy (which I can agree with for some uses, can't for others here) that only the minimally useful set should be implemented, because that is the cheapest and useable by the most people. A dedicated DDR SDRAM interface would be very nice, but that would consume a couple mm^2 of silicon, which is only usable by those who are going to plunk down a DDR interface, on a specific set of pins. >> 2) I don't see the need for putting four processors on a die. In almost >> all cases a single 405 should be adequate, in a few case you could make >> good use of two but I don't think that you would ever need four. There >> should have been a wider choice of parts with a single 405 core. > >We just don't know how customers will use all of this power. If 405ppc's are >'free', you can use one executing out of internal cache to handle the "error >404", and another running off internal cache to monitor QOS, etc. > >When electric motors were very expensive, a machine shop had one, and leather >belts to every tool station. When fractional horsepower motors became >inexpensive and ubiquitous, they were used everywhere, with no thought. > >If 405ppc are everywhere, you may dedicate them to tasks that seem horribly >inefficient if you continue to think in terms of the one big expensive monster >processor. And processors these days, for a simple core, are INCREDIBLY cheap, especially this one: It has no memory (those are the BlockRAMs), only the register file, datapath, and control logic. Even in synthesis, discounting the register file and caches, a 5 stage SPARC uP core takes 1.3mm x .85mm in a .18uM process. The caches, out of 4 1024x32b memories, are almost as big as the core itself! http://www.eecg.toronto.edu/~pagiamt/research/leon.html So in the area of about ~8-10 Virtex 2 BlockRAMs (1024x18b memories), you can fit a SYNTHESIZED sparc core (without a hardware multiplier/divider or MMU). I suspect that the Virtex 2 PPC core is even smaller, but with most of the actual area being the interfacing of the core to everything else. I'd love to get my hands on an XC2VP4 or larger die or die photo, just to verify these hunches about area in more detail. But according to the datasheet, the XC2VP2 uses 4 columns, 4 high of BlockRAMS, with the top and bottom of the center columns replaced with the RocketIO transecivers, so a pitch of 4 clb slices/BlockRAM. The XC2VP4 uses 4 columns, 10 high (its a 40x22 instead of a 16x22 array) and has 28 BlockRAMs, so 8 BlockRAMs are replaced for the PPC core, and 128 CLBs (500 slices) of logic. This is pretty CHEAP! If you have a low time critical function (EG, one which takes a fair path-length, but isn't necessarily pipeline-every-cycle), if you can replace just 128 CLBs with the use of the processor core, you've won, bigtime. So my assumption here is the 8 BlockRAMs of area are replaced with the uP core, with the rest going to a heck of a lot of interface logic. >> 4) On chip Flash RAM would be useful. An embedded PPC is going to require >> some Flash. Also it would be nice if the serial Flash RAM were on chip, >> I bet every one is sick of the extra part that most Xilinx designs >> require. > >Flash requires a process that is usually two years behind the leading >process. To do a flash capable FPGA would be to be obsolete on day 1 of the >introduction. Not very exciting. The only way I could conceive of their being Flash on the die is some fancy packaging, eg, a chip-up smaller flash chip bonded to internal pads on a chip down larger part. And do you REALLY want to spend an extra $20 just to reduce your part count from 2 to 1, and save 16-30 external pins? >> 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about >> offering versions of the Virtex II without the on board multipliers. The >> multipliers make sense for DSP applications but they are a waste of money >> and power for everything else. In my 12 years doing Xilinx designs I have >> never needed a multiplier. I've frequently needed a CAM so I wouldn't >> mind a few CAMs on board, but I'd rather have a cheaper part without the >> multiplers. > >Well, they take up a tiny amount of area, so the cost savings is washed out >completely by having to make two parts, with lower volumes in each. And, as Ray Andraka has pointed out, a multiplier makes a great shifter as well. A variable shift is suprisingly expensive in an FPGA fabric: there are a lot of muxes, but it is an operation that is suprisingly common. An 18x18 multiplier can implement an 18 bit variable rotation with just 18 LUTs worth of logic to deincode the shift amount, and an additional 18 LUTs worth of logic if you want to make it a left shift/rotate, an additional 36 LUTs worth if you want to make a variable left/right shift. The multiplier blocks are an example of something which IS very common. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 4 Apr 2002 19:09:15 +0000 (UTC) Organization: Unknown Lines: 9 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CAC9AC3.C181A79D@ieee.org> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1017947355 23681 128.32.247.226 (4 Apr 2002 19:09:15 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Thu, 4 Apr 2002 19:09:15 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed.media.kyoto-u.ac.jp!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16121 In article <3CAC9AC3.C181A79D@ieee.org>, Lasse Langwadt Christensen wrote: >But anyways, buying the source code for an ARM will probably cost you an >arm ;) and a leg, While SPARC is free. :) http://www.gaisler.com/leon.html -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 4 Apr 2002 19:40:46 +0000 (UTC) Organization: Unknown Lines: 36 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAC80DE.40E4D721@xilinx.com> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1017949246 25860 128.32.247.226 (4 Apr 2002 19:40:46 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Thu, 4 Apr 2002 19:40:46 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!news-hog.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16123 In article , Falk Brunner wrote: >110% acknowledge!!!!!!! > >This "one big CPU for all task" is the ancient approach of those Intel guys. >I remember a day, not too long ago, where Intel saw the future of the >personel computer with just a big RAM and a CPU, doing everything just in >software. :-0 >Hey guys, see those grafic controllers nowadays? See how many transistor >they have? See how much OPS they do? >Yes? Pfah. Big bloated pieces of silicon. :) It has ALWAYS been that several small processors are more "efficient" than one big processor, and it has always been a matter of programmability. A classic example is the Intel IXP1200 network processor, it consists of a single ARM core and 6 small risc-like cores, with context-switch on event (memory miss). A really powerful architecture if you can program it, and small too. Excluding the numerous interfaces (SDRAM, PCI, IXP bus, etc), it ends up being in the ~$10 silicon range. There is a lot of space still left in architectures with such performance that are also easier to program. Remember, an 8x8mm die, in a wafer level package, can buy you >200 pins [1], 10+ 32b Gops/second, in the sub $10/chip range. [2] [1] albeit at a .5mm pitch. Then again, 200 pins, any other ways, is going to easily add another $4-5 to the chip cost. So it is a tradeoff: higher board cost, lower part cost and area. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Message-ID: <3CACAFB7.1030902@synplicity.com> From: Ken McElvain User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:0.9.4) Gecko/20011128 Netscape6/6.2.1 X-Accept-Language: en-us MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CAC9AC3.C181A79D@ieee.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 43 Date: Thu, 04 Apr 2002 19:55:24 GMT NNTP-Posting-Host: 209.157.48.1 X-Complaints-To: abuse@verio.net X-Trace: sea-read.news.verio.net 1017950124 209.157.48.1 (Thu, 04 Apr 2002 19:55:24 GMT) NNTP-Posting-Date: Thu, 04 Apr 2002 19:55:24 GMT Organization: Verio Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!iad-peer.news.verio.net!news.verio.net!sea-read.news.verio.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16120 Lasse Langwadt Christensen wrote: >> > > you can definately put an ARM in an FPGA the last project I worked on, I > did > an a ASIC proto of a SoC with an ARM7-TDMI-S in a virtexE, rigth now I'm > working > on something similar but in a virtex2, so it can hopefully get more of > the > clock gating in the design working in the prototype. Clock gating for an asic design can be automatically converted to enables in Certify with no source code changes. This covers flops, latches, memories (inferred or instantiated). Ken McElvain CTO Synplicity, Inc. > > Size and performance will not be like a hard implementation, but for a > prototype > that doesn't really matter as long as the performance is enough and the > design > fits a chip you can buy. And if you need to there's things that could be > changed > to bettter fit and fpga, so performance could be increased, but for a > prototype > you don't what to do that unless you have to. > > But anyways, buying the source code for an ARM will probably cost you an > arm ;) and a leg, > > -Lasse > -- Lasse Langwadt Christensen, > -- Aalborg, Danmark > ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 11:55:45 -0800 Organization: Xilinx Lines: 40 Message-ID: <3CACAFC2.140DBBFD@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!wn2feed!wn3feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!12.120.28.17!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16119 Austin answered the specific questions very well. Please allow me to add some philosophical comments: We are in the business of providing programmable solutions, but there is always a temptation to add dedicated circuitry because it is smaller and faster and may consume less power. We have to make agonizing choices, because any specialization detracts from the universality, and any one of the special circuits we add burdens each chip and must be paid for by every user, while it may help only certain users or applications. Over the years we have added global clocks, carry logic, BlockRAM, clock management, lots of I/O standards, on-chip termination resistors, multipliers, triple-DES decryption, and now also PowerPC and 3-gigabit SerDes dedicated circuitry. Every one of these additions was made after carefully evaluating the trade-offs between the dedicated area (cost) vs general usefulness. And we are happy with our choices. There is a long list of potential candidates that were rejected ( I was in favor of adding a dedicated PCI interface, the the XC4000, which luckily was rejected). Some of our competitors have populated a graveyard (or at least a retirement community) of commercially unsuccessful attempts to add excessive or poorly executed specialization to programmable logic, and IMHO Excalibur with its glued-on ARM and Mercury with its limited-speed incomplete dedicated clock recovery may be headed in the same direction. Whenever you add something costly, you should do it right, and don't leave the job half completed! Xilinx is obviously also adding dedicated circuitry, but only after very careful consideration of the technical and economical trade-offs. And it looks like we have been right in our choices so far. But keep the suggestions coming. We are listening! Peter Alfke ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 13:26:47 -0800 Organization: Xilinx Lines: 128 Message-ID: <3CACC517.AC390FDE@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!newsfeed1.cidera.com!Cidera!dca6-feed2.news.algx.net!allegiance!feed2.news.rcn.net!rcn!wn1feed!wn2feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi.com!12.120.28.17!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16117 Nicholas, Just one minor point: the 405ppc has its own caches (16K for data, and 16K for instructions) so you can execute quite a bit right out of that without ever using a BRAM. Austin Nicholas Weaver wrote: > Additional view from a computer architect type: > > In article <3CAC80DE.40E4D721@xilinx.com>, > Austin Lesea wrote: > >> 1) How come there isn't a dedicated DDR interface on the chip. I've never > >> seen a PPC application that didn't require DRAM, a dedicated interface > >> would be cheaper and higher performing than using valuable CLBs to build > >> a soft interface. (If I'm mistaken about the lack of a dedicated DDR > >> interface please let me know, I didn't see any mention of one when I read > >> the spec). > > > >DDR is built out of the DDR FF in the IOB's and logic in the FPGA. DDR isn't > >the only standard, and customers have many other applications. DDR is neat, > >but too specific. > > There is also a design pholosophy (which I can agree with for some > uses, can't for others here) that only the minimally useful set should > be implemented, because that is the cheapest and useable by the most > people. > > A dedicated DDR SDRAM interface would be very nice, but that would > consume a couple mm^2 of silicon, which is only usable by those who > are going to plunk down a DDR interface, on a specific set of pins. > > >> 2) I don't see the need for putting four processors on a die. In almost > >> all cases a single 405 should be adequate, in a few case you could make > >> good use of two but I don't think that you would ever need four. There > >> should have been a wider choice of parts with a single 405 core. > > > >We just don't know how customers will use all of this power. If 405ppc's are > >'free', you can use one executing out of internal cache to handle the "error > >404", and another running off internal cache to monitor QOS, etc. > > > >When electric motors were very expensive, a machine shop had one, and leather > >belts to every tool station. When fractional horsepower motors became > >inexpensive and ubiquitous, they were used everywhere, with no thought. > > > >If 405ppc are everywhere, you may dedicate them to tasks that seem horribly > >inefficient if you continue to think in terms of the one big expensive monster > >processor. > > And processors these days, for a simple core, are INCREDIBLY cheap, > especially this one: > > It has no memory (those are the BlockRAMs), only the register file, > datapath, and control logic. > > Even in synthesis, discounting the register file and caches, a 5 stage > SPARC uP core takes 1.3mm x .85mm in a .18uM process. The caches, out > of 4 1024x32b memories, are almost as big as the core itself! > http://www.eecg.toronto.edu/~pagiamt/research/leon.html > > So in the area of about ~8-10 Virtex 2 BlockRAMs (1024x18b memories), > you can fit a SYNTHESIZED sparc core (without a hardware > multiplier/divider or MMU). I suspect that the Virtex 2 PPC core is > even smaller, but with most of the actual area being the interfacing > of the core to everything else. > > I'd love to get my hands on an XC2VP4 or larger die or die photo, just > to verify these hunches about area in more detail. > > But according to the datasheet, the XC2VP2 uses 4 columns, 4 high of > BlockRAMS, with the top and bottom of the center columns replaced with > the RocketIO transecivers, so a pitch of 4 clb slices/BlockRAM. > > The XC2VP4 uses 4 columns, 10 high (its a 40x22 instead of a 16x22 > array) and has 28 BlockRAMs, so 8 BlockRAMs are replaced for the PPC > core, and 128 CLBs (500 slices) of logic. This is pretty CHEAP! > > If you have a low time critical function (EG, one which takes a fair > path-length, but isn't necessarily pipeline-every-cycle), if you can > replace just 128 CLBs with the use of the processor core, you've won, > bigtime. So my assumption here is the 8 BlockRAMs of area are > replaced with the uP core, with the rest going to a heck of a lot of > interface logic. > > >> 4) On chip Flash RAM would be useful. An embedded PPC is going to require > >> some Flash. Also it would be nice if the serial Flash RAM were on chip, > >> I bet every one is sick of the extra part that most Xilinx designs > >> require. > > > >Flash requires a process that is usually two years behind the leading > >process. To do a flash capable FPGA would be to be obsolete on day 1 of the > >introduction. Not very exciting. > > The only way I could conceive of their being Flash on the die is some > fancy packaging, eg, a chip-up smaller flash chip bonded to internal > pads on a chip down larger part. And do you REALLY want to spend an > extra $20 just to reduce your part count from 2 to 1, and save 16-30 > external pins? > > >> 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about > >> offering versions of the Virtex II without the on board multipliers. The > >> multipliers make sense for DSP applications but they are a waste of money > >> and power for everything else. In my 12 years doing Xilinx designs I have > >> never needed a multiplier. I've frequently needed a CAM so I wouldn't > >> mind a few CAMs on board, but I'd rather have a cheaper part without the > >> multiplers. > > > >Well, they take up a tiny amount of area, so the cost savings is washed out > >completely by having to make two parts, with lower volumes in each. > > And, as Ray Andraka has pointed out, a multiplier makes a great > shifter as well. A variable shift is suprisingly expensive in an FPGA > fabric: there are a lot of muxes, but it is an operation that is > suprisingly common. > > An 18x18 multiplier can implement an 18 bit variable rotation with > just 18 LUTs worth of logic to deincode the shift amount, and an > additional 18 LUTs worth of logic if you want to make it a left > shift/rotate, an additional 36 LUTs worth if you want to make a > variable left/right shift. > > The multiplier blocks are an example of something which IS very > common. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu ###### Reply-To: "Steve Casselman" From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> Subject: Re: powerpc in virtex2pro Lines: 28 Organization: Virtual Computer Corporation X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: NNTP-Posting-Host: 64.174.106.246 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1017957648 ST000 64.174.106.246 (Thu, 04 Apr 2002 17:00:48 EST) NNTP-Posting-Date: Thu, 04 Apr 2002 17:00:48 EST X-UserInfo1: [[OQB\SDJSSURWH]^JKBOW@@YJ_ZTB\MV@BL\QMIWIWTEPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Thu, 04 Apr 2002 22:00:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16130 I have to disagree that a part with dedicated pins is a net loss for Xilinx. For example my patent http://www.delphion.com/details?pn=US06178494__ suggests that it might be useful to have a part that can be inserted into a pre-existing socket. For example if there were a part that fit into the second slot in of a Pentium system there is a good chance you could sell millions and millions of them. Steve "Peter Alfke" wrote in message news:3CACAFC2.140DBBFD@xilinx.com... > Austin answered the specific questions very well. > Please allow me to add some philosophical comments: > > We are in the business of providing programmable solutions, but there is always > a temptation to add dedicated circuitry because it is smaller and faster and may > consume less power. We have to make agonizing choices, because any > specialization detracts from the universality, and any one of the special > circuits we add burdens each chip and must be paid for by every user, while it > may help only certain users or applications. > ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 4 Apr 2002 22:05:49 +0000 (UTC) Organization: Unknown Lines: 18 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAC80DE.40E4D721@xilinx.com> <3CACC517.AC390FDE@xilinx.com> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1017957949 31660 128.32.247.226 (4 Apr 2002 22:05:49 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Thu, 4 Apr 2002 22:05:49 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16158 In article <3CACC517.AC390FDE@xilinx.com>, Austin Lesea wrote: >Nicholas, > >Just one minor point: the 405ppc has its own caches (16K for data, and 16K for >instructions) so you can execute quite a bit right out of that without ever using a >BRAM. OK. That makes even more sense (i shoulda noticed something was wrong), because otherwise it would take a HELL of a lot of interface logic to occupy 128 CLBs worth of logic. In any case, the assertion is: A uP is small. Including a fair number of them in a large FPGA is rather low cost. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 4 Apr 2002 22:16:53 +0000 (UTC) Organization: Unknown Lines: 17 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> NNTP-Posting-Host: soda.csua.berkeley.edu X-Trace: agate.berkeley.edu 1017958613 32086 128.32.247.226 (4 Apr 2002 22:16:53 GMT) X-Complaints-To: usenet@agate.berkeley.edu NNTP-Posting-Date: Thu, 4 Apr 2002 22:16:53 +0000 (UTC) Originator: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!agate.berkeley.edu!agate!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16156 In article , Steve Casselman wrote: >I have to disagree that a part with dedicated pins is a net loss for Xilinx. >For example my patent http://www.delphion.com/details?pn=US06178494__ >suggests that it might be useful to have a part that can be inserted into a >pre-existing socket. For example if there were a part that fit into the >second slot in of a Pentium system there is a good chance you could sell >millions and millions of them. However, the only consistant dedicated pins NEEDED are power and ground. Otherwise, the joys of reconfiguration, as long as the reconfigurable logic is fast enough, you can match the interface. Also, any dedicated circuitry is much harder to test, as it adds irregularities which need to be tested. -- Nicholas C. Weaver nweaver@cs.berkeley.edu ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 18:35:27 -0600 Organization: None Lines: 19 Sender: kevinbraceusenet@hotmail.com Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> NNTP-Posting-Host: 1cust82.tnt75.chi5.da.uu.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1017966356 21065 67.195.57.82 (5 Apr 2002 00:25:56 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Fri, 5 Apr 2002 00:25:56 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16166 I have seen a patent issued to Xilinx that describes an FPGA with a dedicated bus controller. The bus controller the patent described was a PCI interface. Peter, is this patent related to what you just said? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Peter Alfke wrote: > > > There is a long list of potential candidates that were rejected ( I was in favor > of adding a dedicated PCI interface, the the XC4000, which luckily was > rejected). > ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Thu, 04 Apr 2002 16:39:10 -0800 Organization: Xilinx Lines: 25 Message-ID: <3CACF22F.65671D85@xilinx.com> References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!colt.net!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!wn14eed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi_feed3!attbi.com!12.120.28.17!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16132 There is no clear relationship between patents and product planning. Sometimes things get patented, but still don't make it through the product planning process. A clever idea is one thing, a successful product something else. Sometimes they come together :-) I do not know about this particular patent. It is not in my name... Peter Alfke ====================== Kevin Brace wrote: > I have seen a patent issued to Xilinx that describes an FPGA with a > dedicated bus controller. > The bus controller the patent described was a PCI interface. > Peter, is this patent related to what you just said? > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > Peter Alfke wrote: > > > > > > There is a long list of potential candidates that were rejected ( I was in favor > > of adding a dedicated PCI interface, the the XC4000, which luckily was > > rejected). > > ###### Message-ID: <3CACFCE1.45DEFC66@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 48 Date: Fri, 05 Apr 2002 01:24:13 GMT NNTP-Posting-Host: 68.15.41.165 X-Complaints-To: abuse@cox.net X-Trace: news1.east.cox.net 1017969853 68.15.41.165 (Thu, 04 Apr 2002 20:24:13 EST) NNTP-Posting-Date: Thu, 04 Apr 2002 20:24:13 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!netnews.com!xfer02.netnews.com!news-out.visi.com!hermes.visi.com!cox.net!news1.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16142 Well, no it wasn't me this time. Actually the multipliers can be used as a shifter but... consider that to build a 16 bit rotator or shifter only requires 64 luts, and if pipelined to the maximum 4 stages can be clocked at more than twice the speed of the multiplier. Even then, the speed of the multiplier assumes that the multiplier has its input and outputs registered in the adjacent CLBs with no LUTs between (the multiplier has fairly long setup and clock to out times compared to the CLBs, so you need to keep the routes to/from the multiplier very short and with no LUTs). Adding those registers, you have 16 in, 16 out on top of the registes and logic for the shift decode (that can actually be done with the BRAM rather than with CLBs). In any event, you can see that using the multiplier as a shifter winds up costing more than half the CLB resources needed to do the same function in the fabric, and you only get half the speed or less if you are not careful about placement. The in-the-fabric version also gives you freedom of placement anywhere on the die instead of being constrained to the multiplier sites. The time-hardware product in this case actually favors the shifter implemented in the fabric even if the multipliers themselves are free and not counted in the comparison. Sorry to rain on your parade there, but you know not everyone can see the emperor's new clothes. Nicholas Weaver wrote: > And, as Ray Andraka has pointed out, a multiplier makes a great > shifter as well. A variable shift is suprisingly expensive in an FPGA > fabric: there are a lot of muxes, but it is an operation that is > suprisingly common. > > An 18x18 multiplier can implement an 18 bit variable rotation with > just 18 LUTs worth of logic to deincode the shift amount, and an > additional 18 LUTs worth of logic if you want to make it a left > shift/rotate, an additional 36 LUTs worth if you want to make a > variable left/right shift. > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Jan Gray" Newsgroups: comp.arch.fpga Subject: Re: powerpc in virtex2pro Date: Sun, 7 Apr 2002 08:14:56 -0700 Organization: Gray Research LLC Lines: 22 Message-ID: References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> NNTP-Posting-Host: 04.2e.94.06 X-Server-Date: 7 Apr 2002 15:18:22 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsfeed0.news.atl.earthlink.net!news.atl.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16220 "Steve Casselman" wrote > For example my patent http://www.delphion.com/details?pn=US06178494__ > suggests that it might be useful to have a part that can be inserted into a > pre-existing socket. http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html: "Five times better latency and four times better bandwidth could be achieved if FPGA vendors invent a way to directly connect their parts to the Pentium Pro external bus, as a peer of the memory/bus controller. A custom, dedicated Pentium Pro interface would probably be required, since FPGA configurable logic would be too slow and electrically incompatible." (4/96, 5/96 threads: http://groups.google.com/groups?th=589c20eee24735de, http://groups.google.com/groups?th=2946a4c24dd295ae) Jan Gray, Gray Research LLC ###### Reply-To: "Steve Casselman" From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <28c66cd3.0203120612.6792156a@posting.google.com> <3CA54B02.A18049F2@earthlink.net> <3CA86C40.21220550@bittware.com> <3CAA3906.C7F98F3@xilinx.com> <3CAB7A34.F16B1AC4@xilinx.com> <3CAC80DE.40E4D721@xilinx.com> <3CACAFC2.140DBBFD@xilinx.com> Subject: Re: powerpc in virtex2pro Lines: 34 Organization: Virtual Computer Corporation X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: NNTP-Posting-Host: 64.174.106.246 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr14.news.prodigy.com 1018289182 ST000 64.174.106.246 (Mon, 08 Apr 2002 14:06:22 EDT) NNTP-Posting-Date: Mon, 08 Apr 2002 14:06:22 EDT X-UserInfo1: F[OQB\SDJSSURWH]^JKBOW@@YJ_ZTB\MV@BT]UEK@YUDUWYAKVUOPCW[ML\JXUCKVFDYZKBMSFX^OMSAFNTINTDDMVW[X\THOPXZRVOCJTUTPC\_JSBVX\KAOTBAJBVMZTYAKMNLDI_MFDSSOLXINH__FS^\WQGHGI^C@E[A_CF\AQLDQ\BTMPLDFNVUQ_VM Date: Mon, 08 Apr 2002 18:06:22 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newscon02.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr14.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:16240 Hey Jan. You'll notice that even though the patent was issued in 2000 it was submitted 11/96. Of course my note book that has my initial write up is dated dec 17, 1994... Steve Casselman "Jan Gray" wrote in message news:a8pnvu$e89$1@slb4.atl.mindspring.net... > "Steve Casselman" wrote > > For example my patent http://www.delphion.com/details?pn=US06178494__ > > suggests that it might be useful to have a part that can be inserted into > a > > pre-existing socket. > > http://www.fpgacpu.org/usenet/fpgas_as_pc_coprocessors.html: > "Five times better latency and four times better bandwidth could be > achieved if FPGA vendors invent a way to directly connect their parts > to the Pentium Pro external bus, as a peer of the memory/bus > controller. A custom, dedicated Pentium Pro interface would probably > be required, since FPGA configurable logic would be too slow and > electrically incompatible." > > (4/96, 5/96 threads: > http://groups.google.com/groups?th=589c20eee24735de, > http://groups.google.com/groups?th=2946a4c24dd295ae) > > Jan Gray, Gray Research LLC > > >