From: eeburyc@swan.ac.uk (Colin Bury) Newsgroups: comp.arch.fpga Subject: Clock multiplier/ADPLL in PLD Date: 1 Mar 2002 04:41:20 -0800 Organization: http://groups.google.com/ Lines: 18 Message-ID: <63533cbc.0203010441.75580a5a@posting.google.com> NNTP-Posting-Host: 137.44.158.146 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1014986480 8612 127.0.0.1 (1 Mar 2002 12:41:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Mar 2002 12:41:20 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!novia!novia!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14810 Hi, I need to multiply a clock from around 44kHz to 11MHz, to be implemented in a Lattice ISP (Programmable Logic) device. Does anyone know of how to implement a clock multiplier in VHDL/Verilog or have any schematics or references? I am considering trying to implement an All-Digital PLL (due to noise considerations I would prefer not use an analogue VCO), does anyone have any idea/know of any references on how to do this? Am I being stupid, or is it possible to implement this without using a high frequency external reference clock? Any help would be greatly appreciated. Colin Bury eeburyc@swan.ac.uk University of Wales Swansea ###### Message-ID: <3C7F9590.67DCD197@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Clock multiplier/ADPLL in PLD References: <63533cbc.0203010441.75580a5a@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 46 Date: Fri, 01 Mar 2002 14:47:13 GMT NNTP-Posting-Host: 68.14.84.212 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1014994033 68.14.84.212 (Fri, 01 Mar 2002 09:47:13 EST) NNTP-Posting-Date: Fri, 01 Mar 2002 09:47:13 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!isdnet!sn-xit-02!supernews.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14772 For a digital PLL, you'll need a master clock that is higher than your target frequency. Typically, you'll need something that is at least 16x, which puts the design frequency near the upper limit of what you'll be able to do in the device. The higher your master, the smaller the resulting jitter. You could put a ring oscillator in your design to generate a high frequency master. The ring oscillator's frequency would be sensitive to temperature, supply voltage and possibly the phase of the moon, but since you would be using for a reference in a DPLL, the drift would probably be OK as long as it wasn't fast compared to your output frequency. The other option would be to implement a delay lock loop, although I think the delay granularity possible in the CPLD may make that impractical. Colin Bury wrote: > Hi, > > I need to multiply a clock from around 44kHz to 11MHz, to be > implemented in a Lattice ISP (Programmable Logic) device. > > Does anyone know of how to implement a clock multiplier in > VHDL/Verilog or have any schematics or references? > I am considering trying to implement an All-Digital PLL (due to noise > considerations I would prefer not use an analogue VCO), does anyone > have any idea/know of any references on how to do this? > Am I being stupid, or is it possible to implement this without using a > high frequency external reference clock? > > Any help would be greatly appreciated. > > Colin Bury > eeburyc@swan.ac.uk > University of Wales Swansea -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3C7FB5F7.B826C97C@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Clock multiplier/ADPLL in PLD References: <63533cbc.0203010441.75580a5a@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 51 Date: Fri, 01 Mar 2002 17:10:16 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1015002616 192.65.17.17 (Fri, 01 Mar 2002 10:10:16 MST) NNTP-Posting-Date: Fri, 01 Mar 2002 10:10:16 MST Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14829 My thoughts are that you'll need a high(er) frequency external clock of some kind. What are your jitter requirements on the 11MHz? If you just need an average of 11MHz and you can skip an entire clock cycle (90ns jitter), a digital PLL can be designed pretty easily. If you can get by with a few ns of jitter, there are techniques that can still produce good results without going to extremes, but that's in brand X devices. You'll most probably end up with a tradeoff of jitter versus external frequency to deal with. Think of a digital PLL as an arithmetic equivalent of an analog PLL and you may see how to design the DPLL with limited logic requirements (phase comparator provides an error in counts of the high frequency reference, the CRC 2nd order filter can be approximated with some shift and accumulation, the VCO is realized as a phase accumulator based off the high speed clock). The Xilinx Virtex-II devices have some nice internal digital clock management units that can provide high speed clocks (based on at least 25MHz input frequency) with variable phase values and "global clock mux" elements that allow glitchless switching between phases to end up with a *very* resolute clock (in digital terms) without breaking the bank in the smallest device of the family. But Lattice? Dunno. - John_H Colin Bury wrote: > Hi, > > I need to multiply a clock from around 44kHz to 11MHz, to be > implemented in a Lattice ISP (Programmable Logic) device. > > Does anyone know of how to implement a clock multiplier in > VHDL/Verilog or have any schematics or references? > I am considering trying to implement an All-Digital PLL (due to noise > considerations I would prefer not use an analogue VCO), does anyone > have any idea/know of any references on how to do this? > Am I being stupid, or is it possible to implement this without using a > high frequency external reference clock? > > Any help would be greatly appreciated. > > Colin Bury > eeburyc@swan.ac.uk > University of Wales Swansea ###### Message-ID: <3C7FD459.71154155@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Clock multiplier/ADPLL in PLD References: <63533cbc.0203010441.75580a5a@posting.google.com> <3C7FB5F7.B826C97C@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 75 Date: Fri, 01 Mar 2002 19:15:09 GMT NNTP-Posting-Host: 68.14.84.212 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1015010109 68.14.84.212 (Fri, 01 Mar 2002 14:15:09 EST) NNTP-Posting-Date: Fri, 01 Mar 2002 14:15:09 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!netnews.com!feed2.news.rcn.net!rcn!feeder.qis.net!sn-xit-02!supernews.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14762 you are the second to mention the Xilinx DLLs/DCMs. Unfortunately, they are of no use here since the input clock is only 44 KHz, and even the desired output is less than half the minimum frequency for those blocks. As for the DPLL, it is not really a direct port from an analog PLL, there are usually no filters per se. Instead, the 'filtering' is done by the counters. Actel has an app note on doing DPLLs in FPGAs that is fairly decent. see http://www.actel.com/appnotes/s04_18.pdf. You might also look at some of the old DPLL device data sheets. You'll still need some source of clock that is faster than your intended output. As I mentioned earlier, if adding an extra external clock is unacceptable, you may be able to use a ring oscillator in the design. John_H wrote: > My thoughts are that you'll need a high(er) frequency external clock of > some kind. What are your jitter requirements on the 11MHz? If you just > need an average of 11MHz and you can skip an entire clock cycle (90ns > jitter), a digital PLL can be designed pretty easily. If you can get by > with a few ns of jitter, there are techniques that can still produce good > results without going to extremes, but that's in brand X devices. > > You'll most probably end up with a tradeoff of jitter versus external > frequency to deal with. > > Think of a digital PLL as an arithmetic equivalent of an analog PLL and > you may see how to design the DPLL with limited logic requirements (phase > comparator provides an error in counts of the high frequency reference, > the CRC 2nd order filter can be approximated with some shift and > accumulation, the VCO is realized as a phase accumulator based off the > high speed clock). > > The Xilinx Virtex-II devices have some nice internal digital clock > management units that can provide high speed clocks (based on at least > 25MHz input frequency) with variable phase values and "global clock mux" > elements that allow glitchless switching between phases to end up with a > *very* resolute clock (in digital terms) without breaking the bank in the > smallest device of the family. > > But Lattice? Dunno. > > - John_H > > Colin Bury wrote: > > > Hi, > > > > I need to multiply a clock from around 44kHz to 11MHz, to be > > implemented in a Lattice ISP (Programmable Logic) device. > > > > Does anyone know of how to implement a clock multiplier in > > VHDL/Verilog or have any schematics or references? > > I am considering trying to implement an All-Digital PLL (due to noise > > considerations I would prefer not use an analogue VCO), does anyone > > have any idea/know of any references on how to do this? > > Am I being stupid, or is it possible to implement this without using a > > high frequency external reference clock? > > > > Any help would be greatly appreciated. > > > > Colin Bury > > eeburyc@swan.ac.uk > > University of Wales Swansea -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3C801729.D7B42F91@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Clock multiplier/ADPLL in PLD References: <63533cbc.0203010441.75580a5a@posting.google.com> <3C7FB5F7.B826C97C@mail.com> <3C7FD459.71154155@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Sat, 02 Mar 2002 00:04:55 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@opbu.xerox.com X-Trace: news-west.eli.net 1015027495 192.65.17.17 (Fri, 01 Mar 2002 17:04:55 MST) NNTP-Posting-Date: Fri, 01 Mar 2002 17:04:55 MST Organization: Xerox Officeprinting NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!out.nntp.be!propagator-SanJose!in.nntp.be!nntp-relay.ihug.net!ihug.co.nz!logbridge.uoregon.edu!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14827 I stated that the DCMs need a 25MHz reference. I read that the system has 44kHz. I was suggesting using the parallel to an analog PLL rather than the DPLLs you see in USB implementations which require significant timing content in the signal the clock is derived from. A phase error detector is emulated by a counter. The 'filtering' is done with shifts and accumulators to mimic the analog filters. The VCO is approximated with a phase accumulator that can leverage the DCMs and global clock muxes to give better jitter characteristics than with a high frequency clock alone. The approach I tried to suggest goes into digital frequency synthesis with the closed-loop approach of an Analog PLL. A system can be designed without abrupt changes in frequency and with other characteristics favorable to analog PLLs without the noise issues inherent in the analog system. My apologies if implementing an analog PLL in the digital realm is too much of a deviation from the "classical" DPLL to effectively communicate the concept. - John_H Ray Andraka wrote: > you are the second to mention the Xilinx DLLs/DCMs. Unfortunately, they are > of no use here since the input clock is only 44 KHz, and even the desired > output is less than half the minimum frequency for those blocks. As for the > DPLL, it is not really a direct port from an analog PLL, there are usually no > filters per se. Instead, the 'filtering' is done by the counters.