From: =?iso-8859-1?Q?St=E9phane?= Guyetant Newsgroups: comp.arch.fpga Subject: SDRAM+FPGA Date: Wed, 27 Feb 2002 19:21:39 +0100 Organization: IRISA, Campus de Beaulieu, 35042 Rennes Cedex, FRANCE Lines: 22 Message-ID: <3C7D23B3.9D2FDF38@irisa.fr> NNTP-Posting-Host: curry.irisa.fr Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.irisa.fr 1014834101 18659 131.254.61.68 (27 Feb 2002 18:21:41 GMT) X-Complaints-To: usenet@irisa.fr NNTP-Posting-Date: 27 Feb 2002 18:21:41 GMT X-Mailer: Mozilla 4.79 [en] (X11; U; SunOS 5.8 sun4u) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!freenix!enst!univ-angers.fr!news.univ-brest.fr!news.crihan.fr!univ-rennes1.fr!irisa.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14719 I am interfacing a 256MB SDRAM to a Spartan2. 1) As I don't know yet at which frequency my RAM controller will run on the FPGA, I am wondering if I can link directly the clk input to a FPGA I/O pin. I don't expect this frequency to be over 66ish Mhz. 2) Do I need to use the Board Level Deskew method described on Xilinx web site(XAPP174) ? I have only one RAM chip which should be close to the FPGA. 3) By the way, what means on the RAM spec that some supply pins (VddQ and VssQ for this Micron chip) are "isolated DQ power (or gnd) to the die ..." Shall I put some capacitors there? Regards, Stephane ###### From: kayrock66@yahoo.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: SDRAM+FPGA Date: 27 Feb 2002 17:17:40 -0800 Organization: http://groups.google.com/ Lines: 44 Message-ID: References: <3C7D23B3.9D2FDF38@irisa.fr> NNTP-Posting-Host: 208.178.183.62 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1014859060 21497 127.0.0.1 (28 Feb 2002 01:17:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 28 Feb 2002 01:17:40 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14742 read below... Stéphane Guyetant wrote in message news:<3C7D23B3.9D2FDF38@irisa.fr>... > I am interfacing a 256MB SDRAM to a Spartan2. > > 1) > As I don't know yet at which frequency my RAM controller will run on the > FPGA, I am wondering if I can link directly the clk input to a FPGA I/O > pin. > I don't expect this frequency to be over 66ish Mhz. No, this isn't the best way to do it, regardless of frequency (look under hold violations). And you should be so lucky to get a 66MHz auto P&R sdram controller. > 2) > Do I need to use the Board Level Deskew method described on Xilinx web > site(XAPP174) ? > I have only one RAM chip which should be close to the FPGA. Yes, this is the way to do it (if I'm thinking about the same XAPP.) The issue is that the clock distribution network on the die puts a large and variable delay between the clock input pin on the Spartan and the flop clock port. You need to deskew to match the board clock edges. > 3) > By the way, what means on the RAM spec that some supply pins (VddQ and > VssQ for this Micron chip) are "isolated DQ power (or gnd) to the die > ..." > Shall I put some capacitors there? I don't have the spec in front of me, but I would venture to guess that these are the supply pins for those beefy data line drivers. They are seperate on the DIMM because they don't want to upset the rest of the sdram die when all those outputs start pouring electrons into your bus capacitance all at once. And yes, I would bypass these pins and them bring them directly to your power plane. > > Regards, > Stephane Regards!