From: kingcoolking@rediffmail.com (king) Newsgroups: comp.arch.fpga Subject: Comparison between two FPGAs- what is decisive factor? Date: 25 Feb 2002 04:35:03 -0800 Organization: http://groups.google.com/ Lines: 10 Message-ID: NNTP-Posting-Host: 164.164.56.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1014640503 22022 127.0.0.1 (25 Feb 2002 12:35:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 25 Feb 2002 12:35:03 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14649 Hi all, I have a design which uses say X no of XCV1000E FPGAs. I wud like to go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is approximately 1.5 Million while in XC2V6000 is 6 Million. So can I assume that the logic implemented in four (6/1.5) FPGAs can be implemented using a single XC2V6000 FPGAs? But the LUTs of the two looks different. Will this affect the beforesaid ratio? Or is there any other decisive factors involved? Ur reply will be most welcom with kind regs king ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Comparison between two FPGAs- what is decisive factor? Date: 25 Feb 2002 21:15:19 +0100 Organization: My own Private Self Lines: 33 Message-ID: <6u7kp1gvxk.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1014668119 385 10.0.3.2 (25 Feb 2002 20:15:19 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 25 Feb 2002 20:15:19 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:14653 kingcoolking@rediffmail.com (king) writes: > The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? No. The XC2V6000 gains a larger part of its total gates from BRAMs and its multiplier units. > But the LUTs of the two > looks different. The LUTs are identical 4-input type. The CLBs are different, having 4 vs 8 LUTs in them. > Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? LUT count is the thing to compare: XCV1000E: 64x96x4=24576 XC2V6000: 96x88x8=67584 So you will get 67584/24576=2.75 more logic per chip. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: kayrock66@yahoo.com (Jay) Newsgroups: comp.arch.fpga Subject: Re: Comparison between two FPGAs- what is decisive factor? Date: 25 Feb 2002 13:59:07 -0800 Organization: http://groups.google.com/ Lines: 28 Message-ID: References: NNTP-Posting-Host: 208.178.183.62 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1014674347 6282 127.0.0.1 (25 Feb 2002 21:59:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 25 Feb 2002 21:59:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!cyclone.bc.net!logbridge.uoregon.edu!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14704 IMHO the key number is the number of logic cells. Ignore the 6M gate numbers and compare logic cells. That 6M number is taking some gate equivalency for ram which most designers consider seperately from their logic. So add up the logic cells and use that to compare density. The single part solution is nice because its cute, but something to keep in mind is that if your design can be partitioned in a smart way, you can P&R each section of the design seperately. And since P&R times seem to be exponential with size, there is a P&R big time savings to going with smaller parts. This way you P&R just the section you have changed. Our XC2V6000 takes all night to re-run, and sometimes we only changed a few lines of code in one place. Regards kingcoolking@rediffmail.com (king) wrote in message news:... > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? Ur reply will be most welcom > with kind regs > king ###### From: assaf_sarfati@yahoo.com (Assaf Sarfati) Newsgroups: comp.arch.fpga Subject: Re: Comparison between two FPGAs- what is decisive factor? Date: 25 Feb 2002 21:47:46 -0800 Organization: http://groups.google.com/ Lines: 23 Message-ID: <44b0ca4e.0202252147.6945c67b@posting.google.com> References: NNTP-Posting-Host: 62.90.193.22 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1014702466 17822 127.0.0.1 (26 Feb 2002 05:47:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 26 Feb 2002 05:47:46 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14705 kingcoolking@rediffmail.com (king) wrote in message news:... > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? Ur reply will be most welcom > with kind regs > king If you have a working design you probably have a working tool-chain. Try to write a wrapper above your X chips, keeping all internal connections inside it and defining as ports everything that goes out (if you have a working HDL test-bench for the whole design, you can use it as template). Run this design through the tool-chain, selecting the new target device (Virtex2 or whatever you like) and see the reported size. Of course the reported size will not be 100% accurate, but you'll get an very good approximation; it's not a good idea to fill up an FPGA anyway - best not to go above 70% utilization unless the design is absolutely frozen and you want to save every last penny in production BOM. ###### Message-ID: <3C7ED765.C6A39560@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Comparison between two FPGAs- what is decisive factor? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 Date: Fri, 01 Mar 2002 01:16:01 GMT NNTP-Posting-Host: 68.14.84.212 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1014945361 68.14.84.212 (Thu, 28 Feb 2002 20:16:01 EST) NNTP-Posting-Date: Thu, 28 Feb 2002 20:16:01 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!feeder.qis.net!sn-xit-02!supernews.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14770 Nope, different marketing gates. The virtexII has a higher concentration of memory, plus the multipliers contribute to the gate count. You will need to compare the number of slices, which will leave you somewhat less than 3:1 when comparing 2V6000 to 1000E. Also, it is worth noting that the cost is more or less exponential with device size. For a given number of slices, rather than a given number of marketing gates (and ignoring the other goodies) the VIrtexE is very competitive. king wrote: > Hi all, > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > assume that the logic implemented in four (6/1.5) FPGAs can be > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > looks different. Will this affect the beforesaid ratio? Or is there > any other decisive factors involved? Ur reply will be most welcom > with kind regs > king -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Comparison between two FPGAs- what is decisive factor? Date: Fri, 1 Mar 2002 10:47:22 -0000 Message-ID: <1014989839.3662.0.nnrp-14.9e9832fa@news.demon.co.uk> References: <3C7ED765.C6A39560@andraka.com> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 1014989839 nnrp-14:3662 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Lines: 43 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14823 And the routing resources (and speed) steadily increase as the generations advance. For some applications this can be decisive. Which sadly means that the only certain guide for your design is a trial implementation. Ray Andraka wrote: > Nope, different marketing gates. The virtexII has a higher concentration > of memory, plus the multipliers contribute to the gate count. You will > need to compare the number of slices, which will leave you somewhat less > than 3:1 when comparing 2V6000 to 1000E. Also, it is worth noting that > the cost is more or less exponential with device size. For a given number > of slices, rather than a given number of marketing gates (and ignoring the > other goodies) the VIrtexE is very competitive. > > king wrote: > > > Hi all, > > I have a design which uses say X no of XCV1000E FPGAs. I wud like to > > go for denser FPGAs ( XC2V6000). The total system gates in XCV1000E is > > approximately 1.5 Million while in XC2V6000 is 6 Million. So can I > > assume that the logic implemented in four (6/1.5) FPGAs can be > > implemented using a single XC2V6000 FPGAs? But the LUTs of the two > > looks different. Will this affect the beforesaid ratio? Or is there > > any other decisive factors involved? Ur reply will be most welcom > > with kind regs > > king > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >