From: rk Newsgroups: comp.arch.fpga Subject: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: Tue, 05 Feb 2002 17:07:23 -0500 Organization: Just an OldEngineer Lines: 18 Message-ID: <3C60579B.D6464137@nospamplease.erols.com.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZr1ZZEnCCps191tKI7ayWB0IN2uqafvp0xscyP1/850FBAHuBtGocd X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 5 Feb 2002 22:03:53 GMT X-Mailer: Mozilla 4.73 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13980 Hi, A friend asked me a question and perhaps someone out there can help. There was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what manufacturer and model) and the claim was that groundbounce in the FPGA from SSO's caused the SDRAM to latchup; this was supposed to explain a functional failure that would be cleared by cycling the power. That sounds a bit odd to me, although I haven't used SDRAM and am not familiar with their details. For a low, quiet output, they measured a 710 mV peak below ground; that doesn't sound too bad, about a diode drop. Again, I don't know what's going on inside SDRAM technology so I thought I'd ask and see if anyone has any experience with this. Thanks in advance, -- Just an OldEngineer ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: Tue, 05 Feb 2002 14:32:26 -0800 Organization: Xilinx Lines: 127 Message-ID: <3C605D7A.F027ECC4@xilinx.com> References: <3C60579B.D6464137@nospamplease.erols.com.invalid> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------472B2B391712B18C28D08B3A" X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!prairie.attcanada.net!newsfeed.attcanada.net!12.127.17.144!attbt1!attbt2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13985 --------------472B2B391712B18C28D08B3A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit RK, The concern is that if you inject enough current below ground, and forward bias the parasitic SCR structure, you may cause latchup. A few years ago we were really worried about this for 4K (a customer had done no signal integrity engineering, and created an SI nightmare for his company), so we wired 128 outputs through 1 foot of transmssion lines (50 ohm coax) to 128 inputs in order to provide the horrendous overshoot and undershoot required. We were slamming > 20 mA on each and every pin, both above 3.3 Vdc and below 0.0 V by as much as .71 volts (after all, the diode is clamping as hard as it can, so voltage doesn't tell you anything at all--you need to know the current). No problem. It seems that to trigger the SCR latchup, it requires a steady currents for many tens of nanoseconds, at currents greater than 300 mA for the entire edge, at a voltage above or below ground by a diode drop. These tests were done on 4Kxl and 4Kxla, which had almost identical 0.35u IO transistor structures. Bottom line, don't do that! Even if the design doesn't latch up, it will have incredible jitter, and probably have other problems caused by all of that ground bounce. Any voltage that causes the diodes to be forward biased is going to lead to problems, one way or another. As "just an old engineer" you should be familiar with signal integrity from the days when being an engineer meant you knew what Ldi/dt meant, and knew how to calculate the voltage at the end of a transmission line. Now latching up the SDRAM might well be possible (maybe they didn't have time to characterize the parasitic SCR structure, or to control the alphas of the npnp stucture), but don't blame the FPGA! If you hit it with a hammer, it would break, too. Is it the hammer's fault? Austin rk wrote: > Hi, > > A friend asked me a question and perhaps someone out there can help. There > was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what > manufacturer and model) and the claim was that groundbounce in the FPGA > from SSO's caused the SDRAM to latchup; this was supposed to explain a > functional failure that would be cleared by cycling the power. > > That sounds a bit odd to me, although I haven't used SDRAM and am not > familiar with their details. For a low, quiet output, they measured a 710 > mV peak below ground; that doesn't sound too bad, about a diode drop. > Again, I don't know what's going on inside SDRAM technology so I thought > I'd ask and see if anyone has any experience with this. > > Thanks in advance, > > -- > Just an OldEngineer --------------472B2B391712B18C28D08B3A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit RK,

The concern is that if you inject enough current below ground, and forward bias the parasitic SCR structure, you may cause latchup.  A few years ago we were really worried about this for 4K (a customer had done no signal integrity engineering, and created an SI nightmare for his company), so we wired 128 outputs through 1 foot of transmssion lines (50 ohm coax) to 128 inputs in order to provide the horrendous overshoot and undershoot required.  We were slamming > 20 mA on each and every pin, both above 3.3 Vdc and below 0.0 V by as much as .71 volts (after all, the diode is clamping as hard as it can, so voltage doesn't tell you anything at all--you need to know the current).

No problem.

It seems that to trigger the SCR latchup, it requires a steady currents for many tens of nanoseconds, at currents greater than 300 mA for the entire edge, at a voltage above or below ground by a diode drop.

These tests were done on 4Kxl and 4Kxla, which had almost identical 0.35u IO transistor structures.

Bottom line, don't do that!  Even if the design doesn't latch up, it will have incredible jitter, and probably have other problems caused by all of that ground bounce.  Any voltage that causes the diodes to be forward biased is going to lead to problems, one way or another.  As "just an old engineer" you should be familiar with signal integrity from the days when being an engineer meant you knew what Ldi/dt meant, and knew how to calculate the voltage at the end of a transmission line.

Now latching up the SDRAM might well be possible (maybe they didn't have time to characterize the parasitic SCR structure, or to control the alphas of the npnp stucture), but don't blame the FPGA!  If you hit it with a hammer, it would break, too.  Is it the hammer's fault?

Austin
 
 
 

rk wrote:

Hi,

A friend asked me a question and perhaps someone out there can help.  There
was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what
manufacturer and model) and the claim was that groundbounce in the FPGA
from SSO's caused the SDRAM to latchup; this was supposed to explain a
functional failure that would be cleared by cycling the power.

That sounds a bit odd to me, although I haven't used SDRAM and am not
familiar with their details.  For a low, quiet output, they measured a 710
mV peak below ground; that doesn't sound too bad, about a diode drop.
Again, I don't know what's going on inside SDRAM technology so I thought
I'd ask and see if anyone has any experience with this.

Thanks in advance,

--
Just an OldEngineer

--------------472B2B391712B18C28D08B3A-- ###### From: rk Newsgroups: comp.arch.fpga Subject: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: Tue, 05 Feb 2002 21:47:26 -0500 Organization: Just an OldEngineer Lines: 132 Message-ID: <3C60993E.27877A19@nospamplease.erols.com.invalid> References: <3C60579B.D6464137@nospamplease.erols.com.invalid> <3C605D7A.F027ECC4@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYXPSyG0DQKu58LJ2W8kFfe05TioHfDO8w8w7Ew64jFeTqm1TOYTiyP X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 6 Feb 2002 02:43:57 GMT X-Mailer: Mozilla 4.73 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!13184!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13981 Hi, Thanks for the quick response; comments embedded below. Austin Lesea wrote: > > RK, It's rk, not RK. It looks funny in big letters. ;-) > The concern is that if you inject enough current below ground, and > forward bias the parasitic SCR structure, you may cause latchup. A few > years ago we were really worried about this for 4K (a customer had done > no signal integrity engineering, and created an SI nightmare for his > company), so we wired 128 outputs through 1 foot of transmssion lines (50 > ohm coax) to 128 inputs in order to provide the horrendous overshoot and > undershoot required. We were slamming > 20 mA on each and every pin, > both above 3.3 Vdc and below 0.0 V by as much as .71 volts (after all, > the diode is clamping as hard as it can, so voltage doesn't tell you > anything at all--you need to know the current). Yup; I was just relaying what I had. Another engineer went to a meeting and brought back a set of viewgraphs. They simply had recorded one parameter of the ground bounce, max voltage. Also, I don't have a physical model of the board so I don't know how long the lines were, how many loads on it, nada. From the cartoon that they showed, it didn't look like it was clamping; it was just a tiny little peak, no flat top. It was not an oscilloscope picture. Based on the XQR400XL data sheet, it didn't seem like there should be a problem in the FPGA, although some people were saying it might have latched up. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. They didn't have a time scale on the picture or currents. 200 mA on a whole pile of pins is a whole mess of current. Doubt they did that for 10 ns. > No problem. > > It seems that to trigger the SCR latchup, it requires a steady currents > for many tens of nanoseconds, at currents greater than 300 mA for the > entire edge, at a voltage above or below ground by a diode drop. > > These tests were done on 4Kxl and 4Kxla, which had almost identical 0.35u > IO transistor structures. This was, as far as I know, an XQR device, although I'm not sure. Info is sketchy. :-( > Bottom line, don't do that! Yikes! I didn't do anything! > Even if the design doesn't latch up, it will > have incredible jitter, and probably have other problems caused by all of > that ground bounce. Any voltage that causes the diodes to be forward > biased is going to lead to problems, one way or another. As "just an old > engineer" you should be familiar with signal integrity from the days when > being an engineer meant you knew what Ldi/dt meant, and knew how to > calculate the voltage at the end of a transmission line. Yup. I don't like designs that turn on the diodes at all. But that's just me. > Now latching up the SDRAM might well be possible (maybe they didn't have > time to characterize the parasitic SCR structure, or to control the > alphas of the npnp stucture), but don't blame the FPGA! If you hit it > with a hammer, it would break, too. Is it the hammer's fault? I blame no one. Yet. ;-) I just hadn't messed with DRAMs in a while, been using SRAMs, and don't know how susceptible the devices were to latch up. The last few times I did DRAM designs, I was very, Very, VERY careful to have nicely terminated lines, controlled impedance boards, and did not allow the signals to go below ground or above Vcc and didn't have any problems. From what I can tell from the little bit of information that I have, they didn't have terminated signals and were using high-slew outputs from the FPGA. They apparently didn't test the SDRAMs for latchup from driving inputs below ground as part of the failure report. Me, being a bit lazy, don't want to have to set that up and do that. So I was hoping someone here might have some experience with more modern SDRAMs. Thanks! -- rk Just an OldEngineer > > Austin > > > > > rk wrote: > > > Hi, > > > > A friend asked me a question and perhaps someone out there can help. > > There > > was a Xilinx 4036XL hooked up to an SDRAM (no, he didn't know what > > manufacturer and model) and the claim was that groundbounce in the FPGA > > > > from SSO's caused the SDRAM to latchup; this was supposed to explain a > > functional failure that would be cleared by cycling the power. > > > > That sounds a bit odd to me, although I haven't used SDRAM and am not > > familiar with their details. For a low, quiet output, they measured a > > 710 > > mV peak below ground; that doesn't sound too bad, about a diode drop. > > Again, I don't know what's going on inside SDRAM technology so I > > thought > > I'd ask and see if anyone has any experience with this. > > > > Thanks in advance, > > > > -- > > Just an OldEngineer ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: 06 Feb 2002 16:31:20 +0000 Organization: TRW Conekt Lines: 40 Sender: Thompsm@977845-DT Message-ID: References: <3C60579B.D6464137@nospamplease.erols.com.invalid> <3C605D7A.F027ECC4@xilinx.com> <3C60993E.27877A19@nospamplease.erols.com.invalid> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1013013060 44285059 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13982 rk writes: > > I just hadn't messed with DRAMs in a while, been using SRAMs, and don't > know how susceptible the devices were to latch up. The last few times I > did DRAM designs, I was very, Very, VERY careful to have nicely terminated > lines, controlled impedance boards, and did not allow the signals to go > below ground or above Vcc and didn't have any problems. From what I can > tell from the little bit of information that I have, they didn't have > terminated signals and were using high-slew outputs from the FPGA. They > apparently didn't test the SDRAMs for latchup from driving inputs below > ground as part of the failure report. Me, being a bit lazy, don't want to > have to set that up and do that. So I was hoping someone here might have > some experience with more modern SDRAMs. > According to my Micron datasheet (MT48LC64M4A2): PARAMETER/CONDITION SYMBO L MIN MAX UNITS INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD + 0.3 V INPUT LOW VOLTAGE : Logic 0; All inputs VIL -0.3 0.8 V And the associated footnote: VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width = 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width = 3ns. HTH! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: Mike Treseler Newsgroups: comp.arch.fpga Subject: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: Wed, 06 Feb 2002 10:32:55 -0800 Organization: Fluke Networks Lines: 28 Message-ID: <3C6176D7.8C3E50CB@flukenetworks.com> References: <3C60579B.D6464137@nospamplease.erols.com.invalid> NNTP-Posting-Host: slick.tc.fluke.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.4.7-4GB i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!newspush.london1.eu.level3.net!level3eu!newsfeed.mathworks.com!nycmny1-snh1.gtei.net!evrtwa1-snf1.gtei.net!news.gtei.net!fluke!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14000 rk wrote: > the claim was that groundbounce in the FPGA > from SSO's caused the SDRAM to latchup; this was supposed to explain a > functional failure that would be cleared by cycling the power. Any CMOS device can latch up if device pins are forced below ground with enough energy. CMOS wells and substrates combine to form unintended n-p-n-p (SCR) structures. If these get triggered you get a a pretty good short from power to ground through the device. This may destroy the chip, or if you are lucky, requires a power cycle to turn off the SCR. To fix this, you need a better ground plane and/or better supply bypassing. > For a low, quiet output, they measured a 710 > mV peak below ground; that doesn't sound too bad, That is above the maximum low value for most devices, another indication an inadequate ground plane. -- Mike Treseler ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible? Date: Wed, 06 Feb 2002 15:49:02 -0800 Organization: Xilinx Lines: 46 Message-ID: <3C61C0EE.14176C0A@xilinx.com> References: <3C60579B.D6464137@nospamplease.erols.com.invalid> <3C6176D7.8C3E50CB@flukenetworks.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:14023 Mike, One can design the circuits and the process so the inputs can't latch up. It is related to the beta (or alpha) of the parasitic npn and pnp transistors that are connected in an SCR arangement. It turns out that there are process tricks, implants, etc. that are done to minimize the gain so that the scr can't stay ON. Too bad the SDRAM folks had to get to market so fast.... Of course, it helps to have been there and done that. Austin Mike Treseler wrote: > rk wrote: > > the claim was that groundbounce in the FPGA > > from SSO's caused the SDRAM to latchup; this was supposed to explain a > > functional failure that would be cleared by cycling the power. > > Any CMOS device can latch up if device pins > are forced below ground with enough energy. > > CMOS wells and substrates combine to form > unintended n-p-n-p (SCR) structures. > > If these get triggered you get a > a pretty good short from power to > ground through the device. > > This may destroy the chip, or if you are lucky, > requires a power cycle to turn off the SCR. > > To fix this, you need a better ground plane > and/or better supply bypassing. > > > For a low, quiet output, they measured a 710 > > mV peak below ground; that doesn't sound too bad, > > That is above the maximum low value for most devices, > another indication an inadequate ground plane. > > -- Mike Treseler