From: Steven Derrien Newsgroups: comp.arch.fpga,comp.arch.embdedded Subject: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Mon, 28 Jan 2002 14:06:25 +0100 Organization: INRIA - RENNES Lines: 51 Message-ID: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: spyder.irisa.fr Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.irisa.fr 1012223185 29645 131.254.51.10 (28 Jan 2002 13:06:25 GMT) X-Complaints-To: usenet@irisa.fr NNTP-Posting-Date: 28 Jan 2002 13:06:25 GMT X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en, fr Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!fr.usenet-edu.net!usenet-edu.net!ciril.fr!univ-angers.fr!univ-rennes1.fr!irisa.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13879 Hello, This post is just for submitting an idea to those who are familiar with embedded system design, in order to get some feed-back (with respect to feasibility, cost, usefulness and so on…). The basic idea is the following : We want to design a reconfigurable SoC, which will be connected to an IDE hard-drive, used by the application running on the SoC. One of the key point, is that we need to perform dynamic reconfiguration of the FPGA. Our idea is to use the Hard-drive memory to store the various FPGA configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA reconfiguration from the HDD. (the 8051 would share the IDE bus with the FPGA, but they would have a mutual exclusive use of the HDD, since the MCU would only be used during reconfiguration) Since the FPGA should be a relatively big Virtex/Spartan-II, and since a large density configuration EEPROMs (several Mbits) are quite expensive compared to a small MCU, we feel that this could be a nice way to reduce the total system cost. Now we are wondering whether this idea is good or not :), we are specifically concerned with : - PCB layout and signal integrity problems due to the fact that the IDE connection is shared between the MCU and the FPGA. For ex. would it be possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? - Reliability : since the hard-drive will be used for both read and write operation during the application, we must ensure that some part of the HDD storage is locked (to guarantee that the configurations are not overwritten by mistake) - Feasibility : How difficult would it be to design and debug such a system ? Any advice, comments, critics, ideas are welcome, Thank you in advance. Steven ###### Reply-To: "Paul" From: "Paul" Newsgroups: comp.arch.fpga,comp.arch.embedded References: <3C554CD1.893D0AA0@irisa.fr> Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Lines: 9 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: Date: Mon, 28 Jan 2002 13:41:51 -0000 NNTP-Posting-Host: 62.252.188.55 X-Complaints-To: abuse@ntlworld.com X-Trace: news11-gui.server.ntli.net 1012225096 62.252.188.55 (Mon, 28 Jan 2002 13:38:16 GMT) NNTP-Posting-Date: Mon, 28 Jan 2002 13:38:16 GMT Organization: ntlworld News Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!diablo.theplanet.net!newspeer.clara.net!news.clara.net!peernews!peer.cwci.net!news5-gui.server.ntli.net!ntli.net!news11-gui.server.ntli.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13886 You could try looking at the IDE core at http://www.opencores.org and even a simple CPU core there or at www.free-ip.com It might get you started. Paul ###### From: Steven Derrien Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Mon, 28 Jan 2002 14:49:43 +0100 Organization: INRIA - RENNES Lines: 35 Message-ID: <3C5556F7.6BEAF057@irisa.fr> References: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: spyder.irisa.fr Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.irisa.fr 1012225783 32498 131.254.51.10 (28 Jan 2002 13:49:43 GMT) X-Complaints-To: usenet@irisa.fr NNTP-Posting-Date: 28 Jan 2002 13:49:43 GMT X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en, fr Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!fr.usenet-edu.net!usenet-edu.net!ciril.fr!univ-angers.fr!news!univ-rennes1.fr!irisa.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13881 Paul wrote: > You could try looking at the IDE core at http://www.opencores.org and even a > simple CPU core there or at www.free-ip.com Weel, I might have not been very clear. Right now we want to use a dicrete external 8051 since the FPGA cannot recofnigure itself. Besides we already have some 8051 assembly code to access a IDE drive and to configure a Xilinx FPGA. The operating mode is the following : 1) At boot-up, the FPGA is not configured (all IO in three state), the 8051 fetches configuartion data from the Hard-drive and use this data to configure the FGPA. Once the configuration is done, all the 8051 pind connected to the IDE pins go three state, and the FPGA now has access to the Hard-drive. 2) When the FPGA decides to recofnigure itself, it ask the 8051 by aserting some signal, the 8051 the puts the FPGA in recofniguration mode (all io ion therr state), resets its pins in normal (in or out) mode, anf fetches another configuration data from the hard drive. Once the configuration is done, all the 8051 pind connected to the IDE pins go three state, and the FPGA now has again access to the Hard-drive. Steven > > > It might get you started. > > Paul ###### From: "Bill Blyth" Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Mon, 28 Jan 2002 14:24:57 -0000 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3C554CD1.893D0AA0@irisa.fr> <3C5556F7.6BEAF057@irisa.fr> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Complaints-To: newsabuse@supernews.com Lines: 52 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13757 Have you considered SystemACE from Xilinx. One of the options is to boot from compact flash with relatively large storage. Bill "Steven Derrien" wrote in message news:3C5556F7.6BEAF057@irisa.fr... > > > Paul wrote: > > > You could try looking at the IDE core at http://www.opencores.org and even a > > simple CPU core there or at www.free-ip.com > > Weel, I might have not been very clear. Right now we want to use a dicrete > external 8051 > since the FPGA cannot recofnigure itself. Besides we already have some 8051 > assembly > code to access a IDE drive and to configure a Xilinx FPGA. > > The operating mode is the following : > > 1) At boot-up, the FPGA is not configured (all IO in three state), the 8051 > fetches configuartion data from the Hard-drive and use this data to configure > the FGPA. Once the configuration is done, all the 8051 pind connected to the IDE > pins go three state, and the FPGA now has access to the Hard-drive. > > 2) When the FPGA decides to recofnigure itself, it ask the 8051 by aserting some > signal, the 8051 the puts the FPGA in recofniguration mode (all io ion therr > state), resets its pins in normal (in or out) mode, anf fetches another > configuration data from the hard drive. Once the configuration is done, all the > 8051 pind connected to the IDE pins go three state, and the FPGA now has again > access to the Hard-drive. > > Steven > > > > > > > It might get you started. > > > > Paul > ###### From: Neil Glenn Jacobson Newsgroups: comp.arch.fpga,comp.arch.embdedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Mon, 28 Jan 2002 14:14:13 -0800 Organization: Xilinx, Inc. Lines: 51 Message-ID: <3C55CD35.24CB0BC5@xilinx.com> References: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: krazykat.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (X11; U; SunOS 5.6 sun4u) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!ctu-gate!news.nctu.edu.tw!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13605 An approach that might be easier and cheaper than what you propose is a compact flash and controller-based approach like that provided by Xilinx as the SystemACE CF. Have a look at the web page listed below. http://www.xilinx.com/isp/systemace/systemacecf.htm Steven Derrien wrote: > Hello, > > This post is just for submitting an idea to those who are familiar with > embedded system design, in order to get some feed-back (with respect to > feasibility, cost, usefulness and so on?). > > The basic idea is the following : > > We want to design a reconfigurable SoC, which will be connected to an > IDE hard-drive, used by the application running on the SoC. One of the > key point, is that we need to perform dynamic reconfiguration of the > FPGA. > > Our idea is to use the Hard-drive memory to store the various FPGA > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > FPGA, but they would have a mutual exclusive use of the HDD, since the > MCU would only be used during reconfiguration) > > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a > large density configuration EEPROMs (several Mbits) are quite expensive > compared to a small MCU, we feel that this could be a nice way to reduce > the total system cost. > > Now we are wondering whether this idea is good or not :), we are > specifically concerned with : > > - PCB layout and signal integrity problems due to the fact that the IDE > connection is shared between the MCU and the FPGA. For ex. would it be > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > > - Reliability : since the hard-drive will be used for both read and > write operation during the application, we must ensure that some part of > the HDD storage is locked (to guarantee that the configurations are not > overwritten by mistake) > > - Feasibility : How difficult would it be to design and debug such a > system ? > > Any advice, comments, critics, ideas are welcome, > > Thank you in advance. > Steven ###### From: "Geert Van Doorselaer" Newsgroups: comp.arch.fpga,comp.arch.embdedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Wed, 30 Jan 2002 09:37:36 +0100 Organization: University of Ghent, Belgium Lines: 46 Message-ID: References: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: tfcg7.elis.rug.ac.be X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!naxos.belnet.be!news.belnet.be!inf6serv.rug.ac.be!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13728 > Our idea is to use the Hard-drive memory to store the various FPGA > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > FPGA, but they would have a mutual exclusive use of the HDD, since the > MCU would only be used during reconfiguration) > This means that your FPGA should contain 'code' to access your hard drive. Why not assigning this job to the MCU (as it is already implemented for the (re)configuration of the FPGA). This will create less overhead in your FPGA. > Now we are wondering whether this idea is good or not :), we are > specifically concerned with : The idea itself looks challenging ... If power consumption is not a big issue here ... Why not? > > - PCB layout and signal integrity problems due to the fact that the IDE > connection is shared between the MCU and the FPGA. For ex. would it be > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > Is this 50MHz clock really needed? If not, the MCU can handle this task. > - Feasibility : How difficult would it be to design and debug such a > system ? Less development and debug time when you don't implement the IDE interface on your FPGA. > > Any advice, comments, critics, ideas are welcome, > Just my thoughts ... > Thank you in advance. > Steven > You are welcome, Geert ###### From: Steven Derrien Newsgroups: comp.arch.fpga,comp.arch.embdedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: Wed, 30 Jan 2002 10:33:17 +0100 Organization: INRIA - RENNES Lines: 60 Message-ID: <3C57BDDD.2E891D3E@irisa.fr> References: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: spyder.irisa.fr Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.irisa.fr 1012383198 6030 131.254.51.10 (30 Jan 2002 09:33:18 GMT) X-Complaints-To: usenet@irisa.fr NNTP-Posting-Date: 30 Jan 2002 09:33:18 GMT X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en, fr Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!freenix!jussieu.fr!univ-angers.fr!news!univ-rennes1.fr!irisa.fr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13884 Geert Van Doorselaer wrote: > > Our idea is to use the Hard-drive memory to store the various FPGA > > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > > FPGA, but they would have a mutual exclusive use of the HDD, since the > > MCU would only be used during reconfiguration) > > This means that your FPGA should contain 'code' to access your hard drive. Absolutely ! > > Why not assigning this job to the MCU (as it is already implemented for the > (re)configuration of the FPGA). This will create less overhead in your FPGA. Yes, but the interface is likely to be very slow (in don't imagine getting close to the ATA-5 timing (>33Mhz) with a 80C51). > > Now we are wondering whether this idea is good or not :), we are > > specifically concerned with : > > The idea itself looks challenging ... If power consumption is not a big > issue here ... Why not? > > - PCB layout and signal integrity problems due to the fact that the IDE > > connection is shared between the MCU and the FPGA. For ex. would it be > > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > > > > Is this 50MHz clock really needed? If not, the MCU can handle this task. It is needed, since we want to perform processing on the data stream coming from the hard-drive (we are building a kind of network attached storage device). > > - Feasibility : How difficult would it be to design and debug such a > > system ? > > Less development and debug time when you don't implement the IDE interface > on your FPGA. > > > > > Any advice, comments, critics, ideas are welcome, > > > > Just my thoughts ... Thanks, > > Thank you in advance. > > Steven > > > > You are welcome, > Geert ###### Message-ID: <3C5804E0.21D27B6@soton.sc.philips.com> Date: Wed, 30 Jan 2002 14:36:16 +0000 From: Iwo Mergler X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.4.4 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) References: <3C554CD1.893D0AA0@irisa.fr> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 70 NNTP-Posting-Host: gw-cro01.pgb.philips.com X-Trace: 1012401447 read-nat.news.uk.uu.net 9442 194.201.166.113 X-Complaints-To: abuse@uk.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!newsfeed.online.be!195.129.110.18.MISMATCH!bnewspeer00.bru.ops.eu.uu.net!auucp0.ams.ops.eu.uu.net!bnewsifeed01.bru.ops.eu.uu.net!lnewspost00.lnd.ops.eu.uu.net!emea.uu.net!read-nat.news.uk.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13739 Steven Derrien wrote: > > Hello, > > This post is just for submitting an idea to those who are familiar with > embedded system design, in order to get some feed-back (with respect to > feasibility, cost, usefulness and so on?). > > The basic idea is the following : > > We want to design a reconfigurable SoC, which will be connected to an > IDE hard-drive, used by the application running on the SoC. One of the > key point, is that we need to perform dynamic reconfiguration of the > FPGA. > > Our idea is to use the Hard-drive memory to store the various FPGA > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > FPGA, but they would have a mutual exclusive use of the HDD, since the > MCU would only be used during reconfiguration) > > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a > large density configuration EEPROMs (several Mbits) are quite expensive > compared to a small MCU, we feel that this could be a nice way to reduce > the total system cost. > > Now we are wondering whether this idea is good or not :), we are > specifically concerned with : > > - PCB layout and signal integrity problems due to the fact that the IDE > connection is shared between the MCU and the FPGA. For ex. would it be > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? A standard IDE interface supports 2 devices on the cable, that is, 2 cmos inputs per signal. I have the PCB of an old IDE drive in front of me and it looks like they use a series termination of 330 Ohm between the cable and the ASIC. My suggestion is to have a close look at a modern harddrive and mime that circuitry for your microcontroller. Then you connect the controller instead of the second disk. This way, the micro will load the signals like a slave disk does. For the transfer speeds you are going to achieve with the micro, the weird cable shape shouldn't matter. #============#=====# IDE PORT HDD1 HDD0 #============#=====# FPGA uC HDD > > - Reliability : since the hard-drive will be used for both read and > write operation during the application, we must ensure that some part of > the HDD storage is locked (to guarantee that the configurations are not > overwritten by mistake) I don't think there is an easy way to 'lock' part of the disk without changing the disk's firmware. If you can control the IDE IP in your FPGA, you could ignore write requests for a certain block range... > > - Feasibility : How difficult would it be to design and debug such a > system ? Not having done it myself - it shouldn't be too hard, as long as you have a good logic analyser... ;^) Have a nice day, Iwo ###### Message-ID: <3C585E7C.6D781860@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) References: <3C554CD1.893D0AA0@irisa.fr> <3C5804E0.21D27B6@soton.sc.philips.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 89 Date: Wed, 30 Jan 2002 20:53:03 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1012423983 24.13.238.93 (Wed, 30 Jan 2002 15:53:03 EST) NNTP-Posting-Date: Wed, 30 Jan 2002 15:53:03 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!nntp-relay.ihug.net!ihug.co.nz!hub1.nntpserver.com!peer1-sjc1.usenetserver.com!usenetserver.com!newsfeeds-atl1.usenetserver.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13626 An IDE controller that just does sector reads and sector writes is pretty straightforward in the FPGA. For what you are doing, I suspect that is all you need. The hardest part is digesting the ATA-5 spec. Iwo Mergler wrote: > Steven Derrien wrote: > > > > Hello, > > > > This post is just for submitting an idea to those who are familiar with > > embedded system design, in order to get some feed-back (with respect to > > feasibility, cost, usefulness and so on?). > > > > The basic idea is the following : > > > > We want to design a reconfigurable SoC, which will be connected to an > > IDE hard-drive, used by the application running on the SoC. One of the > > key point, is that we need to perform dynamic reconfiguration of the > > FPGA. > > > > Our idea is to use the Hard-drive memory to store the various FPGA > > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > > FPGA, but they would have a mutual exclusive use of the HDD, since the > > MCU would only be used during reconfiguration) > > > > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a > > large density configuration EEPROMs (several Mbits) are quite expensive > > compared to a small MCU, we feel that this could be a nice way to reduce > > the total system cost. > > > > Now we are wondering whether this idea is good or not :), we are > > specifically concerned with : > > > > - PCB layout and signal integrity problems due to the fact that the IDE > > connection is shared between the MCU and the FPGA. For ex. would it be > > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > > A standard IDE interface supports 2 devices on the cable, that is, 2 cmos > inputs per signal. I have the PCB of an old IDE drive in front of me and > it looks like they use a series termination of 330 Ohm between the cable > and the ASIC. > > My suggestion is to have a close look at a modern harddrive and mime that > circuitry for your microcontroller. Then you connect the controller instead > of the second disk. This way, the micro will load the signals like a slave > disk does. For the transfer speeds you are going to achieve with the micro, > the weird cable shape shouldn't matter. > > #============#=====# > IDE PORT HDD1 HDD0 > > #============#=====# > FPGA uC HDD > > > > > - Reliability : since the hard-drive will be used for both read and > > write operation during the application, we must ensure that some part of > > the HDD storage is locked (to guarantee that the configurations are not > > overwritten by mistake) > > I don't think there is an easy way to 'lock' part of the disk without changing > the disk's firmware. If you can control the IDE IP in your FPGA, you could > ignore write requests for a certain block range... > > > > > - Feasibility : How difficult would it be to design and debug such a > > system ? > > Not having done it myself - it shouldn't be too hard, as long as you have a > good logic analyser... ;^) > > Have a nice day, > > Iwo -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: steen_junk@yahoo.com (Steen Larsen) Newsgroups: comp.arch.fpga,comp.arch.embdedded Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?) Date: 1 Feb 2002 15:04:09 -0800 Organization: http://groups.google.com/ Lines: 68 Message-ID: References: <3C554CD1.893D0AA0@irisa.fr> NNTP-Posting-Host: 134.134.248.26 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1012604649 14598 127.0.0.1 (1 Feb 2002 23:04:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 1 Feb 2002 23:04:09 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13834 Steven, this sounds similar to Paul's MP3 player at www.pjrc.com. An 8051 accesses the storage on an IDE drive and talks to a Xilinx part (not sure of the size, but small, in an 84 PLCC) that buffers to a SIMM DRAM for playback through an MP3 decoder. He is offering the configuration for $150 (minus HD and SIMM) so it is pretty cost-effective. Just some notes on your questions: -Anything over 20MHz PCB trace lengths you pretty much need to simulate trace length and impedances. ( or gamble if you feel lucky...) -I certainly don't know your application, but what about adding a FLASH part to buffer HD data. You could probably find one for about $1 and have a jumper that prevents HD from overwriting the FLASH buffer. If you are doing run-time reconfigurations, maybe having a separate partition on the drive that is unknown to the other users of the drive might be a method... -I think Paul's board is a 4"x5" at four layers. I think the first spin took less than two months. Ask him for more accuracy, but this certainly depends on your expertise. -Steen (respond to steen at tech-forge.com) Steven Derrien wrote in message news:<3C554CD1.893D0AA0@irisa.fr>... > Hello, > > This post is just for submitting an idea to those who are familiar with > embedded system design, in order to get some feed-back (with respect to > feasibility, cost, usefulness and so on…). > > The basic idea is the following : > > We want to design a reconfigurable SoC, which will be connected to an > IDE hard-drive, used by the application running on the SoC. One of the > key point, is that we need to perform dynamic reconfiguration of the > FPGA. > > Our idea is to use the Hard-drive memory to store the various FPGA > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA > reconfiguration from the HDD. (the 8051 would share the IDE bus with the > FPGA, but they would have a mutual exclusive use of the HDD, since the > MCU would only be used during reconfiguration) > > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a > large density configuration EEPROMs (several Mbits) are quite expensive > compared to a small MCU, we feel that this could be a nice way to reduce > the total system cost. > > Now we are wondering whether this idea is good or not :), we are > specifically concerned with : > > - PCB layout and signal integrity problems due to the fact that the IDE > connection is shared between the MCU and the FPGA. For ex. would it be > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ? > > - Reliability : since the hard-drive will be used for both read and > write operation during the application, we must ensure that some part of > the HDD storage is locked (to guarantee that the configurations are not > overwritten by mistake) > > - Feasibility : How difficult would it be to design and debug such a > system ? > > Any advice, comments, critics, ideas are welcome, > > Thank you in advance. > Steven