From: "Fong Chii Biao" Newsgroups: comp.arch.fpga Subject: Dynamic Reconfiguration of single Xilinx FPGA Date: Thu, 24 Jan 2002 22:00:02 +0800 Lines: 15 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 NNTP-Posting-Host: tsk-79-51.tm.net.my X-Original-NNTP-Posting-Host: tsk-79-51.tm.net.my Message-ID: <3c50130f_1@news.tm.net.my> X-Trace: news.tm.net.my 1011880719 tsk-79-51.tm.net.my (24 Jan 2002 21:58:39 +0800) Organization: TMnet Malaysia Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.icl.net!dispose.news.demon.net!demon!news.maxwell.syr.edu!newsfeed.cwix.com!news1.tm.net.my Xref: chonsp.franklin.ch comp.arch.fpga:13495 Hi, i really need help bout this, as i worked for this for a week, no result turns out. first, any one ever try reconfigure Xilinx FPGA using the chip itself? (i'm using a single XC4010XL) the problem is.. when i connect the user I/O to the /program pin, the configuration can't even complete at power start up.. when i disconnect the I/O .. the configuration working pretty well.. whats the solution for this? anyone, anyone at all, who has any idea, ple reply to me, thnaks chiibiao ###### From: "Alex Carreira" Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Thu, 24 Jan 2002 08:50:01 -0700 Organization: University of Calgary Lines: 39 Message-ID: References: <3c50130f_1@news.tm.net.my> NNTP-Posting-Host: @124-121.dialup.ucalgary.ca X-Trace: nserve1.acs.ucalgary.ca 1011887295 51202 136.159.124.121 (24 Jan 2002 15:48:15 GMT) X-Complaints-To: news@ucalgary.ca NNTP-Posting-Date: 24 Jan 2002 15:48:15 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2314.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2314.1300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!newsfeed.direct.ca!look.ca!cyclone.bc.net!rover.ucs.ualberta.ca!news.ucalgary.ca!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13517 I am pretty sure the solution is to try this with a Virtex instead, but first read XAPP 151 and all the others on the configuration architecture. It may be possible on 4000 series but I don't think so (I am guessing that reconfiguration causes functionality to stop during reprogramming of the configuration memory, which is not the case for all scenarios with the Virtex--of course I could be dead wrong about the 4000 series and if so please excuse me). You can find out if it will work the the 4000 series for sure by digging up an in depth ap. note on its configuration architecture (if one exists--I think it does but my memory on the subject is weak right now). I have had discussions with numerous people about reconfiguring a Virtex FPGA with its own resources. It would be particularly slick in RTR (run-time-reconfigurable) applications. A :) Fong Chii Biao wrote in message news:3c50130f_1@news.tm.net.my... > Hi, i really need help bout this, as i worked for this for a week, no result > turns out. > first, any one ever try reconfigure Xilinx FPGA using the chip itself? (i'm > using a single XC4010XL) > > the problem is.. when i connect the user I/O to the /program pin, the > configuration can't even complete at power start up.. > when i disconnect the I/O .. the configuration working pretty well.. whats > the solution for this? > > anyone, anyone at all, who has any idea, ple reply to me, thnaks > > chiibiao > > ###### Message-ID: <3C50430A.1F418834@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA References: <3c50130f_1@news.tm.net.my> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 58 Date: Thu, 24 Jan 2002 17:18:11 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1011892691 24.13.238.93 (Thu, 24 Jan 2002 12:18:11 EST) NNTP-Posting-Date: Thu, 24 Jan 2002 12:18:11 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hub1.nntpserver.com!peer1-sjc1.usenetserver.com!usenetserver.com!newsfeeds-atl1.usenetserver.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13492 We've always used a small PAL outside the FPGA to assist in self-reconfiguration. Can you give more specifics as to why you think it won't configure? Check the program pin to make sure it isn't staying low, same with the init pin. Also check to make sure they aren't going low at the end of configuration. Alex Carreira wrote: > I am pretty sure the solution is to try this with a Virtex instead, but > first read XAPP 151 and all the others on the configuration architecture. > It may be possible on 4000 series but I don't think so (I am guessing that > reconfiguration causes functionality to stop during reprogramming of the > configuration memory, which is not the case for all scenarios with the > Virtex--of course I could be dead wrong about the 4000 series and if so > please excuse me). > > You can find out if it will work the the 4000 series for sure by digging up > an in depth ap. note on its configuration architecture (if one exists--I > think it does but my memory on the subject is weak right now). > > I have had discussions with numerous people about reconfiguring a Virtex > FPGA with its own resources. It would be particularly slick in RTR > (run-time-reconfigurable) applications. > > A :) > > Fong Chii Biao wrote in message > news:3c50130f_1@news.tm.net.my... > > Hi, i really need help bout this, as i worked for this for a week, no > result > > turns out. > > first, any one ever try reconfigure Xilinx FPGA using the chip itself? > (i'm > > using a single XC4010XL) > > > > the problem is.. when i connect the user I/O to the /program pin, the > > configuration can't even complete at power start up.. > > when i disconnect the I/O .. the configuration working pretty well.. whats > > the solution for this? > > > > anyone, anyone at all, who has any idea, ple reply to me, thnaks > > > > chiibiao > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: "Fong Chii Biao" Newsgroups: comp.arch.fpga References: <3c50130f_1@news.tm.net.my> Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Fri, 25 Jan 2002 01:45:01 +0800 Lines: 38 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 NNTP-Posting-Host: tsk-171-106.tm.net.my X-Original-NNTP-Posting-Host: tsk-171-106.tm.net.my Message-ID: <3c504767$1_1@news.tm.net.my> X-Trace: news.tm.net.my 1011894119 tsk-171-106.tm.net.my (25 Jan 2002 01:41:59 +0800) Organization: TMnet Malaysia Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!news1.tm.net.my Xref: chonsp.franklin.ch comp.arch.fpga:13499 i have no choice but a XC4000 series cause thats what we have in our Uni :) Im working on my undergraduate thesis actually. I read on the dynamic reconfiguration application note, it says that self reconfigure is possible, even the internal memory is gone once the reconfig was initiated, and all IO was put into tri state, its still reliable in doing so. but my problem is, it cant even configure on power up.. sad. well, thanks alot for sharing ur information, Alex. any information bout this on XC4000 series, let me know ya :) FCB Alex Carreira wrote in message news:a2pabv$1i02$1@nserve1.acs.ucalgary.ca... > I am pretty sure the solution is to try this with a Virtex instead, but > first read XAPP 151 and all the others on the configuration architecture. > It may be possible on 4000 series but I don't think so (I am guessing that > reconfiguration causes functionality to stop during reprogramming of the > configuration memory, which is not the case for all scenarios with the > Virtex--of course I could be dead wrong about the 4000 series and if so > please excuse me). > > You can find out if it will work the the 4000 series for sure by digging up > an in depth ap. note on its configuration architecture (if one exists--I > think it does but my memory on the subject is weak right now). > > I have had discussions with numerous people about reconfiguring a Virtex > FPGA with its own resources. It would be particularly slick in RTR > (run-time-reconfigurable) applications. > > A :) ###### From: "Fong Chii Biao" Newsgroups: comp.arch.fpga References: <3c50130f_1@news.tm.net.my> <3C50430A.1F418834@andraka.com> Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Fri, 25 Jan 2002 01:56:09 +0800 Lines: 43 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 NNTP-Posting-Host: tsk-171-106.tm.net.my X-Original-NNTP-Posting-Host: tsk-171-106.tm.net.my Message-ID: <3c504a03_1@news.tm.net.my> X-Trace: news.tm.net.my 1011894787 tsk-171-106.tm.net.my (25 Jan 2002 01:53:07 +0800) Organization: TMnet Malaysia Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!8712!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!news1.tm.net.my Xref: chonsp.franklin.ch comp.arch.fpga:13494 Well, i have two 512k PROM with each chip enable connected to Done pin of XC4010XL. Another edge trigger D-flip-flop for temparory register(coz all I/O go into tri state during reconfig) to select the PROM by Output Enable pin. and i use another user pin as an initiate pin to pull the program pin low. it can't configure when start up, if i had the user pin connected to this program pin. when i check on the program pin, it never goes high, its blinking actually.. the user pin is causing problem, but i have no idea why is it so. when i tied another not in use user pin to program pin, the power up configuration is working again. why is the user pin that i use in my design will cause such a problem? is this make any sense to you? thanks for giving ur opinion. :) Ray Andraka wrote in message news:3C50430A.1F418834@andraka.com... > We've always used a small PAL outside the FPGA to assist in > self-reconfiguration. Can you give more specifics as to why you think it won't > configure? Check the program pin to make sure it isn't staying low, same with > the init pin. Also check to make sure they aren't going low at the end of > configuration. > > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > ###### Message-ID: <3C505D92.3A099E8A@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA References: <3c50130f_1@news.tm.net.my> <3C50430A.1F418834@andraka.com> <3c504a03_1@news.tm.net.my> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 65 Date: Thu, 24 Jan 2002 19:11:23 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1011899483 24.13.238.93 (Thu, 24 Jan 2002 14:11:23 EST) NNTP-Posting-Date: Thu, 24 Jan 2002 14:11:23 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeed.gamma.ru!Gamma.RU!newsfeed.rt.ru!news-hub.siol.net!newsfeeds-atl2!newsfeeds-atl1.usenetserver.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13498 Sounds like you randomly selected LDC or one of the other dual use pins that goes low during configuration. If you did that, then as soon as the chip starts configuring, LDC goes low, pulling the program pin low, which restarts reconfiguration. While program is low, the LDC goes high so it releases program and the configuration starts until LDC goes low again. I kind of figured something like that was going on. Since you only have two configurations, this should work fine as long as you avoid pins that go low during configuration. It may be best to use HDC to get a solid high level during configuration. Fong Chii Biao wrote: > Well, i have two 512k PROM with each chip enable connected to Done pin of > XC4010XL. > Another edge trigger D-flip-flop for temparory register(coz all I/O go into > tri state during reconfig) > to select the PROM by Output Enable pin. > and i use another user pin as an initiate pin to pull the program pin low. > > it can't configure when start up, if i had the user pin connected to this > program pin. > when i check on the program pin, it never goes high, its blinking actually.. > the user pin is causing problem, > but i have no idea why is it so. > > when i tied another not in use user pin to program pin, the power up > configuration is working again. > why is the user pin that i use in my design will cause such a problem? > is this make any sense to you? > > thanks for giving ur opinion. :) > > Ray Andraka wrote in message > news:3C50430A.1F418834@andraka.com... > > We've always used a small PAL outside the FPGA to assist in > > self-reconfiguration. Can you give more specifics as to why you think it > won't > > configure? Check the program pin to make sure it isn't staying low, same > with > > the init pin. Also check to make sure they aren't going low at the end of > > configuration. > > > > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Thu, 24 Jan 2002 15:01:21 -0800 Organization: Xilinx Lines: 41 Message-ID: <3C509241.1AF3B12A@xilinx.com> References: <3c50130f_1@news.tm.net.my> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Alex Carreira Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!143799!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!pln-e!extra.newsguy.com!lotsanews.com!rockie.attcanada.net!172.31.25.103!prairie.attcanada.net!newsfeed.attcanada.net!12.127.17.144!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13539 See below: Alex Carreira wrote: > I am pretty sure the solution is to try this with a Virtex instead, but > first read XAPP 151 and all the others on the configuration architecture. > It may be possible on 4000 series No, XC4000 does not offer partial reconfiguration. > but I don't think so (I am guessing that > reconfiguration causes functionality to stop during reprogramming of the > configuration memory, yes > which is not the case for all scenarios with the > Virtex--of course I could be dead wrong about the 4000 series and if so > please excuse me). You are right on. Let me point out, however, that even good old XC3000, XC4000 and Spartan devices can initiate their own (complete) reconfiguration ( by pulling PROG Low) This may seem to violate some timing specs, but it works "by design". 100% ! > > > You can find out if it will work the the 4000 series for sure by digging up > an in depth ap. note on its configuration architecture (if one exists--I > think it does but my memory on the subject is weak right now). > > I have had discussions with numerous people about reconfiguring a Virtex > FPGA with its own resources. It would be particularly slick in RTR > (run-time-reconfigurable) applications. Reconfiguration can be initiated ( triggered) by any Xilinx device, partial reconfiguration only by Virtex (Spartan-II) devices. Peter Alfke, Xilinx Applications ###### From: "Fong Chii Biao" Newsgroups: comp.arch.fpga References: <3c50130f_1@news.tm.net.my> <3C50430A.1F418834@andraka.com> <3c504a03_1@news.tm.net.my> <3C505D92.3A099E8A@andraka.com> Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Fri, 25 Jan 2002 11:19:46 +0800 Lines: 49 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MIMEOLE: Produced By Microsoft MimeOLE V5.00.2615.200 NNTP-Posting-Host: tsk-10-34.tm.net.my X-Original-NNTP-Posting-Host: tsk-10-34.tm.net.my Message-ID: <3c50ce8a_1@news.tm.net.my> X-Trace: news.tm.net.my 1011928714 tsk-10-34.tm.net.my (25 Jan 2002 11:18:34 +0800) Organization: TMnet Malaysia Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!news1.tm.net.my Xref: chonsp.franklin.ch comp.arch.fpga:13547 oh, no, i didnt in fact, i was using non speacial function user I/O at first. its not working.. i tried using HDC, it can't work either.. and i even tried LDC, this is our of sense ya, and its not working (as expected).. one thing, i am using VHDL to design my logic, and in the contraints editor, i set the initiate user I/O to pull up.. so, it should be pulled high once the configuration completed, shouldnt it? i did this for double security, as i already set it high in my VHDL code.. until reconfigure is necessary. any idea, anything wrongs that you find? thanks again. :) Ray Andraka wrote in message news:3C505D92.3A099E8A@andraka.com... > Sounds like you randomly selected LDC or one of the other dual use pins that > goes low during configuration. If you did that, then as soon as the chip starts > configuring, LDC goes low, pulling the program pin low, which restarts > reconfiguration. While program is low, the LDC goes high so it releases program > and the configuration starts until LDC goes low again. I kind of figured > something like that was going on. Since you only have two configurations, this > should work fine as long as you avoid pins that go low during configuration. It > may be best to use HDC to get a solid high level during configuration. > > Fong Chii Biao wrote: > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > ###### From: "Fong Chii Biao" Newsgroups: comp.arch.fpga References: <3c50130f_1@news.tm.net.my> <3C509241.1AF3B12A@xilinx.com> Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Date: Fri, 25 Jan 2002 11:27:47 +0800 Lines: 57 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MIMEOLE: Produced By Microsoft MimeOLE V5.00.2615.200 NNTP-Posting-Host: tp-71-88.tm.net.my X-Original-NNTP-Posting-Host: tp-71-88.tm.net.my Message-ID: <3c50d0a7_2@news.tm.net.my> X-Trace: news.tm.net.my 1011929255 tp-71-88.tm.net.my (25 Jan 2002 11:27:35 +0800) Organization: TMnet Malaysia Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!news1.tm.net.my Xref: chonsp.franklin.ch comp.arch.fpga:13544 Greetings , Peter so, do you have any idea about my problems in start-up configuration? i tried to reconfigure (completely) XC4010 by initiating it using one of the I/O (non special function), when i connect it directly to PROG, the start-up can't work.. its working once i disconnect it Peter Alfke wrote in message news:3C509241.1AF3B12A@xilinx.com... > See below: > > Alex Carreira wrote: > > > I am pretty sure the solution is to try this with a Virtex instead, but > > first read XAPP 151 and all the others on the configuration architecture. > > It may be possible on 4000 series > > No, XC4000 does not offer partial reconfiguration. > > > but I don't think so (I am guessing that > > reconfiguration causes functionality to stop during reprogramming of the > > configuration memory, > > yes > > > which is not the case for all scenarios with the > > Virtex--of course I could be dead wrong about the 4000 series and if so > > please excuse me). > > You are right on. > Let me point out, however, that even good old XC3000, XC4000 and Spartan devices > can initiate their own (complete) reconfiguration ( by pulling PROG Low) This > may seem to violate some timing specs, but it works "by design". 100% ! > > > > > > > You can find out if it will work the the 4000 series for sure by digging up > > an in depth ap. note on its configuration architecture (if one exists--I > > think it does but my memory on the subject is weak right now). > > > > I have had discussions with numerous people about reconfiguring a Virtex > > FPGA with its own resources. It would be particularly slick in RTR > > (run-time-reconfigurable) applications. > > Reconfiguration can be initiated ( triggered) by any Xilinx device, > partial reconfiguration only by Virtex (Spartan-II) devices. > > Peter Alfke, Xilinx Applications > > ###### Message-ID: <3C50F0F5.7A29B501@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA References: <3c50130f_1@news.tm.net.my> <3C50430A.1F418834@andraka.com> <3c504a03_1@news.tm.net.my> <3C505D92.3A099E8A@andraka.com> <3c50ce8a_1@news.tm.net.my> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 76 Date: Fri, 25 Jan 2002 05:40:12 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@cox.net X-Trace: news2.east.cox.net 1011937212 24.13.238.93 (Fri, 25 Jan 2002 00:40:12 EST) NNTP-Posting-Date: Fri, 25 Jan 2002 00:40:12 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!23417!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hub1.nntpserver.com!peer1-sjc1.usenetserver.com!usenetserver.com!newsfeeds-atl1.usenetserver.com!cox.net!news2.east.cox.net.POSTED!53ab2750!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13542 You said the program pin was toggling. Any more detail? ONe of two things are happening: either it is getting pulled low as soon as configuration begins, or it is getting pulled low at the end of configuration. Make sure the pin you have it connected to isn't set up to output a low on power up (ie when global reset is active). Check the start-up sequence. The default,IIRC, lets go of the configuration use for the pins one CCLK before turning on the pin drivers. The weak internal pullup on the user I/O may not be enough to keep program from going low. You might consider an external pullup on the /program pin. Do yourself a favor, open that loop and watch the pin you are driving program with. If it goes low at all, then you you just have to figure out when it goes low which should then tell you why. If it stays high like that, put an external pull-down to load the output and see what it does then. Fong Chii Biao wrote: > oh, no, i didnt > in fact, i was using non speacial function user I/O at first. its not > working.. > i tried using HDC, it can't work either.. > and i even tried LDC, this is our of sense ya, and its not working (as > expected).. > > one thing, i am using VHDL to design my logic, > and in the contraints editor, i set the initiate user I/O to pull up.. > so, it should be pulled high once the configuration completed, shouldnt it? > i did this for double security, as i already set it high in my VHDL code.. > until reconfigure is necessary. > > any idea, anything wrongs that you find? > thanks again. :) > > Ray Andraka wrote in message > news:3C505D92.3A099E8A@andraka.com... > > Sounds like you randomly selected LDC or one of the other dual use pins > that > > goes low during configuration. If you did that, then as soon as the chip > starts > > configuring, LDC goes low, pulling the program pin low, which restarts > > reconfiguration. While program is low, the LDC goes high so it releases > program > > and the configuration starts until LDC goes low again. I kind of figured > > something like that was going on. Since you only have two configurations, > this > > should work fine as long as you avoid pins that go low during > configuration. It > > may be best to use HDC to get a solid high level during configuration. > > > > Fong Chii Biao wrote: > > > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: <03835ugjmt5aegvmst3ike0e00uca973p1@4ax.com> References: <3c50130f_1@news.tm.net.my> X-Newsreader: Forte Agent 1.8/32.553 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 58 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1011983402 ST000 216.103.85.188 (Fri, 25 Jan 2002 13:30:02 EST) NNTP-Posting-Date: Fri, 25 Jan 2002 13:30:02 EST X-UserInfo1: [[PA@S^EYJTSC\@[ARHDM^P@VZ\LPCXLLBWLOOAFQATJUZ]CDVW[AKK[J\]^HVKHG^EWZHBLO^[\NH_AZFWGN^\DHNVMX_DHHX[FSQKBOTS@@BP^]C@RHS_AGDDC[AJM_T[GZNRNZAY]GNCPBDYKOLK^_CZFWPGHZIXW@C[AFKBBQS@E@DAZ]VDFUNTQQ]FN Date: Fri, 25 Jan 2002 18:30:02 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newscon02.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13558 Good news, I know exactly what is going wrong. During config, normal I/O pins are tri-state. In other email you said you are not using a special programming pin like LDC or HDC to connect to your /program pin. Even if you did use HDC, (which then becomes a normal I/O after config, you would still have a problem. When config finishes, the I/O pins go active, and the output will switch to whatever your circuit in the FPGA has as its initial value. You need to do two things: 1) A pull up resistor on the net between the general purpose output pin and the /program pin. This is the net that you will be driving low to start reconfiguration. 2) You need to make sure that the output value as the chip changes from configuration to active is logic HIGH. (I am sure this is your basic problem). Here's how I have done this: Use an IOB flipflop to drive you control signal out and place an INIT=S attribute on it. This will make the initial state a logic HIGH. You also need to have the logic that feeds this flipflop also initially supply a logic HIGH to its D input, as the chip starts up, and continues high till you want to reconfigure. You can check that you have this right by putting a high speed scope on the signal, and trigger the scope (and view it as well) the DONE pin. If you dont have things right, you will see the DONE pin go high, then as your I/O goes active, if it switches from pulled up high, to LOW, then you need to fix your logic. It should stay high. This can work, I have done it (about 9 years ago :-) Philip. On Thu, 24 Jan 2002 22:00:02 +0800, "Fong Chii Biao" wrote: >Hi, i really need help bout this, as i worked for this for a week, no result >turns out. >first, any one ever try reconfigure Xilinx FPGA using the chip itself? (i'm >using a single XC4010XL) > >the problem is.. when i connect the user I/O to the /program pin, the >configuration can't even complete at power start up.. >when i disconnect the I/O .. the configuration working pretty well.. whats >the solution for this? > >anyone, anyone at all, who has any idea, ple reply to me, thnaks > >chiibiao > Philip Freidin Fliptronics