Message-ID: <3C4803EE.43C4B0AC@thmuli.com> Date: Fri, 18 Jan 2002 12:15:58 +0100 From: Juergen Buehler X-Mailer: Mozilla 4.76 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: DDR-Interface Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 14 NNTP-Posting-Host: proxy.thmulti.com X-Trace: 1011352567 read.news.fr.uu.net 14587 141.11.234.62 X-Complaints-To: abuse@fr.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!lnewspeer00.lnd.ops.eu.uu.net!lnewspost00.lnd.ops.eu.uu.net!emea.uu.net!read.news.fr.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13315 Hallo, does anybody has experience with an DDR-Interface in FPGA. We have to use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock frequency for video application. We tried it with the new Altera APEXII EP2A15, but run into lot of trouble. Has anybody run such an DDR interface with Altera, Xilinx or other manufactorers? Thanks in advance for your help Juergen ###### From: "Paul Baxter" Newsgroups: comp.arch.fpga References: <3C4803EE.43C4B0AC@thmuli.com> Subject: Re: DDR-Interface Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: <6eU18.41133$WQ1.6558498@news6-win.server.ntlworld.com> Date: Fri, 18 Jan 2002 12:10:28 -0000 NNTP-Posting-Host: 62.252.188.91 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1011355650 62.252.188.91 (Fri, 18 Jan 2002 12:07:30 GMT) NNTP-Posting-Date: Fri, 18 Jan 2002 12:07:30 GMT Organization: ntlworld News Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!proxad.net!news-hub.cableinet.net!blueyonder!newspeer.clara.net!news.clara.net!peernews!peer.cwci.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13327 Doesn't altera provide a free DDR core on their web site? You could also look at the cores at www.opencores.org though I don't think I saw a DDR one. Paul "Juergen Buehler" wrote in message news:3C4803EE.43C4B0AC@thmuli.com... > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > Juergen > ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: DDR-Interface Date: Fri, 18 Jan 2002 07:55:20 -0800 Organization: Xilinx Lines: 42 Message-ID: <3C484568.F90DFBF1@xilinx.com> References: <3C4803EE.43C4B0AC@thmuli.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13319 Juergen, We have many successful designs that I have seen from our customers using HSTL, SSTL, and LVDCI at 133 MHz DDR in Virtex family devices. In Virtex II, the IOB has the dedicated DDR FF which is optimized for inputs and outputs. The DCM removes all clock skew, and provides duty cycle corrected clocks (better timing margins). Signal integrity on your board, avoidance of cross talk induced delay variations in your bus, are all issues that will break any design (Altera or Xilinx). Oh, and bypassing must be excellent, or else you give up even more in having ground bounce that not only ruins the noise margin, but adds jitter. Look at the app notes: http://www.support.xilinx.com/xapp/xapp253.pdf http://www.support.xilinx.com/xapp/xapp214.pdf http://www.support.xilinx.com/xapp/xapp200.pdf .... and more. Austin Juergen Buehler wrote: > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > Juergen ###### Message-ID: <3C484936.8EF5F980@thmuli.com> Date: Fri, 18 Jan 2002 17:11:34 +0100 From: Juergen Buehler X-Mailer: Mozilla 4.76 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: DDR-Interface References: <3C4803EE.43C4B0AC@thmuli.com> <6eU18.41133$WQ1.6558498@news6-win.server.ntlworld.com> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 44 NNTP-Posting-Host: proxy.thmulti.com X-Trace: 1011370295 read.news.fr.uu.net 14583 141.11.234.62 X-Complaints-To: abuse@fr.uu.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!proxad.net!news-hub.cableinet.net!blueyonder!btnet-peer!btnet!lnewspeer01.lnd.ops.eu.uu.net!lnewspost00.lnd.ops.eu.uu.net!emea.uu.net!read.news.fr.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13313 Hi Paul, The free DDR core is only for a 20k Device. The problem when using the APEXII is that there is a difference between the documentation (marketing stuff !!!) and the technique. A lot of things which are described in the documentation are not functional as they are described. For example the plls, ddr-lpms and the STTL2 output standart. At opencores there are no DDR-RAM Interfaces described. The problem is not the DDR controller, the problem is the realisation of the hardware interface in the FPGA. There we miss a lot of information about a successful implementation Jürgen Paul Baxter wrote: > Doesn't altera provide a free DDR core on their web site? > > You could also look at the cores at www.opencores.org though I don't think I > saw a DDR one. > > Paul > > "Juergen Buehler" wrote in message > news:3C4803EE.43C4B0AC@thmuli.com... > > Hallo, > > > > does anybody has experience with an DDR-Interface in FPGA. We have to > > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > > frequency for video application. We tried it with the new Altera APEXII > > EP2A15, but run into lot of trouble. > > Has anybody run such an DDR interface with Altera, Xilinx or other > > manufactorers? > > > > Thanks in advance for your help > > > > Juergen > > ###### From: Roberta Crescentini Newsgroups: comp.arch.fpga Subject: Re: DDR-Interface Date: Fri, 18 Jan 2002 15:03:55 +0100 Organization: Alcatel Lines: 22 Message-ID: <3C482B4B.A197633@alcatel.it> References: <3C4803EE.43C4B0AC@thmuli.com> NNTP-Posting-Host: inter5.alcanet.it Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: pluto.news.dsi.unimi.it 1011362995 12097 194.243.74.5 (18 Jan 2002 14:09:55 GMT) X-Complaints-To: news@news.dsi.unimi.it NNTP-Posting-Date: 18 Jan 2002 14:09:55 GMT X-Mailer: Mozilla 4.78 [en] (X11; U; SunOS 5.8 sun4u) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!asynchrone!fr.usenet-edu.net!usenet-edu.net!newsfeeds.belnet.be!news.belnet.be!newsmi-eu.news.garr.it!NewsITBone-GARR!newsserver.cilea.it!news.unimi.it!news.dsi.unimi.it!ipl003!nobody Xref: chonsp.franklin.ch comp.arch.fpga:13363 Hi could you explain which kind of problems you have met? Robi Juergen Buehler wrote: > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > Juergen ###### From: ed.moore@snellwilcox.com (Edward Moore) Newsgroups: comp.arch.fpga Subject: Re: DDR-Interface Date: 21 Jan 2002 08:22:20 -0800 Organization: http://groups.google.com/ Lines: 48 Message-ID: <4bf8cea0.0201210822.13f04640@posting.google.com> References: <3C4803EE.43C4B0AC@thmuli.com> <3C484568.F90DFBF1@xilinx.com> NNTP-Posting-Host: 195.173.15.26 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1011630140 12850 127.0.0.1 (21 Jan 2002 16:22:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 21 Jan 2002 16:22:20 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.abs.net!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13419 Can anybody help me understand how the DDR interfaces in these application notes work ? I can't figure out how read data can be clocked into the virtex using the same clock that feeds the ram. My understanding of DDR SDRAMS is that read data can arrive up to 0.75 ns after the clock, and may be valid for no more than half the clock period minus 0.75 ns. At 133 MHz, that gives you a 2.26 ns window to latch the data, and requires a delayed clock which is positioned to account for setup time, clock jitter and pcb trace delays. But the application notes don't use a delayed clock. And even if they did, at 133 MHz I can't see how you could meet the setup time requirement of the IOB input registers listed in the virtex datasheets. So, since there are succesfull DDR SDRAM designs out there, where am I going wrong ? -- Ed Austin Lesea wrote > > We have many successful designs that I have seen from our customers using > HSTL, SSTL, and LVDCI at 133 MHz DDR in Virtex family devices. In Virtex > II, the IOB has the dedicated DDR FF which is optimized for inputs and > outputs. The DCM removes all clock skew, and provides duty cycle corrected > clocks (better timing margins). > > Signal integrity on your board, avoidance of cross talk induced delay > variations in your bus, are all issues that will break any design (Altera > or Xilinx). Oh, and bypassing must be excellent, or else you give up even > more in having ground bounce that not only ruins the noise margin, but adds > jitter. > > Look at the app notes: > > http://www.support.xilinx.com/xapp/xapp253.pdf > > http://www.support.xilinx.com/xapp/xapp214.pdf > > http://www.support.xilinx.com/xapp/xapp200.pdf > > .... and more. > > Austin >