Message-ID: <3c46a0b2@pfaff.ethz.ch> From: Christian Plessl Subject: Virtex2 ICAP Newsgroups: comp.arch.fpga Date: Thu, 17 Jan 2002 10:58:59 +0100 Lines: 17 User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit NNTP-Posting-Host: tec-pc-cp.ethz.ch X-Trace: 17 Jan 2002 11:00:18 +0100, tec-pc-cp.ethz.ch Organization: Swiss Federal Institute of Technology (ETHZ) Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:13362 Hi Incidentally, I just stumbled over the Virtex2 ICAP (Internal configuration access port) primitive. Just looking at the name of the component this sounds very interessting. Is it possible to access/modify the Virtex2 configuration from a circuit within the FPGA itself using this component? Unfortunately I could not find any documentation ICAP on the Xilinx webpage. Does anybody know, what this component is good for? Is there any documentation on this? Thanks for any hints. Christian ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Virtex2 ICAP Date: Thu, 17 Jan 2002 07:38:01 -0800 Organization: Xilinx Lines: 41 Message-ID: <3C46EFD9.A88F5706@xilinx.com> References: <3c46a0b2@pfaff.ethz.ch> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed.cwix.com!prairie.attcanada.net!newsfeed.attcanada.net!12.127.17.144!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13321 Christian, Yes, that is what the ICAP primitive is for. We added it to support the internal reconfiguration, and self modifying efforts of many groups. With the addition of the floorplanner in 4.1i, one can now assign areas to functions (necessary for using ICAP so you don't step on yourself). Look for more applications notes using this capability. If you are interested in using it now, contact your FAE for the necessary technical support, or just give it a try (it has been verified to work in the silicon). Basically it is quite simple, it is a 2:1 multiplexer that allows access to all external configuration pins inside the logic plane. So, basically, anything you could do outside the part, you can now do inside the part. The posting on using the -r bitstream option to generate differences between bitstreams as re-configurable snippets would be one way to use this: configure once with the first pattern, load the changes into a block RAM (might be part of the first pattern), and then use the BRAM and the ICAP to re-program the change at the point it is needed. Austin Christian Plessl wrote: > Hi > > Incidentally, I just stumbled over the Virtex2 ICAP (Internal configuration > access port) primitive. Just looking at the name of the component this > sounds very interessting. Is it possible to access/modify the Virtex2 > configuration from a circuit within the FPGA itself using this component? > > Unfortunately I could not find any documentation ICAP on the Xilinx webpage. > > Does anybody know, what this component is good for? Is there any > documentation on this? > > Thanks for any hints. > > Christian ###### Message-ID: <3c470261@pfaff.ethz.ch> From: Christian Plessl Subject: Re: Virtex2 ICAP Newsgroups: comp.arch.fpga Date: Thu, 17 Jan 2002 17:55:46 +0100 References: <3c46a0b2@pfaff.ethz.ch> <3C46EFD9.A88F5706@xilinx.com> Lines: 16 User-Agent: KNode/0.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit NNTP-Posting-Host: tec-pc-cp.ethz.ch X-Trace: 17 Jan 2002 17:57:05 +0100, tec-pc-cp.ethz.ch Organization: Swiss Federal Institute of Technology (ETHZ) Path: chonsp.franklin.ch!pfaff.ethz.ch Xref: chonsp.franklin.ch comp.arch.fpga:13359 > Basically it is quite simple, it is a 2:1 multiplexer that allows access > to all external configuration pins inside the logic plane. So, basically, > anything you could do outside the part, you can now do inside the part. > > The posting on using the -r bitstream option to generate differences > between bitstreams as > re-configurable snippets would be one way to use this: configure once > with the first pattern, load the changes into a block RAM (might be part > of the first pattern), and then use the BRAM and the ICAP to re-program > the change at the point it is needed. Wow. Im looking forward to a JBits version that supports Virtex2. This will make this new ICAP feature really usefull.. Best regards, Chris