From: Matthias Weber Newsgroups: comp.arch.fpga Subject: latch vs. register Date: Tue, 08 Jan 2002 11:55:29 GMT Organization: 1&1 Internet AG Lines: 10 Message-ID: <1103_1010490929@news.online.de> NNTP-Posting-Host: p508442e1.dip0.t-ipconnect.de Content-Type: text/plain; charset="windows-1252" X-Trace: news.online.de 1010490969 11013 80.132.66.225 (8 Jan 2002 11:56:09 GMT) X-Complaints-To: abuse@online.de NNTP-Posting-Date: 8 Jan 2002 11:56:09 GMT User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98) Opera 6.0 [de] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!blackbush.xlink.net!blackbush.de.kpnqwest.net!rz.uni-karlsruhe.de!schlund.de!news.online.de!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12983 hi, do i understand right that latches consists of simple flipflops without beeing clocked so that the circuit storesimmediately every change of signal. is the difference between latches and registers that latter are clocked (constructed by D-, RS- or JK-FlipFlops)? thanks for information, matthias weber ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: Tue, 08 Jan 2002 09:25:27 -0800 Organization: Xilinx Lines: 29 Message-ID: <3C3B2B86.EE738C4F@xilinx.com> References: <1103_1010490929@news.online.de> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Matthias Weber Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!DirecTV-DSL!enews.sgi.com!nntp.wetware.com!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12967 Tutorial: A flip-flop consists of two latches, a master and a slave. A latch accepts data when the Latch Enable is active, and stores data when LE is not active. With LE active, the latch is transparent, its output follows the input. A flip-flop combines two latches with opposite LE polarities, such that the master latch accepts incoming data when the clock is Low, and the slave latch copies the master when the clock is High ( This is thus a rising-clock-edge edge-triggered flip-flop. The opposite clock polarity is also possible). A flip-flop is never transparent, its output can thus be fed back to its input without creating a race condition. That's why we need and love flip-flops. In FPGAs, all flip-flops are implemented as D-flip-flops. Any different type ( R,S,T) is constructed by additional logic in front of the D. Peter Alfke ========================== Matthias Weber wrote: > hi, > > do i understand right that latches consists of simple flipflops without beeing clocked so that the circuit storesimmediately every change of signal. > is the difference between latches and registers that latter are clocked (constructed by D-, RS- or JK-FlipFlops)? > > thanks for information, > > matthias weber ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: Re: latch vs. register References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 08 Jan 2002 12:22:35 -0800 Message-ID: Lines: 24 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 8 Jan 2002 12:33:20 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:13012 Peter Alfke writes: > Tutorial: > A flip-flop consists of two latches, a master and a slave. > > A latch accepts data when the Latch Enable is active, and stores data > when LE is not active. With LE active, the latch is transparent, its > output follows the input. > > A flip-flop combines two latches with opposite LE polarities, such > that the master latch accepts incoming data when the clock is Low, and > the slave latch copies the master when the clock is High ( This is > thus a rising-clock-edge edge-triggered flip-flop. The opposite clock > polarity is also possible). I think you're probably more of an expert on digital logic than I am, but aren't there several other edge-triggered flip-flop designs that do NOT operate in a master-slave fashion? It seems to me that the plain old 7474 D flip-flop is edge-triggered but not master-slave. The output is valid after a short delay from the active edge, whereas on a master-slave the output would not be valid until after the opposite clock edge. Or perhaps I'm completely clueless. It wouldn't be the first time. It's been a LONG time since I studied flip-flops in detail. ###### Message-ID: <3C3B5B70.AC2A89C8@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: latch vs. register References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 29 Date: Tue, 08 Jan 2002 20:49:52 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@tek.com X-Trace: news-west.eli.net 1010522992 192.65.17.17 (Tue, 08 Jan 2002 13:49:52 MST) NNTP-Posting-Date: Tue, 08 Jan 2002 13:49:52 MST Organization: Tektronix NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!DirecTV-DSL!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13038 Eric Smith wrote: > It seems to me that the plain > old 7474 D flip-flop is edge-triggered but not master-slave. The output > is valid after a short delay from the active edge, whereas on a > master-slave the output would not be valid until after the opposite > clock edge. This is one of the fun parts of looking into other people's hardware. I think it was an old TI databook that I really got to understand how the master-slave thing works - I think it was the 7474. Using your terminology above, before the active edge (when the clock is low) the input latch (the master? Thanks, Peter) is transparent allowing the incoming data to show up at the input of the output latch (the slave) but blocked. When the clock polarity changes, the output latch becomes transparent allowing the data from the input latch to show up on the output; in the mean time the input latch no longer tracks the input data because it's no longer transparent. So after the active edge, the output is looking at the data "in the middle" through a transparent output latch. When the opposite edge comes by the transparent output latch turns non-transparent (opaque?) and the data is held for the second half of the clock cycle as the input latch begins once again to look at the input data. Ahhhh, for the days when the data books gave all the gate level description you needed :-) - John ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: Tue, 08 Jan 2002 15:00:28 -0800 Organization: Xilinx Lines: 39 Message-ID: <3C3B7A0B.A341461B@xilinx.com> References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> <3C3B5B70.AC2A89C8@mail.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: John_H Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!93002!news.imp.ch!fu-berlin.de!spring.edu.tw!feeder.seed.net.tw!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12956 John, thanks, you just saved me a long explanation. It is exactly as you described it . I date back to the introduction of the 7474 and the equivalent Fairchild dual flip-flops. Nowadays we shelter the reader from this kind of nitty-gritty. Most users appreciate that, some don't... Peter Alfke ==================================== John_H wrote: > Eric Smith wrote: > > > It seems to me that the plain > > old 7474 D flip-flop is edge-triggered but not master-slave. The output > > is valid after a short delay from the active edge, whereas on a > > master-slave the output would not be valid until after the opposite > > clock edge. > > This is one of the fun parts of looking into other people's hardware. I > think it was an old TI databook that I really got to understand how the > master-slave thing works - I think it was the 7474. Using your terminology > above, before the active edge (when the clock is low) the input latch (the > master? Thanks, Peter) is transparent allowing the incoming data to show up > at the input of the output latch (the slave) but blocked. When the clock > polarity changes, the output latch becomes transparent allowing the data > from the input latch to show up on the output; in the mean time the input > latch no longer tracks the input data because it's no longer transparent. > So after the active edge, the output is looking at the data "in the middle" > through a transparent output latch. > > When the opposite edge comes by the transparent output latch turns > non-transparent (opaque?) and the data is held for the second half of the > clock cycle as the input latch begins once again to look at the input data. > > Ahhhh, for the days when the data books gave all the gate level description > you needed :-) > > - John ###### Message-ID: <3C3B88B1.FB72B874@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: latch vs. register References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> <3C3B5B70.AC2A89C8@mail.com> <3C3B7A0B.A341461B@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 20 Date: Wed, 09 Jan 2002 00:02:57 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1010534580 62.254.210.251 (Wed, 09 Jan 2002 00:03:00 GMT) NNTP-Posting-Date: Wed, 09 Jan 2002 00:03:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!13756!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!btnet-peer1!btnet-feed3!btnet-peer0!btnet-peer!btnet!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12968 Peter Alfke wrote: > John, thanks, you just saved me a long explanation. It is exactly as you > described it . > I date back to the introduction of the 7474 and the equivalent Fairchild dual > flip-flops. > Nowadays we shelter the reader from this kind of nitty-gritty. > Most users appreciate that, some don't... > Peter Alfke > ==================================== > Wasn't it true that the large flip-flop speed up obtained by Fairchild's `F'ast TTL series was down to using a long-tailed pair (aka diff amp) at the core of an F74 instead of a master-slave latch ? ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: Tue, 08 Jan 2002 16:44:59 -0800 Organization: Xilinx Lines: 24 Message-ID: <3C3B928B.B46A1426@xilinx.com> References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> <3C3B5B70.AC2A89C8@mail.com> <3C3B7A0B.A341461B@xilinx.com> <3C3B88B1.FB72B874@algor.co.uk> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Rick Filipkiewicz Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!204.52.135.42!nntp1.hal-pc.org!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12955 Rick Filipkiewicz wrote: > Wasn't it true that the large flip-flop speed up obtained by Fairchild's `F'ast > TTL series was down to using a long-tailed pair (aka diff amp) at the core of an > F74 instead of a master-slave latch ? Not to my knowledge, and I was responsible for Digital Applications there from 1969 to 1976. There were some strange "ones-catching" flip-flops around, but, after a while, everybody ( including today's CMOS ) settled on the dual-latch master-slave edge-triggered version. I tried in vain to kill the word "hold-time" and substitute it with "min. set-up time", but TI, who needed to defend their poorly designed flip-flop sporting positive hold time, was too dominant. Those were the days of cultural battles, Californians against Texans. Californians counting 0,1,2,3 but Texans counting 1,2,3,4. We felt so superior, but were beaten by the almighty 7400 series. Nostalgia... Peter Alfke ###### From: Jonathan Bromley Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: Wed, 9 Jan 2002 09:33:50 +0000 Organization: Doulos Ltd. Message-ID: References: <1103_1010490929@news.online.de> <3C3B2B86.EE738C4F@xilinx.com> <3C3B5B70.AC2A89C8@mail.com> Reply-To: Jonathan Bromley NNTP-Posting-Host: no-dns-yet.demon.co.uk X-NNTP-Posting-Host: no-dns-yet.demon.co.uk:62.49.185.60 X-Trace: news.demon.co.uk 1010569007 nnrp-12:9076 NO-IDENT no-dns-yet.demon.co.uk:62.49.185.60 X-Complaints-To: abuse@demon.net MIME-Version: 1.0 X-Newsreader: Turnpike Integrated Version 5.01 M Lines: 57 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!dispose.news.demon.net!news.demon.co.uk!demon!no-dns-yet.demon.co.uk!doulos.co.uk!Jonathan.Bromley Xref: chonsp.franklin.ch comp.arch.fpga:12993 In article <3C3B5B70.AC2A89C8@mail.com>, John_H writes [snip master/slave FF description] > >Ahhhh, for the days when the data books gave all the gate level description >you needed :-) DANGER, maudlin nostalgic post follows: When I was very, very much younger than I am now, I remember being mightily troubled by how a divide-by-2 (toggle FF) worked. I just couldn't see how the thing could cope with an output that changed because of the input, which was in fact the changed output..... After much head-scratching and looking at books that I really didn't understand, with pictures of dual-triode Eccles-Jordan relays (that's a vacuum-tube R-S latch to you young'uns), I came up with the master-slave idea. Off to the garden shed. Ten BC108 transistors with their cans shoved in to ten little holes in a piece of wood, legs in the air. 1k resistors for collector pull-ups. 10k resistors for base current limiting. Much soldering and cursing, far and away the most difficult circuit I had ever built. One more transistor to buffer the output on to a flashlight bulb. Hardwire the thing as a toggle FF because I didn't understand any kind of sequential logic other than a counter. Connect the clock input to a bit of wire (no money to buy real switches). Spend an afternoon utterly mystified by the circuit's almost random behaviour when clocked by flicking this wire on and off the battery terminal. That way I learned some hard lessons about fan-in and switch bounce. But the right answers, learnt "properly" a few years later, made much more sense because of the childhood experience. And "RTL" doesn't just mean Register Transfer Level for me! -- Jonathan Bromley DOULOS Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 1425 471573 Web: http://www.doulos.com ********************************** ** Developing design know-how ** ********************************** This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. ###### From: jmrice@ntlworld.com (Martin Rice) Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: 11 Jan 2002 12:55:14 -0800 Organization: http://groups.google.com/ Lines: 48 Message-ID: References: <1103_1010490929@news.online.de> NNTP-Posting-Host: 62.253.64.6 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1010782515 27758 127.0.0.1 (11 Jan 2002 20:55:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 11 Jan 2002 20:55:15 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13171 Matthias Weber wrote in message news:<1103_1010490929@news.online.de>... > hi, > > do i understand right that latches consists of simple flipflops without beeing clocked so that the circuit storesimmediately every change of signal. > is the difference between latches and registers that latter are clocked (constructed by D-, RS- or JK-FlipFlops)? > > thanks for information, > > matthias weber Unfortunately, the terms latch, register and flip-flop do not have universally accepted meanings, that are adhered to. You can have memory elemants with no clock input, you can have memory elements that do have a clock, elements that have an enable, and you can have collections of memory elements. Take two, two-input NOR gates and join the output of one to the input of the other, in a cross-coupled sort of circuit. This is a bistable circuit that can be changed from one state to the other by asserting the right signals on the two spare inputs. It is normally referred to as an SR latch, but also as an RS latch, an RS flip-flop, an SR bistable, etc. Perhaps this is the circuit you have in mind when you mention 'simple flipflops'. If you add a third input (a clock) and some circuitry that means that the output can only change in response to a change of state on the clock, then you get an edge-triggered device. Most people call this a flip-flop, although you do find references to edge-triggered latches. If, instead of the clock, you add a third input (an enable) and some (different) circuitry that means that the output follows the input when the enable is in one state, but stores the latest input when the enable is in its other state, then you get a level-triggered device. Most people call this a latch, and to emphasise the way the output follows the input when the enable is active, qualify the latch as transparent. If you string some flip-flops (edge-triggered) together, with all the clocks combined, you get what most people call a register. On the other hand, the term registered when describing a digital output, probably just means that you need to apply a clock signal to get the output to change, and may apply to just one output. So, be careful what you read into these terms. Make sure you know whether the device is level triggered or edge triggered, and what polarity of level or edge makes the device output change. Martin Rice ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: latch vs. register Date: Fri, 11 Jan 2002 15:30:40 -0800 Organization: Xilinx Lines: 19 Message-ID: <3C3F759F.7397D0BA@xilinx.com> References: <1103_1010490929@news.online.de> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Martin Rice Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!381948!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!pln-e!extra.newsguy.com!lotsanews.com!rockie.attcanada.net!172.31.25.103!prairie.attcanada.net!newsfeed.attcanada.net!12.127.17.144!attbt1!attbt2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:13143 Martin Rice wrote: > > Unfortunately, the terms latch, register and flip-flop do not have > universally accepted meanings, that are adhered to. Let me suggest that in this newsgroup a latch is a bistable storage element that has only one rank, i.e. is transparent ( input directly affecting the output) while enabled. A flip-flop is more complex, dual-rank, and is thus never transparent, and the data input never affects the output directly. Usually, a register is a collection of flip-flops with a common clock. If we adhere to these definitions, we are in synch with most of the industry. Peter Alfke