From: doug@frombob.to (Doug) Newsgroups: comp.arch.fpga Subject: Spartan-IIE interfacing issues Date: 3 Jan 2002 17:07:06 -0800 Organization: http://groups.google.com/ Lines: 21 Message-ID: NNTP-Posting-Host: 64.167.13.185 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1010106427 3857 127.0.0.1 (4 Jan 2002 01:07:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 4 Jan 2002 01:07:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!29236!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12917 I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA, which has 3.3V I/O. I know I could use something like a 74LVX3245, but apparently it can be safely done with resistors as well. In the appnote "Spartan-IIE Family: Frequently Asked Questions" (Xilinx document #FAQ100), it says: "The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V I/Os when an external pull-up resistor is used." ...and that's all the info I've been able to find so far. Before I proceed, I would like to see more specific recommendations (preferably from Xilinx!) about how best to do this. Is anyone out there aware of any other documents detailing Xilinx' recommended method, specifically for the Spartan-IIE family? Thanks in advance, Doug Jones ###### From: Kevin Brace Newsgroups: comp.arch.fpga Subject: Re: Spartan-IIE interfacing issues Date: Fri, 04 Jan 2002 04:55:01 -0600 Organization: None Lines: 6 Sender: kevinbraceusenet@hotmail.com Message-ID: References: NNTP-Posting-Host: 32-pool1.ras10.ilchi.tii-dial.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.mailgate.org 1010141284 1343 206.250.224.32 (4 Jan 2002 10:48:04 GMT) X-Complaints-To: abuse@mailgate.org NNTP-Posting-Date: Fri, 4 Jan 2002 10:48:04 +0000 (UTC) X-Mailer: Mozilla 4.79 [en] (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsreader.mailgate.org!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12907 Why not use an older Spartan-II instead? It supports 5V tolerant I/Os. Kevin Brace (don't respond to me directly, respond within the newsgroup) ###### Message-ID: <3C359B6B.1494B9AD@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Spartan-IIE interfacing issues References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 46 Date: Fri, 04 Jan 2002 12:09:15 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1010146164 62.254.210.251 (Fri, 04 Jan 2002 12:09:24 GMT) NNTP-Posting-Date: Fri, 04 Jan 2002 12:09:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!proxad.net!news-hub.cableinet.net!blueyonder!btnet-peer!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12896 Doug wrote: > I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA, > which has 3.3V I/O. > > I know I could use something like a 74LVX3245, but apparently it can > be safely done with resistors as well. In the appnote "Spartan-IIE > Family: Frequently Asked Questions" (Xilinx document #FAQ100), it > says: > > "The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V > I/Os when an external pull-up resistor is used." > > ...and that's all the info I've been able to find so far. > and it is, in fact, slightly misleading. There are 2 parts to getting 5V compatibility with 3V3 devices: o Output: The devices receiving signals from the FPGA have to have a Vih(min) <= the FPGA's Voh(min). For most modern TTL-compatible devices this is o.k. but you'll have to be careful if there are any true CMOS 5V parts. This is sort of where the ``pull-up'' comes in but there are better/cleaner ways of doing this. o Input: Here the problem is that no Virtex class devices except for the original Virtex familiy are 5V tolerant. There are 2 approaches you can take to this: - Xilinx state that a 100R between the 5V source and the FPGA pin is sufficient. - Use QuickSwitch type buffers between the 5V domain and the FPGA. For something like 5V PCI the QS approach is much less electrically intrusive although it costs more in PCB real estate. These magic devices are really a bunch of FET switches whose impedance is about 5-10R (with a max Tpd of 250ps) until the driving side gets to about 0V7 below VCC. From then on the impedance increases very steeply. For the 5V QS parts the trick is/was to power them from a supply in the 3V3-3V9 range. There are now 3V3 versions of these parts but BE WARNED: They come in 2 flavours - clamping and non-clamping. ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Spartan-IIE interfacing issues Date: Fri, 04 Jan 2002 07:37:00 -0800 Organization: Xilinx Lines: 68 Message-ID: <3C35CC1C.FE50DBF1@xilinx.com> References: NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!enews.sgi.com!nntp.wetware.com!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12897 Doug, The recommendation is to use a 100 ohm resistor in series with the 5V driver output to the 3.3V powered IO bank on the Spartan IIE. This way, if the driver can pull all the way to 5V, the forward clamping of the input diode to Vcco limits the voltage at the input pin to Vcco+0.5V (the diodes are intrinsic to the pmos output fets which are present in the IOB, so they are ~ 0.5V drop). If you first simulate the connection in IBIS, you may find that the 5V outputs are classic TTL (not CMOS), and can not pull above Voh(max) of a voltage that does not exceed Vcco+0.5V (i.e. less than 3.8 V). If this is the case, no resistor is needed to limit the input current into the Spartan IIE. Many TTL parts that are CMOS used nmos pull-up transistors in the output stage, so the Voh(max) was always ~ 0.7 V below the Vcc of 5V, or lower. If placing a 100 ohm resistor in series slows down the signal too much, one can also simulate it in IBIS with a resistor to ground. A 75 ohm resistor, for example, will load down the driver without slowing down the signal, resulting in a lower Voh(max). Remember to simulate the fast/strong corner in IBIS, as that is the cold/strong transistor/high vcc case that will be the worst case. Also then simulate the slow/weak corner to be sure the voltages are still within spec for the input to see 0's and 1's. Innoveda's Hyperlynx has a free download version that can be used for these kinds of what if's. The demo version can not import new IBIS files, and has other restrictions, but I highly recommend trying it out. Once you get using it, you will be hooked, and just buy the real version. The cost will save board respins due to bad SI, so you will end up saving money the first time you use it. For those of you with the Cadence, or Mentor IBIS simulator tools, those are also excellent, and I highly recommend them. Avant! Hspice also imports IBIS as a subcircuit model, so it can be used for those who like spice. Austin Lesea ICDES Xilinx Doug wrote: > I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA, > which has 3.3V I/O. > > I know I could use something like a 74LVX3245, but apparently it can > be safely done with resistors as well. In the appnote "Spartan-IIE > Family: Frequently Asked Questions" (Xilinx document #FAQ100), it > says: > > "The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V > I/Os when an external pull-up resistor is used." > > ...and that's all the info I've been able to find so far. > > Before I proceed, I would like to see more specific recommendations > (preferably from Xilinx!) about how best to do this. Is anyone out > there aware of any other documents detailing Xilinx' recommended > method, specifically for the Spartan-IIE family? > > Thanks in advance, > > Doug Jones