From: "Frank Papenfuss" Newsgroups: comp.arch.fpga Subject: CE on XILINX FFs and Metastability Date: Fri, 21 Dec 2001 10:49:15 +0100 Lines: 33 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 NNTP-Posting-Host: 139.30.201.23 X-Original-NNTP-Posting-Host: 139.30.201.23 Message-ID: <3c2305a6$1@news.uni-rostock.de> X-Trace: 21 Dec 2001 10:49:26 +0100, 139.30.201.23 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!21963618!news.imp.ch!psinet-eu-nl!unlisys!news.snafu.de!zrz.TU-Berlin.DE!news.uni-rostock.de Xref: chonsp.franklin.ch comp.arch.fpga:12614 Dear FPGA comunity, I have a design that must cope with asynchronous input signals. Basically I have a WE pulse that gates a data vector into the chip. The WE signal is sampled by two FFs to enshure proper pulse detection. One FF is clocked by the positive edge of the system clock and one by the negative edge (I do not want to go into too much details about why I must do this). The FFs that sample the pulse connect to the CE (clock enable) of the following FF to prevent the metastable state from probagating actually into the design. Since I have only simulated this so far I cannot say if it will really work inside the chip (which will be a XILINX FPGA). My question is: Has anyone experience with using CE as a mean to prevent a metastable state from probagating further. Tool Setup: ----------- Simulation & Synthesis: SYNOPSIS Ver 1999.10 Target Technology Mapping: XILINX Design Manager V3.3.08i Target Part: XILINX VirtexE XCV300E-8-PQ240 I would also be greatful if you could point me to some electronically available article, technote or appnote about this topic, if available. Thanks in advance, FRANK ###### Message-ID: <3C230E88.7DB38FF@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: CE on XILINX FFs and Metastability References: <3c2305a6$1@news.uni-rostock.de> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 41 Date: Fri, 21 Dec 2001 10:27:20 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1008930443 62.254.210.251 (Fri, 21 Dec 2001 10:27:23 GMT) NNTP-Posting-Date: Fri, 21 Dec 2001 10:27:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!grolier!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12570 Frank Papenfuss wrote: > Dear FPGA comunity, > > I have a design that must cope with asynchronous input > signals. Basically I have a WE pulse that gates a data > vector into the chip. The WE signal is sampled by two > FFs to enshure proper pulse detection. One FF is clocked > by the positive edge of the system clock and > one by the negative edge (I do not want to go > into too much details about why I must do this). The FFs > that sample the pulse connect to the CE (clock enable) > of the following FF to prevent the metastable state from > probagating actually into the design. Since I have only > simulated this so far I cannot say if it will really work > inside the chip (which will be a XILINX FPGA). > > My question is: Has anyone experience with using CE as > a mean to prevent a metastable state from probagating > further. > Frank, It is an unfortunate fact that if an signal from a source async to a clock is sampled on that clock then there is always a chance that a metastable state could propagate arbitrarily far into your system. Metastability is a statistical thing and so all you can do is reduce the probability of its affecting your system to some very small number (or the MTBF >> time between you changing jobs). IIRC there is even a paper somewhere that proves metstability cannot be eliminated by purely digital means. BTW: If anyone has that original reference I'd be grateful - I read it in ~1984 and have long since lost it. ###### Reply-To: "none" From: "none" Newsgroups: comp.arch.fpga References: <3c2305a6$1@news.uni-rostock.de> Subject: Re: CE on XILINX FFs and Metastability Lines: 11 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2314.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2314.1300 Message-ID: Date: Fri, 21 Dec 2001 13:39:59 -0000 NNTP-Posting-Host: 213.86.13.101 X-Trace: news.uk.colt.net 1008942059 213.86.13.101 (Fri, 21 Dec 2001 13:40:59 GMT) NNTP-Posting-Date: Fri, 21 Dec 2001 13:40:59 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!small.news.tele.dk!212.74.64.35!colt.net!news.uk.colt.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12622 Virtex meta posts in this group: http://groups.google.com/groups?as_q=virtex&as_oq=metastable%20metastability &as_ugroup=comp.arch.fpga&num=50&as_scoring=d&hl=en Meta posts in this group by Peter Alfke: http://groups.google.com/groups?as_q=metastability&as_ugroup=comp.arch.fpga& as_uauthors=Peter%20Alfke&num=50&as_scoring=d&hl=en watch the wrap on the links ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: CE on XILINX FFs and Metastability Date: Fri, 21 Dec 2001 12:51:23 -0800 Organization: Xilinx Lines: 45 Message-ID: <3C23A0CB.806FD9AF@xilinx.com> References: <3c2305a6$1@news.uni-rostock.de> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Frank Papenfuss Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!14298!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12704 Hi, Frank. What you describe is the classical double-synchronizer ( sped up by using alternate clock edges) At any reasonable clock rate, this will stop the propagation of metastable signals. So, go ahead. Frohes Fest ! Peter Alfke, Xilinx Applications =============================== Frank Papenfuss wrote: > Dear FPGA comunity, > > I have a design that must cope with asynchronous input > signals. Basically I have a WE pulse that gates a data > vector into the chip. The WE signal is sampled by two > FFs to enshure proper pulse detection. One FF is clocked > by the positive edge of the system clock and > one by the negative edge (I do not want to go > into too much details about why I must do this). The FFs > that sample the pulse connect to the CE (clock enable) > of the following FF to prevent the metastable state from > probagating actually into the design. Since I have only > simulated this so far I cannot say if it will really work > inside the chip (which will be a XILINX FPGA). > > My question is: Has anyone experience with using CE as > a mean to prevent a metastable state from probagating > further. > > Tool Setup: > ----------- > Simulation & Synthesis: SYNOPSIS Ver 1999.10 > Target Technology Mapping: XILINX Design Manager V3.3.08i > Target Part: XILINX VirtexE XCV300E-8-PQ240 > > I would also be greatful if you could point me to some > electronically available article, technote or appnote > about this topic, if available. > > Thanks in advance, > FRANK ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: CE on XILINX FFs and Metastability Date: Fri, 21 Dec 2001 12:51:36 -0800 Organization: Xilinx Lines: 45 Message-ID: <3C23A0D8.9E15AEAE@xilinx.com> References: <3c2305a6$1@news.uni-rostock.de> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Frank Papenfuss Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out.visi.com!hermes.visi.com!nycmny1-snh1.gtei.net!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12703 Hi, Frank. What you describe is the classical double-synchronizer ( sped up by using alternate clock edges) At any reasonable clock rate, this will stop the propagation of metastable signals. So, go ahead. Frohes Fest ! Peter Alfke, Xilinx Applications =============================== Frank Papenfuss wrote: > Dear FPGA comunity, > > I have a design that must cope with asynchronous input > signals. Basically I have a WE pulse that gates a data > vector into the chip. The WE signal is sampled by two > FFs to enshure proper pulse detection. One FF is clocked > by the positive edge of the system clock and > one by the negative edge (I do not want to go > into too much details about why I must do this). The FFs > that sample the pulse connect to the CE (clock enable) > of the following FF to prevent the metastable state from > probagating actually into the design. Since I have only > simulated this so far I cannot say if it will really work > inside the chip (which will be a XILINX FPGA). > > My question is: Has anyone experience with using CE as > a mean to prevent a metastable state from probagating > further. > > Tool Setup: > ----------- > Simulation & Synthesis: SYNOPSIS Ver 1999.10 > Target Technology Mapping: XILINX Design Manager V3.3.08i > Target Part: XILINX VirtexE XCV300E-8-PQ240 > > I would also be greatful if you could point me to some > electronically available article, technote or appnote > about this topic, if available. > > Thanks in advance, > FRANK ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: CE on XILINX FFs and Metastability Date: Fri, 21 Dec 2001 12:59:30 -0800 Organization: Xilinx Lines: 49 Message-ID: <3C23A2B3.FE365AB5@xilinx.com> References: <3c2305a6$1@news.uni-rostock.de> <3C230E88.7DB38FF@algor.co.uk> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Rick Filipkiewicz Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!enews.sgi.com!nntp.wetware.com!attdv1!attdv2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12698 Rick Filipkiewicz wrote: > Frank Papenfuss wrote: > > > Dear FPGA comunity, > > > > I have a design that must cope with asynchronous input > > signals. Basically I have a WE pulse that gates a data > > vector into the chip. The WE signal is sampled by two > > FFs to enshure proper pulse detection. One FF is clocked > > by the positive edge of the system clock and > > one by the negative edge (I do not want to go > > into too much details about why I must do this). The FFs > > that sample the pulse connect to the CE (clock enable) > > of the following FF to prevent the metastable state from > > probagating actually into the design. Since I have only > > simulated this so far I cannot say if it will really work > > inside the chip (which will be a XILINX FPGA). > > > > My question is: Has anyone experience with using CE as > > a mean to prevent a metastable state from probagating > > further. > > > > Frank, > > It is an unfortunate fact that if an signal from a source async to a > clock is sampled on that clock then there is always a chance that a > metastable state could propagate arbitrarily far into your system. > > Metastability is a statistical thing and so all you can do is reduce the > probability of its affecting your system to some very small number (or > the MTBF >> time between you changing jobs). > The first flip-flop will undoubtably go metastable occasionally. For the second flip-flop to go metastable, the first Q must transition just at the sensitive moment of the second flip-flop. That is very unlikely ( but the probability is not zero) If the settling time margin from the Q of the first flip-flop to the D of the second flip-flop is reasonably long ( 5 ns or more) then the probability of the second Q behaving strangely will border on zero. If human life depends on the proper operation of this circuit, add another stage. Peter Alfke