Reply-To: "Jason Berringer" From: "Jason Berringer" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: ISA syncronization? Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: Date: Sat, 8 Dec 2001 11:03:41 -0500 NNTP-Posting-Host: 216.209.137.63 X-Complaints-To: abuse@sympatico.ca X-Trace: news20.bellglobal.com 1007827440 216.209.137.63 (Sat, 08 Dec 2001 11:04:00 EST) NNTP-Posting-Date: Sat, 08 Dec 2001 11:04:00 EST Organization: Bell Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!torn!webster!nf1.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12237 Hello all, Another novice question here that I would appreciate some help with. I'm writing the code for a simple ISA interface, simple being that this card is only going to interrupt the processor (at 1kHz) and place 16 bit data blocks on the bus when the address is decoded. My question is about syncronization. Do I need to syncronize to the bclk pin on the ISA bus or should I bring that clock into my 100MHz clock domain to syncronize to that? Or is syncronization even necessary on the ISA bus. In all of the limited documentation that I have found on the ISA bus it isn't very specific. I would appreciate if anyone has more specific technical documentation on the bus if they could email me a copy or a snippit of some code verified would be great. No one seems to care about the ISA bus anymore, it's all PCI but we are using PC/104 gear in our designs and therefore are at present using the ISA bus. A follow up question is; is it better to design using a finite state machine approach for the ISA bus, or because mine is a scaled down version, is it necessary? I have done a quick VHDL design but it at present does not include any syncronization. Thanks for the help Jason ###### From: ikauranen@netscape.net (ikauranen) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: ISA syncronization? Date: 9 Dec 2001 14:04:41 -0800 Organization: http://groups.google.com/ Lines: 9 Message-ID: References: NNTP-Posting-Host: 195.5.130.106 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1007935481 5361 127.0.0.1 (9 Dec 2001 22:04:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 9 Dec 2001 22:04:41 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!feed2.onemain.com!feed1.onemain.com!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12289 Hello Jason, For implementation of the PC104/ISA interface, I suggest you to use read/write strobes, address ADDR[], address enable AEN, and CH READY (if delay is required) signals, without the clock. Thus, the design will include [inferred, in the case of VHDL] register and comparator; no state machines is required. Best Regards, Igor Kauranen ###### Reply-To: "Jason Berringer" From: "Jason Berringer" Newsgroups: comp.arch.fpga References: Subject: Re: ISA syncronization? Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Message-ID: Date: Sun, 9 Dec 2001 18:32:58 -0500 NNTP-Posting-Host: 206.172.135.115 X-Complaints-To: abuse@sympatico.ca X-Trace: news20.bellglobal.com 1007940815 206.172.135.115 (Sun, 09 Dec 2001 18:33:35 EST) NNTP-Posting-Date: Sun, 09 Dec 2001 18:33:35 EST Organization: Bell Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!news1.tor.metronet.ca!webster!nf1.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12287 Thanks for the examples, it always help to see how others have approached the task, my only worry with the asyncronous exchange is that some fo the data might be lost, I'm fairly confident that it won't but you never know. Have you ever noticed any wierd or unexplained data exchanges in your design for your PC/104 FPGA card? The reason I ask is at present the card we have, which I\m trying to debug seems to have inconsistent readings unless we install another card onto the stack. I have a feeling it's beacause the ISA bus isn't handled very well in that code. Jason "Peter Wallace" wrote in message news:ee739ce.0@WebX.sUN8CHnE... > I think its just as easy to regard the bus as asynchronous and just build edge detectors to detect bus operations-- bringing them into your local clock domain > > http://www.mesanet.com/4i34.zip > > (support code for our FPGA based PC/104 card) > > Has some PC104 examples including 16 bit bus interface/interrupt generation logic... > > PCW ###### From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: ISA syncronization? Date: Mon, 10 Dec 2001 00:46:11 -0500 Lines: 48 Message-ID: <3C144C23.C0188798@yahoo.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVawN9CLBJjJ/RbGo5aSmvpNK1tD50Up0xSodTMpVT9GUGRywv1YyrZL X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 10 Dec 2001 05:45:35 GMT X-Mailer: Mozilla 4.74 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12294 Jason, I recommend , like the others, that you use an async interface. But you may need to sync the control input signals to your FSM. If there is a chance that a FF can go metastable and interfere with the FSM operation, you will need to add some circuitry to deal with this. Jason Berringer wrote: > > Hello all, > > Another novice question here that I would appreciate some help with. I'm > writing the code for a simple ISA interface, simple being that this card is > only going to interrupt the processor (at 1kHz) and place 16 bit data blocks > on the bus when the address is decoded. My question is about syncronization. > Do I need to syncronize to the bclk pin on the ISA bus or should I bring > that clock into my 100MHz clock domain to syncronize to that? Or is > syncronization even necessary on the ISA bus. In all of the limited > documentation that I have found on the ISA bus it isn't very specific. > > I would appreciate if anyone has more specific technical documentation on > the bus if they could email me a copy or a snippit of some code verified > would be great. No one seems to care about the ISA bus anymore, it's all PCI > but we are using PC/104 gear in our designs and therefore are at present > using the ISA bus. > > A follow up question is; is it better to design using a finite state machine > approach for the ISA bus, or because mine is a scaled down version, is it > necessary? I have done a quick VHDL design but it at present does not > include any syncronization. > > Thanks for the help > > Jason -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Miem Chan" Newsgroups: comp.arch.fpga,comp.lang.vhdl References: Subject: Re: ISA syncronization? Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Original-NNTP-Posting-Host: 203.134.81.188 Message-ID: <3c155562_1@news.iprimus.com.au> X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Tue, 11 Dec 2001 11:37:42 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1008031066 203.134.67.67 (Tue, 11 Dec 2001 11:37:46 EST) NNTP-Posting-Date: Tue, 11 Dec 2001 11:37:46 EST Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:12322 I'm sorry for my intervention. I do not have an answer to original poster but an additional question in similar nature. I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an ISA bus board by using GAL16V8D (or something similar) rather than 7485, 74688 etc conventional TTLs. Would some one help/show/point me how to use programmable logic devices to build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA bus board ? Thanks. Miem Chan miemchan@yahoo.com.au "ikauranen" wrote in message news:b0438406.0112091404.765e9599@posting.google.com... > Hello Jason, > For implementation of the PC104/ISA interface, I suggest you to use > read/write strobes, address ADDR[], address enable AEN, and CH READY > (if delay is required) signals, without the clock. Thus, the design > will include [inferred, in the case of VHDL] register and comparator; > no state machines is required. > > Best Regards, > Igor Kauranen ###### From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: ISA syncronization? Date: Mon, 10 Dec 2001 23:16:10 -0500 Lines: 52 Message-ID: <3C15888A.42688061@yahoo.com> References: <3c155562_1@news.iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZcdr2Eu60ub6pGYBmG33Yt2pgXJRMX1wM50Qm3KmFcTlXg7Ae9uUQW X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 11 Dec 2001 04:15:57 GMT X-Mailer: Mozilla 4.74 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12360 Using a PLD for address decoding is not hard if you know how to use the tools for designing with PLDs. The ISA decode is really just a wide AND gate with inversions on the logic low signals. You can design a PLD using a schematic based tool or you can use an HDL like CUPL, ABEL or VHDL. Often the tools are free from the logic supplier. None of this is hard. Start by getting your hands on the tools. Check with your PLD source. Miem Chan wrote: > > I'm sorry for my intervention. > I do not have an answer to original poster but an additional question in > similar nature. > > I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an > ISA bus board by using GAL16V8D (or something similar) rather than 7485, > 74688 etc conventional TTLs. > > Would some one help/show/point me how to use programmable logic devices to > build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA > bus board ? > > Thanks. > > Miem Chan > miemchan@yahoo.com.au > > "ikauranen" wrote in message > news:b0438406.0112091404.765e9599@posting.google.com... > > Hello Jason, > > For implementation of the PC104/ISA interface, I suggest you to use > > read/write strobes, address ADDR[], address enable AEN, and CH READY > > (if delay is required) signals, without the clock. Thus, the design > > will include [inferred, in the case of VHDL] register and comparator; > > no state machines is required. > > > > Best Regards, > > Igor Kauranen -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Philip Freidin Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: ISA syncronization? Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: References: <3c155562_1@news.iprimus.com.au> X-Newsreader: Forte Agent 1.8/32.553 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 267 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1008045960 ST000 216.103.85.188 (Mon, 10 Dec 2001 23:46:00 EST) NNTP-Posting-Date: Mon, 10 Dec 2001 23:46:00 EST X-UserInfo1: Q[R_PJSCOPWKRRH[ZROZOQTDEB\@PD\MNPWZKB]MPXHTEPIB_NVUAH_[BL[\IRKIANGGJBFNJF_DOLSCENSY^U@FRFUEXR@KFXYDBPWBCDQJA@X_DCBHXR[C@\EOKCJLED_SZ@RMWYXYWE_P@\\GOIW^@SYFFSWHFIXMADO@^[ADPRPETLBJ]RDGENSKQQZN Date: Tue, 11 Dec 2001 04:46:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!newscon02.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12352 On Tue, 11 Dec 2001 11:37:42 +1100, "Miem Chan" wrote: > >I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an >ISA bus board by using GAL16V8D (or something similar) rather than 7485, >74688 etc conventional TTLs. > >Would some one help/show/point me how to use programmable logic devices to >build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA >bus board ? > >Thanks. > >Miem Chan >miemchan@yahoo.com.au The following code is for a trivial PAL that is used to load FPGAs via the ISA bus. It implements 2 single bit output ports and 3 single bit input ports. These connect to the FPGA's pins: PIN 18 PROG ; output PIN 19 CCLK ; output PIN 20 DIN ; output PIN 21 INIT ; input PIN 22 DONE ; input The rest of the pins go to the ISA bus, except for a chip select that can also go to the FPGA, if you need it (after config is done). Philip Freidin >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> THIS CODE COMES WITH NO GUARANTEES. USE AT YOUR OWN RISK. NO SUPPORT AVAILABLE. COPY AND REDISTRIBUTE IF YOU WISH. (give me credit if you want) WRITTEN FOR THE NO LONGER AVAILABLE PAL COMPILATION SOFTWARE FROM INTEL. REWRITE FOR SOMETHING ELSE THAT YOU HAVE AVAILABLE. YOUR MILAGE MAY VARY. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Title I/O Port for configuring LCA from PC Bus Pattern None Revision 1.0 Author Philip Freidin Company Fliptronics Date 08/17/94 CHIP config 22V10 PIN 1 IOW ; input PIN 2 SA9 ; input PIN 3 SA8 ; input PIN 4 SA7 ; input PIN 5 SA6 ; input PIN 6 SA5 ; input PIN 7 SA4 ; input PIN 8 SA3 ; input PIN 9 SA2 ; input PIN 10 SA1 ; input PIN 11 SA0 ; input PIN 13 AEN ; input PIN 14 SD0 ; input PIN 15 DEV_SEL ; output PIN 16 FPGA_SEL ; output ;PIN 17 PIN 18 PROG ; output PIN 19 CCLK ; output PIN 20 DIN ; output PIN 21 INIT ; input PIN 22 DONE ; input PIN 23 IOR ; input string base_addr ' SA9 * SA8 * /SA7 * /SA6 * /SA5 * /SA4 * /SA3 ' string dev_0 ' /SA2 * /SA1 ' string dev_2 ' /SA2 * SA1 ' string dev_4 ' SA2 * /SA1 ' string dev_6 ' SA2 * SA1 ' equations ; the following is for a base address of 0x0300 ; this matches addresses 0x0300, 0x0302 and 0x0304 for this PAL, and 0x0306 ; for the FPGA. ; PAL select is for R/W on 0x0300 and 0x0302, and W only on 0x0304 DEV_SEL = base_addr * dev_0 * /AEN * /IOW + base_addr * dev_0 * /AEN * /IOR + base_addr * dev_2 * /AEN * /IOW + base_addr * dev_2 * /AEN * /IOR + base_addr * dev_4 * /AEN * /IOW DEV_SEL.trst = vcc ; FPGA select is for R/W on 0x0306 (and its aliases) FPGA_SEL = base_addr * dev_6 * /AEN * /IOW + base_addr * dev_6 * /AEN * /IOR FPGA_SEL.trst = vcc din := sd0 * DEV_SEL * dev_0 + din * /DEV_SEL + din * dev_2 + din * dev_4 din.trst = vcc cclk := sd0 * DEV_SEL * dev_2 + cclk * /DEV_SEL + cclk * dev_0 + cclk * dev_4 cclk.trst = vcc prog := sd0 * DEV_SEL * dev_4 + prog * /DEV_SEL + prog * dev_0 + prog * dev_2 prog.trst = vcc sd0 = DEV_SEL * dev_0 * done + DEV_SEL * dev_2 * init sd0.trst = DEV_SEL * /ior ; end of design SIMULATION VECTOR A := [ SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ] ; ; start with iow high, address bus at 0, and done, init, and sd0 low, ; and aen and ior high ; setf IOW setf a := 0x0000 setf /done /init /sd0 aen ior ; ; while address is 0 and aen is high, clock with sd0 both 0 and 1 ; no outputs should change ; clockf IOW setf sd0 clockf IOW setf /sd0 clockf IOW ; ; now bring aen low and do it again ; no outputs should change ; setf /aen sd0 clockf IOW setf /sd0 clockf IOW ; ; take aen high, and set address to 0x0300 ; no outputs should change ; setf aen setf a := 0x300 clockf IOW setf sd0 clockf IOW ; ; with aen low, address at 0x0300, we now write a 1 to DIN ; setf /aen clockf IOW ; DIN=1 CCLK=X PROG=X ; ; set aen high, make sure we dont write ; setf aen /sd0 ; DIN=1 CCLK=X PROG=X clockf IOW ; ; set aen low, set address to 2ff, make sure we dont write ; setf /aen setf a := 0x02ff clockf IOW ; DIN=1 CCLK=X PROG=X ; ; now write a 0 to cclk and the prog ; setf a := 0x302 clockf IOW ; DIN=1 CCLK=0 PROG=X setf a := 0x304 clockf IOW ; DIN=1 CCLK=0 PROG=0 setf a := 0x300 setf /sd0 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; set aen high, and sd0. all outputs should remain unchanged ; setf aen sd0 setf a := 0x300 clockf IOW ; DIN=0 CCLK=0 PROG=0 setf a := 0x302 clockf IOW ; DIN=0 CCLK=0 PROG=0 setf a := 0x304 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; now write 1 to din, cclk and prog ; setf /aen setf a := 0x0300 clockf IOW ; DIN=1 CCLK=0 PROG=0 setf a := 0x302 clockf IOW ; DIN=1 CCLK=1 PROG=0 setf a := 0x304 clockf IOW ; DIN=1 CCLK=1 PROG=1 ; ; now write 0 to din, cclk, prog ; setf /sd0 setf a := 0x0300 clockf IOW ; DIN=0 CCLK=1 PROG=1 setf a := 0x302 clockf IOW ; DIN=0 CCLK=0 PROG=1 setf a := 0x304 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; now try some reads. first do a non-read ; setf sd0 setf a := 0 setf /ior setf ior ; ; now read DONE ; setf a := 0x0300 setf /ior ; ; now check that done passes through ; setf done ; ; now read init ; setf a := 0x0302 ; ; now change init ; setf init setf /init ; ; end read ; setf ior ; ; do a read from the fpga ; setf a := 0x0306 setf /ior setf ior ; ; do a write to the fpga ; clockf IOW ; end of simulation Philip Freidin Fliptronics