Message-ID: <3C0535D4.868C1E65@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: SpartanIIE Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 10 Date: Wed, 28 Nov 2001 19:07:00 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1006974423 62.254.210.251 (Wed, 28 Nov 2001 19:07:03 GMT) NNTP-Posting-Date: Wed, 28 Nov 2001 19:07:03 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newscore.univie.ac.at!194.74.65.73.MISMATCH!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11905 Can anybody answer: o Do they relate to VirtexE's in the same way as SpartanII did to the Virtex ? Esp wrt timing. o What the ^$%£$£ is an FT package ? I'm beginning to wonder if package proliferation has taken the place of all those quirky TTL MSI devices I used to spend a lot of time trying to figure a use for. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Wed, 28 Nov 2001 15:06:56 -0500 Lines: 33 Message-ID: <3C0543E0.2EEC6662@yahoo.com> References: <3C0535D4.868C1E65@algor.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: UmFuZG9tSVZUO4nPkDUNMVHa7yFqCB2DzNeWSec4HWe8y94qnXayOpqyaebXSsZY X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 28 Nov 2001 20:06:36 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!64.245.249.19.MISMATCH!dfw3-feed1.news.digex.net!dca6-feed1.news.digex.net!intermedia!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11921 I can't say anything about the connection to the Virtex IIE parts except that I expect that is correct. But the FT package is just a lower profile version of the FG package. There are a lot of applications where height is very, very important. Didn't you go to the web site to find the packaging data sheet? That is where I found it. Rick Filipkiewicz wrote: > > Can anybody answer: > > o Do they relate to VirtexE's in the same way as SpartanII did to the > Virtex ? Esp wrt timing. > > o What the ^$%£$£ is an FT package ? I'm beginning to wonder if package > proliferation has taken the place of all those quirky TTL MSI devices I > used to spend a lot of time trying to figure a use for. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Jan Gray" Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Wed, 28 Nov 2001 13:18:19 -0800 Organization: Gray Research LLC Lines: 27 Message-ID: <9u3knp$53a$1@slb4.atl.mindspring.net> References: <3C0535D4.868C1E65@algor.co.uk> NNTP-Posting-Host: 04.21.a1.6d X-Server-Date: 28 Nov 2001 21:25:13 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!feed2.onemain.com!feed1.onemain.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11950 "Rick Filipkiewicz" wrote in message news:3C0535D4.868C1E65@algor.co.uk... > o Do they relate to VirtexE's in the same way as SpartanII did to the > Virtex ? Esp wrt timing. http://fpgacpu.org/#011120: "You might think that as Virtex-E is to Virtex, so is Spartan-IIE to Spartan-II But you would be wrong. According to data sheets, whereas an XCV200 has 14 BRAMs (56 Kb) and the XCV200E has 28 BRAMs (112 Kb), in the Spartan-II/E family, both the XC2S200 and (alas) the XC2S200E have the same 14 BRAMs (56 Kb). ... But let us count our blessings. The new Spartan-IIE family is lower-voltage, faster (470 ps TILO (2SxxxE-6) vs. 700 ps TILO (2Sxxx-5)), offers a larger part (the 32x48 CLB = 6144 logic cell XC2S300E), supports tons of different I/O signalling standards, and (thank you Xilinx) comes in TQ144 and PQ208 QFP packages. " Jan Gray Gray Research LLC ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Wed, 28 Nov 2001 13:32:01 -0800 Organization: Xilinx Lines: 20 Message-ID: <3C0557D0.9DC2A70D@xilinx.com> References: <3C0535D4.868C1E65@algor.co.uk> <3C0543E0.2EEC6662@yahoo.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: rickman Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!xmission!news-hog.berkeley.edu!ucberkeley!enews.sgi.com!nntp.wetware.com!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11930 rickman wrote: > I can't say anything about the connection to the Virtex IIE parts except > that I expect that is correct. Spartan-IIE is functionally identical to Virtex-E, but has fewer BlockRAMs, and slightly different (?) timing parameters, and it comes in different packages and fewer speed grades. Peter Alfke > > > But the FT package is just a lower profile version of the FG package. > There are a lot of applications where height is very, very important. > Didn't you go to the web site to find the packaging data sheet? That is > where I found it. > ###### From: "Damir Danijel Zagar" Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Thu, 29 Nov 2001 09:12:18 +0100 Organization: Iskon Internet d.d. Lines: 40 Message-ID: <9u4qkj$brh$1@sunce.iskon.hr> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> NNTP-Posting-Host: wr-fgmicro.iskon.hr X-Trace: sunce.iskon.hr 1007021523 12145 213.191.147.56 (29 Nov 2001 08:12:03 GMT) X-Complaints-To: abuse@iskon.hr NNTP-Posting-Date: 29 Nov 2001 08:12:03 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!Iskon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11938 According to Spartan-IIE datasheet, both 200 parts have the same amount of block ram (56k). Damir "Jan Gray" wrote in message news:9u3knp$53a$1@slb4.atl.mindspring.net... > "Rick Filipkiewicz" wrote in message > news:3C0535D4.868C1E65@algor.co.uk... > > o Do they relate to VirtexE's in the same way as SpartanII did to the > > Virtex ? Esp wrt timing. > > http://fpgacpu.org/#011120: > > "You might think that > > as Virtex-E is to Virtex, so is Spartan-IIE to Spartan-II > > But you would be wrong. According to data sheets, whereas an XCV200 has 14 > BRAMs (56 Kb) and the XCV200E has 28 BRAMs (112 Kb), in the Spartan-II/E > family, both the XC2S200 and (alas) the XC2S200E have the same 14 BRAMs (56 > Kb). > ... > But let us count our blessings. The new Spartan-IIE family is lower-voltage, > faster (470 ps TILO (2SxxxE-6) vs. 700 ps TILO (2Sxxx-5)), offers a larger > part (the 32x48 CLB = 6144 logic cell XC2S300E), supports tons of different > I/O signalling standards, and (thank you Xilinx) comes in TQ144 and PQ208 > QFP packages. " > > Jan Gray > Gray Research LLC > > > ###### From: "Damir Danijel Zagar" Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Thu, 29 Nov 2001 10:57:32 +0100 Organization: Iskon Internet d.d. Lines: 51 Message-ID: <9u50ps$fj7$1@sunce.iskon.hr> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> <9u4qkj$brh$1@sunce.iskon.hr> NNTP-Posting-Host: wr-fgmicro.iskon.hr X-Trace: sunce.iskon.hr 1007027836 15975 213.191.147.56 (29 Nov 2001 09:57:16 GMT) X-Complaints-To: abuse@iskon.hr NNTP-Posting-Date: 29 Nov 2001 09:57:16 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4807.1700 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!Iskon!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11937 Sorry, missed the upper part of Jan's post. Damir "Damir Danijel Zagar" wrote in message news:9u4qkj$brh$1@sunce.iskon.hr... > According to Spartan-IIE datasheet, both 200 parts have the same > amount of block ram (56k). > > Damir > > > "Jan Gray" wrote in message > news:9u3knp$53a$1@slb4.atl.mindspring.net... > > "Rick Filipkiewicz" wrote in message > > news:3C0535D4.868C1E65@algor.co.uk... > > > o Do they relate to VirtexE's in the same way as SpartanII did to the > > > Virtex ? Esp wrt timing. > > > > http://fpgacpu.org/#011120: > > > > "You might think that > > > > as Virtex-E is to Virtex, so is Spartan-IIE to Spartan-II > > > > But you would be wrong. According to data sheets, whereas an XCV200 has 14 > > BRAMs (56 Kb) and the XCV200E has 28 BRAMs (112 Kb), in the Spartan-II/E > > family, both the XC2S200 and (alas) the XC2S200E have the same 14 BRAMs > (56 > > Kb). > > ... > > But let us count our blessings. The new Spartan-IIE family is > lower-voltage, > > faster (470 ps TILO (2SxxxE-6) vs. 700 ps TILO (2Sxxx-5)), offers a larger > > part (the 32x48 CLB = 6144 logic cell XC2S300E), supports tons of > different > > I/O signalling standards, and (thank you Xilinx) comes in TQ144 and PQ208 > > QFP packages. " > > > > Jan Gray > > Gray Research LLC > > > > > > > > ###### Message-ID: <3C06AB1D.7ACE3735@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE References: <3C0535D4.868C1E65@algor.co.uk> <3C0543E0.2EEC6662@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 22 Date: Thu, 29 Nov 2001 21:39:41 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1007069984 62.254.210.251 (Thu, 29 Nov 2001 21:39:44 GMT) NNTP-Posting-Date: Thu, 29 Nov 2001 21:39:44 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!newsfeed.online.be!news1.carrier1.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11990 rickman wrote: > > But the FT package is just a lower profile version of the FG package. > There are a lot of applications where height is very, very important. > Didn't you go to the web site to find the packaging data sheet? That is > where I found it. > You're absolutely right. Having a class 1 bad day made me blind (CVS crashed during an attempted remote checkin and scribbled junk over some files just after I found what seems to be the recurrence of an old Synplify bug. !? Should have stopped right there & gone out for a beer or 10). Apologies to Xilinx. I'm trying to imagine an app that needs a ~0.5mm height improvment & can only think of the reverse side of a PCI card where the max component height is 0.8'' IIRC. ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Thu, 29 Nov 2001 15:58:18 -0800 Organization: Xilinx Lines: 47 Message-ID: <3C06CB9A.D9E295C1@xilinx.com> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> <9u4qkj$brh$1@sunce.iskon.hr> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Damir Danijel Zagar Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!cyclone.swbell.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11989 Just to clarify: Virtex-E: XCV200E has 112 K bits of BlockRAM = 28 BlockRAMs Spartan-IIE: XC2S200E has 56 K of BlockRAM = 14 BlockRAMs. The data sheets say it all. Peter Alfke =================================== Damir Danijel Zagar wrote: > According to Spartan-IIE datasheet, both 200 parts have the same > amount of block ram (56k). > > Damir > > "Jan Gray" wrote in message > news:9u3knp$53a$1@slb4.atl.mindspring.net... > > "Rick Filipkiewicz" wrote in message > > news:3C0535D4.868C1E65@algor.co.uk... > > > o Do they relate to VirtexE's in the same way as SpartanII did to the > > > Virtex ? Esp wrt timing. > > > > http://fpgacpu.org/#011120: > > > > "You might think that > > > > as Virtex-E is to Virtex, so is Spartan-IIE to Spartan-II > > > > But you would be wrong. According to data sheets, whereas an XCV200 has 14 > > BRAMs (56 Kb) and the XCV200E has 28 BRAMs (112 Kb), in the Spartan-II/E > > family, both the XC2S200 and (alas) the XC2S200E have the same 14 BRAMs > (56 > > Kb). > > ... > > But let us count our blessings. The new Spartan-IIE family is > lower-voltage, > > faster (470 ps TILO (2SxxxE-6) vs. 700 ps TILO (2Sxxx-5)), offers a larger > > part (the 32x48 CLB = 6144 logic cell XC2S300E), supports tons of > different > > I/O signalling standards, and (thank you Xilinx) comes in TQ144 and PQ208 > > QFP packages. " > > > > Jan Gray > > Gray Research LLC > > > > > > ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Thu, 29 Nov 2001 22:05:38 -0500 Lines: 40 Message-ID: <3C06F782.E0509560@yahoo.com> References: <3C0535D4.868C1E65@algor.co.uk> <3C0543E0.2EEC6662@yahoo.com> <3C06AB1D.7ACE3735@algor.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVax2ZPttuO8QY6CQkCJ0VhEnC4+jeeE08PujYdJu0P4/rB3RYWj5ebD X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Nov 2001 03:04:58 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!jfk3-feed1.news.digex.net!dca6-feed2.news.digex.net!intermedia!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12018 Rick Filipkiewicz wrote: > > rickman wrote: > > > > > But the FT package is just a lower profile version of the FG package. > > There are a lot of applications where height is very, very important. > > Didn't you go to the web site to find the packaging data sheet? That is > > where I found it. > > > > You're absolutely right. Having a class 1 bad day made me blind (CVS crashed > during an attempted remote checkin and scribbled junk over some files just > after I found what seems to be the recurrence of an old Synplify bug. !? > Should have stopped right there & gone out for a beer or 10). Apologies to > Xilinx. > > I'm trying to imagine an app that needs a ~0.5mm height improvment & can only > think of the reverse side of a PCI card where the max component height is > 0.8'' IIRC. I assume that you mean 0.08". Is that really true? I am used to 0.1" being the "standard" back side height for most boards. Even so, the FG256 is only 0.079" (2 mm). I would bet this is more for PCMCIA, PMC cards or some similar mezzanine application. Anyone know for sure why you need 1.55 mm vs. 2 mm component height (FT vs. FG)? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Thu, 29 Nov 2001 22:12:45 -0500 Lines: 40 Message-ID: <3C06F92D.41D20304@yahoo.com> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> <9u5toq$6af0u$1@ID-84877.news.dfncis.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaoL/yDcsHfjlSkZDyq5EKCDkynHVF5B88kHAnEEZD/Kbp1SItXuJPE X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Nov 2001 03:12:06 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12019 Falk Brunner wrote: > > "Jan Gray" schrieb im Newsbeitrag > news:9u3knp$53a$1@slb4.atl.mindspring.net... > > > part (the 32x48 CLB = 6144 logic cell XC2S300E), supports tons of > different > > I/O signalling standards, and (thank you Xilinx) comes in TQ144 and PQ208 > > QFP packages. " > > Who wants a PQ208 package? I dont want to build a brick wall ;-) > -- > MfG > Falk I think the idea is that they are not BGAs of any type. Not everyone wants the highest density known to man. Personally I don't think the CS144 package is used on enough parts, and what ever happened to the CS280??? That was one with enough IO to be useful and the open center made routing possible without dozens of inter-pad vias. The FG256 is one bear to route. The CS144 is nice, but not used on enough parts. Likely the cavity size won't let many parts fit inside... Speaking of routing... Anyone know where I can get guidelines for pad and via layout on these parts? I thought Xilinx had a document somewhere, but I can't find it on their web site. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Magnus Homann Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: 30 Nov 2001 13:58:53 +0100 Organization: Chalmers univ. of Technology Lines: 15 Message-ID: References: <3C0535D4.868C1E65@algor.co.uk> <3C0543E0.2EEC6662@yahoo.com> <3C06AB1D.7ACE3735@algor.co.uk> <3C06F782.E0509560@yahoo.com> NNTP-Posting-Host: licia.dtek.chalmers.se X-Trace: nyheter.chalmers.se 1007125133 23518 129.16.30.88 (30 Nov 2001 12:58:54 GMT) X-Complaints-To: abuse@chalmers.se NNTP-Posting-Date: 30 Nov 2001 12:58:54 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!t-online.de!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!195.54.122.107!newsfeed1.bredband.com!bredband!newsfeed1.telenordia.se!algonet!newsfeed.sunet.se!news01.sunet.se!news.chalmers.se!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12006 rickman writes: > I assume that you mean 0.08". Is that really true? I am used to 0.1" > being the "standard" back side height for most boards. Even so, the > FG256 is only 0.079" (2 mm). I would bet this is more for PCMCIA, PMC > cards or some similar mezzanine application. Anyone know for sure why > you need 1.55 mm vs. 2 mm component height (FT vs. FG)? My understanding is that the FT is thinner because it is. Fewer layers in the spackage substrate (2 instead of 4). Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.se ###### From: Marc Baker Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Fri, 30 Nov 2001 10:42:09 -0800 Organization: FPGA Applications Lines: 15 Message-ID: <3C07D301.5E505F50@xilinx.com> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> <9u5toq$6af0u$1@ID-84877.news.dfncis.de> <3C06F92D.41D20304@yahoo.com> Reply-To: marc.baker@xilinx.com NNTP-Posting-Host: apps46.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.74 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!news-hog.berkeley.edu!ucberkeley!enews.sgi.com!nntp.wetware.com!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11982 Xilinx pad and via layout info is at http://www.xilinx.com/partinfo/pkgs_pdf/pkgs1.pdf . The recommendations for the FT256 are identical to those for the FG256. rickman wrote: > Speaking of routing... Anyone know where I can get guidelines for pad > and via layout on these parts? I thought Xilinx had a document > somewhere, but I can't find it on their web site. -- Marc Baker Xilinx Applications ###### From: Marc Baker Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Fri, 30 Nov 2001 10:53:17 -0800 Organization: FPGA Applications Lines: 17 Message-ID: <3C07D59D.379E4552@xilinx.com> References: <3C0535D4.868C1E65@algor.co.uk> <3C0543E0.2EEC6662@yahoo.com> <3C06AB1D.7ACE3735@algor.co.uk> <3C06F782.E0509560@yahoo.com> Reply-To: marc.baker@xilinx.com NNTP-Posting-Host: apps46.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.74 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!newspeer.cwnet.com!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11986 Magnus Homann wrote: > My understanding is that the FT is thinner because it is. Fewer layers > in the package substrate (2 instead of 4). You are right. The main motivation for the FT package is lower cost, with the thinner dimensions being a side benefit and the reason it had to be called something besides FG. This is described in the Spartan-IIE FAQ on xilinx.com ( http://www.xilinx.com/products/spartan2e/faq100_sp2e.pdf ). -- Marc Baker Xilinx Applications ###### From: Nicolas Matringe Newsgroups: comp.arch.fpga Subject: Re: SpartanIIE Date: Mon, 10 Dec 2001 11:37:27 +0100 Organization: IPricot European Headquarter (formerly DotCom SA) Lines: 14 Message-ID: <3C149067.D21D3DF5@ipricot.com> References: <3C0535D4.868C1E65@algor.co.uk> <9u3knp$53a$1@slb4.atl.mindspring.net> NNTP-Posting-Host: nmatringe.fr.ipricot.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: mo5.fr.ipricot.com 1007980452 90866 192.168.31.116 (10 Dec 2001 10:34:12 GMT) X-Complaints-To: news@ipricot.com NNTP-Posting-Date: Mon, 10 Dec 2001 10:34:12 +0000 (UTC) X-Mailer: Mozilla 4.75 [fr] (WinNT; U) X-Accept-Language: fr,en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news-lei1.dfn.de!news-nue1.dfn.de!uni-erlangen.de!newsfeed1.telenordia.se!algonet!isdnet!news.dotcom.fr!news.fr.ipricot.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12281 Jumping in late due to holidays (lucky me :o) Jan Gray a écrit : > > [...] The new Spartan-IIE family [...] comes in TQ144 and PQ208 > QFP packages. " Unfortunately, they don't come in any package between 256 and 456 balls. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/