From: Kees van Reeuwijk Newsgroups: comp.arch.fpga Subject: Is there a full open-source synthesis path for any FPGA? Date: Wed, 28 Nov 2001 13:18:10 +0100 Organization: Delft University of Technology Lines: 14 Message-ID: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> NNTP-Posting-Host: lon.pds.twi.tudelft.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tudelft.nl 1006949878 23153 130.161.157.242 (28 Nov 2001 12:17:58 GMT) X-Complaints-To: usenet@news.tudelft.nl NNTP-Posting-Date: Wed, 28 Nov 2001 12:17:58 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!newsfeed.wirehub.nl!surfnet.nl!tudelft.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11882 Hi, I'm looking for an open-source implementation of the entire synthesis path for an FPGA, in particular placement, routing, and generation of a configuration file for the FPGA. Any pointers to such software would be greatly appreciated. Alternatively: I understand that the scarcity of such software is partly because vendors do not release enough information. Are there any modern devices for which this information *is* available? IOW, if I wanted to implement an open-source synthesis tool, which devices should I target? Again, recommendations would be greatly appreciated. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 28 Nov 2001 19:37:56 +0100 Organization: My own Private Self Lines: 48 Message-ID: <6u4rnebv23.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1006972676 801 10.0.3.2 (28 Nov 2001 18:37:56 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 28 Nov 2001 18:37:56 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11896 Kees van Reeuwijk writes: > I'm looking for an open-source implementation of the entire synthesis > path for an FPGA, in particular placement, routing, and generation of a > configuration file for the FPGA. Any pointers to such software would be > greatly appreciated. I do not know of any. All I know of are VHDL/Verilog -> EDIF/XNL, then the vendor tools for P&R take over to do ther top-sekrit work. > I understand that the scarcity of such software is partly because > vendors do not release enough information. s/partly/entirely/ Bad bad vendors :-(. P.S. to the @xilinx.com readers here: the often given reason for bitstream secrecy was that the PROM->FPGA link allows it to be grabbed and disassembled. With V2 the DES stuff was implemented to fix that hole. Is there any chance that the V2 bitstream will one day be publically (= non-NDA) documented? Perhaps an XAPP for those that want to know? > Are there any modern devices > for which this information *is* available? AFAIK none. Else I would be using them :-). > IOW, if I wanted to implement > an open-source synthesis tool, which devices should I target? Again, > recommendations would be greatly appreciated. The nearest I have found is to use Virtex/Spartan-II. For these there exists JBits. This is an API+library to modify/generate bitsreams. It is totally low-level (individual CLB features), driven by Java code (so usable to implement own CAE tools), free (as in beer, not as in speech), not crippled (such as artificially slowed to make an payware version attractive), written in Java (runs on Linux and BSD with Sun JDK). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: mrgs1000@yahoo.com (Mark) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 28 Nov 2001 10:58:00 -0800 Organization: http://groups.google.com/ Lines: 27 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> NNTP-Posting-Host: 63.88.196.33 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1006973880 10666 127.0.0.1 (28 Nov 2001 18:58:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 28 Nov 2001 18:58:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11913 Kees van Reeuwijk wrote in message news:<3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com>... > Hi, > > I'm looking for an open-source implementation of the entire synthesis > path for an FPGA, in particular placement, routing, and generation of a > configuration file for the FPGA. Any pointers to such software would be > greatly appreciated. > > Alternatively: > > I understand that the scarcity of such software is partly because > vendors do not release enough information. Are there any modern devices > for which this information *is* available? IOW, if I wanted to implement > an open-source synthesis tool, which devices should I target? Again, > recommendations would be greatly appreciated. I would venture to say that the primary road block to open-source tools is that they are too dificult to support and keep current for people to do for free. There are lots of flows for design entry and simulation, and new devices are released on a weekly basis. I occasionaly start using parts before they are released so I would not be able to wait for open-source tools to have the support. In fact, I have started designs where the vendors own tools didnt suport the part I was using. It's a nice dream, but I doubt it will ever become a reality. Mark ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 28 Nov 2001 23:05:55 +0100 Organization: My own Private Self Lines: 57 Message-ID: <6uy9kqa6v0.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1006985157 1116 10.0.3.2 (28 Nov 2001 22:05:57 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 28 Nov 2001 22:05:57 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11922 mrgs1000@yahoo.com (Mark) writes: > Kees van Reeuwijk wrote in message news:<3fl90u k0l3mmebi1703urlud5e91rou5af@4ax.com>... > > > > I understand that the scarcity of such software is partly because > > vendors do not release enough information. Are there any modern devices > > I would venture to say that the primary road block to open-source > tools is that they are too dificult to support and keep current for > people to do for free. As opposed to tons of video and ethernet chips that the Linux people seem to have no great problem with? Just simply support those chips that members of the open source group use. And the software users then buy those parts. Hint to vendors: if your part has open source support, it gets more recommendations ("take that one, it works"), and you get to sell more of them. I principially buy video and ethernet cards after consultion the on-line support databases. > There are lots of flows for design entry and > simulation, Just support those that the present maintainers use. And use those that are supported. > and new devices are released on a weekly basis. I Huh? As far as I see it Xilinx has so far created about 9 families (2000 3000 4000/Sparten 4000XL/SpartanXL 5200 6200 Virtex/SpartenII VirtexE/SpartanIIE Virtex2) in 15 years. Altera has 8 families (MAX3000 MAX7000 MAX9000 FLEX6K FLEX8K FLEX10K/ACEX APEX Mercury) in over 10 years. Lucent has IIRC 4 families of ORCA. Atmel 2 families (4000 6000). Actel I do not know, as I can not read their website (damn Flash and not HTML alternative). And a few other irrelevant manufacturers. So that makes about 2 falimies per year industrywide to support. Or simply only support a few of them and only use those. > occasionaly start using parts before they are released so I would not > be able to wait for open-source tools to have the support. In fact, I > have started designs where the vendors own tools didnt suport the part > I was using. Does not look like you are an average user there. :-) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Message-ID: <3C05F855.D93ECC02@wanabe.nl> From: Reinoud Organization: remains troubled X-Mailer: Mozilla 4.7 [en] (X11; I; Linux 2.2.17 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 Date: Thu, 29 Nov 2001 09:47:29 GMT NNTP-Posting-Host: 212.64.19.194 X-Trace: pollux.casema.net 1007027249 212.64.19.194 (Thu, 29 Nov 2001 10:47:29 MET) NNTP-Posting-Date: Thu, 29 Nov 2001 10:47:29 MET Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!cleanfeed.casema.net!leda.casema.net!pollux.casema.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11974 Kees van Reeuwijk wrote: > I understand that the scarcity of such software is partly because > vendors do not release enough information. Exactly. > Are there any modern devices for which this information *is* > available? Not really, but there is a workaround (MPGA): http://ce.et.tudelft.nl/~reinoud/mpga/README.html This is a hack of course. BTW, I'm working on a much improved architecture, keep an eye on the mailing list for updates (or have a chat in meatspace, note the URL, we must be close;). > IOW, if I wanted to implement an open-source synthesis tool, which > devices should I target? Again, recommendations would be greatly > appreciated. I warmly recommend targetting MPGA :-). Okay, I'm biased. - Reinoud (Spam goes to wanabe, mail to wanadoo!) ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Thu, 29 Nov 2001 10:21:10 -0500 Lines: 96 Message-ID: <3C065266.E43453F@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaXL0IWPgc7CWwKxZj8QfFkLkm3hlLt9u63W/GcP16wU369pwy4cyUo X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 29 Nov 2001 15:20:40 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11969 Neil Franklin wrote: > > mrgs1000@yahoo.com (Mark) writes: > > > Kees van Reeuwijk wrote in message news:<3fl90u > k0l3mmebi1703urlud5e91rou5af@4ax.com>... > > > > > > I understand that the scarcity of such software is partly because > > > vendors do not release enough information. Are there any modern devices > > > > I would venture to say that the primary road block to open-source > > tools is that they are too dificult to support and keep current for > > people to do for free. > > As opposed to tons of video and ethernet chips that the Linux people > seem to have no great problem with? > > Just simply support those chips that members of the open source group > use. And the software users then buy those parts. > > Hint to vendors: if your part has open source support, it gets more > recommendations ("take that one, it works"), and you get to sell more > of them. I principially buy video and ethernet cards after consultion > the on-line support databases. I think this is where the analogy between standard hardware support under a standard OS and FPGA support under a standard tool fails. Designers don't EVER want to compromize their choice of chip based on the tools. That would be more like vacationing in Newark because the bus is cheaper than taking a plane to the Bahamas! The idea that open source tool support will significantly impact the sales of FPGA chips is weak at best. The customers who buy lots of chips from the FPGA vendors get free tools and often have an FAE parked in their facility. I worked at one place where they still used brand Z chips in SPITE of the awful toolset they had to use. This was because the chip was $10 cheaper than the other brand. It ended up costing them a lot when they had to make revisions, but this was still the best solution in terms of PROFIT!!! (brand Z is not meant to be any particular company!) > > There are lots of flows for design entry and > > simulation, > > Just support those that the present maintainers use. And use those > that are supported. > > > and new devices are released on a weekly basis. I > > Huh? As far as I see it Xilinx has so far created about 9 families > (2000 3000 4000/Sparten 4000XL/SpartanXL 5200 6200 Virtex/SpartenII > VirtexE/SpartanIIE Virtex2) in 15 years. Altera has 8 families > (MAX3000 MAX7000 MAX9000 FLEX6K FLEX8K FLEX10K/ACEX APEX Mercury) > in over 10 years. Lucent has IIRC 4 families of ORCA. Atmel 2 > families (4000 6000). Actel I do not know, as I can not read their > website (damn Flash and not HTML alternative). And a few other > irrelevant manufacturers. > > So that makes about 2 falimies per year industrywide to support. Or > simply only support a few of them and only use those. But a familiy has some 10 different parts in it. Each of those parts has many packages and several speeds. Just getting the speed info (critical) is not an easy problem to solve. Without vendor support, you would be very hard pressed for anyone to trust your data. It certainly could be done, but the fact that it has not happened yet is a good indicator that it is harder than you seem to believe. > > occasionaly start using parts before they are released so I would not > > be able to wait for open-source tools to have the support. In fact, I > > have started designs where the vendors own tools didnt suport the part > > I was using. > > Does not look like you are an average user there. :-) Actually, I think he is a typical user. I think every place I have worked has used beta versions of the chips at one time or another. With a 4 to 6 month design time for an FPGA of any size, it pays to get started as early as possible. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: mrgs1000@yahoo.com (Mark) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 29 Nov 2001 12:23:09 -0800 Organization: http://groups.google.com/ Lines: 128 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> NNTP-Posting-Host: 63.88.196.33 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1007065390 3303 127.0.0.1 (29 Nov 2001 20:23:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 29 Nov 2001 20:23:10 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11960 rickman wrote in message news:<3C065266.E43453F@yahoo.com>... > Neil Franklin wrote: > > > > mrgs1000@yahoo.com (Mark) writes: > > > > > Kees van Reeuwijk wrote in message news:<3fl90u > k0l3mmebi1703urlud5e91rou5af@4ax.com>... > > > > > > > > I understand that the scarcity of such software is partly because > > > > vendors do not release enough information. Are there any modern devices > > > > > > I would venture to say that the primary road block to open-source > > > tools is that they are too dificult to support and keep current for > > > people to do for free. > > > > As opposed to tons of video and ethernet chips that the Linux people > > seem to have no great problem with? > > > > Just simply support those chips that members of the open source group > > use. And the software users then buy those parts. > > > > Hint to vendors: if your part has open source support, it gets more > > recommendations ("take that one, it works"), and you get to sell more > > of them. I principially buy video and ethernet cards after consultion > > the on-line support databases. > > I think this is where the analogy between standard hardware support > under a standard OS and FPGA support under a standard tool fails. > Designers don't EVER want to compromize their choice of chip based on > the tools. That would be more like vacationing in Newark because the bus > is cheaper than taking a plane to the Bahamas! > > The idea that open source tool support will significantly impact the > sales of FPGA chips is weak at best. The customers who buy lots of chips > from the FPGA vendors get free tools and often have an FAE parked in > their facility. I worked at one place where they still used brand Z > chips in SPITE of the awful toolset they had to use. This was because > the chip was $10 cheaper than the other brand. It ended up costing them > a lot when they had to make revisions, but this was still the best > solution in terms of PROFIT!!! (brand Z is not meant to be any > particular company!) > > > > > There are lots of flows for design entry and > > > simulation, > > > > Just support those that the present maintainers use. And use those > > that are supported. > > > > > and new devices are released on a weekly basis. I > > > > Huh? As far as I see it Xilinx has so far created about 9 families > > (2000 3000 4000/Sparten 4000XL/SpartanXL 5200 6200 Virtex/SpartenII > > VirtexE/SpartanIIE Virtex2) in 15 years. Altera has 8 families > > (MAX3000 MAX7000 MAX9000 FLEX6K FLEX8K FLEX10K/ACEX APEX Mercury) > > in over 10 years. Lucent has IIRC 4 families of ORCA. Atmel 2 > > families (4000 6000). Actel I do not know, as I can not read their > > website (damn Flash and not HTML alternative). And a few other > > irrelevant manufacturers. > > > > So that makes about 2 falimies per year industrywide to support. Or > > simply only support a few of them and only use those. > > But a familiy has some 10 different parts in it. Each of those parts has > many packages and several speeds. Just getting the speed info (critical) > is not an easy problem to solve. Without vendor support, you would be > very hard pressed for anyone to trust your data. > > It certainly could be done, but the fact that it has not happened yet is > a good indicator that it is harder than you seem to believe. > It’s actually even worse than that. Vendors are constantly re-characterizing the parts and re-releasing updated timing models for previously released parts. I haven’t paid strict attention, but during a single design phase, the timing models will often get updated on me at least twice. This brings up another point, in addition to the place and route tools, you have to also provide the timing analysis tools. It’s true that new families don’t get released often, but when they do, you have to practically throw out your place and route software because the architecture changes are too drastic. I like doing hand placement for critical circuits. When I switched from Virtex E to Virtex II not only was all of my work in Virtex E worthless, it was a hindrance > > > > occasionaly start using parts before they are released so I would not > > > be able to wait for open-source tools to have the support. In fact, I > > > have started designs where the vendors own tools didnt suport the part > > > I was using. > > > > Does not look like you are an average user there. :-) > > Actually, I think he is a typical user. I think every place I have > worked has used beta versions of the chips at one time or another. With > a 4 to 6 month design time for an FPGA of any size, it pays to get > started as early as possible. > To be clearer, I am a typical Tier One user of FPGAs. Meaning that the companies I have worked for are high profile international accounts for the FPGA companies. I cant say whether or not this makes me a “typical” user since I don’t know the demographics of all FPGA users from people like me down to hobbyists. However, I do know that from a volume standpoint my group uses more FPGAs than any other group. This means that the FPGA companies are mostly concerned with users like myself. For us, spending hundreds of thousands of dollars on 3rd party FPGA tools is no big deal. I say 3rd party because we wont spend a dime on any software from the FPGA company. They give us the tools free for the privilege of having us as a customer. It is true that an open-source community could support a limited number of devices, and it could stay behind the technology curve where specification churn is limited, and specification details are plentiful (no longer NDA) but this group would be limited and most likely restricted to hobbyists, students, and a few niche markets which have little competition. You can choose to debate this, however, the fact such tools don’t exist is pretty good support for my argument. Mark ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 00:15:22 +0100 Organization: My own Private Self Lines: 144 Message-ID: <6un115i2yd.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007075725 663 10.0.3.2 (29 Nov 2001 23:15:25 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 29 Nov 2001 23:15:25 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11976 mrgs1000@yahoo.com (Mark) writes: > rickman wrote in message news:<3C065266.E43453F@yahoo.com>... > > Neil Franklin wrote: > > > > > > Hint to vendors: if your part has open source support, it gets more > > > recommendations ("take that one, it works"), and you get to sell more > > > of them. I principially buy video and ethernet cards after consultion > > > the on-line support databases. > > > > Designers don't EVER want to compromize their choice of chip based on > > the tools. That would be more like vacationing in Newark because the bus > > is cheaper than taking a plane to the Bahamas! Which quite a lot of people actually do. Select on price, that is, not chose Newark. > > The idea that open source tool support will significantly impact the > > sales of FPGA chips is weak at best. Short term they may not. Think long term: they pull in more beginners, and so in time grow the population of FPGA developers, and so allow firms to emply more and so make more FPA projects and that sells more chips. > > chips in SPITE of the awful toolset they had to use. This was because > > the chip was $10 cheaper than the other brand. It ended up costing them > > a lot when they had to make revisions, but this was still the best > > solution in terms of PROFIT!!! If you are at 100'000 or even 1 mio sized series, no doubt this holds. But at 100 parts chip cost is not relevant. Tool support is. > > > > and new devices are released on a weekly basis. I > > > > > > So that makes about 2 falimies per year industrywide to support. Or > > > simply only support a few of them and only use those. > > > > But a familiy has some 10 different parts in it. And a Virtex CLB is a Virtex CLB, whether in XCV50, XCV1000 or XC2S200. > > Each of those parts has > > many packages Inserting pin out tables is not that much work. > > and several speeds. Just getting the speed info (critical) > > is not an easy problem to solve. Without vendor support, you would be > > very hard pressed for anyone to trust your data. That may be important for the n*100MHz croud. Not everyone is playing up there. Just all the potential sound processing applications, for one, 48kHz anyone? > > It certainly could be done, but the fact that it has not happened yet is > > a good indicator that it is harder than you seem to believe. So long non-availability of information makes it impossible, any "not happened" is 100% explained. Everything else remains speculation until that barrier falls. > It’s actually even worse than that. Vendors are constantly > re-characterizing the parts and re-releasing updated timing models for > previously released parts. Again only relevant to the top speed crowd. > This brings up another point, in addition to the place and route > tools, you have to also provide the timing analysis tools. You know how many home/edu people overclock CPUs? Raise frequency until crash, than drop by 10% is the sort of algorithm. It is "good enough" for the target audience. > It’s true that new families don’t get released often, but > when they do, you have to practically throw out your place and route > software because the architecture changes are too drastic. No different from the problems facing the gcc team when supporting code generators for new processors. They are presently at well over 20 architectures. And yes, some of the code generators suck. > doing hand placement for critical circuits. When I switched from > Virtex E to Virtex II not only was all of my work in Virtex E > worthless, it was a hindrance I doubt that "worthless". As ex-VirtexE-er you surely learned VirtexII faster than someone with no experience in placing and so also no knowledge what sort of pitfalls to look out for. Reuse of knowledge. > > > Does not look like you are an average user there. :-) > > > > Actually, I think he is a typical user. I think every place I have > > worked has used beta versions of the chips at one time or another. > To be clearer, I am a typical Tier One user of FPGAs. Meaning that the > companies I have worked for are high profile international accounts > for the FPGA companies. Your critique may apply to the situation at top commercial facilities. For home/edu (where I am) I would not expect that to be the case. > know that from a volume standpoint my group uses more FPGAs than any > other group. Present usage. Think a bit further into the future. There are millions of future developers out there. Presently they are playing around designing websites. What are they going to go into professionally? Websites. Now think if a few 10'000 of them were playing around with FPGAs. Whom will they be presenting their workforce to in 5 years? > plentiful (no longer NDA) but this group would be limited and most > likely restricted to hobbyists, students, and a few niche markets > which have little competition. And that is already usefull. > You can choose to debate this, however, the fact such tools > don’t exist is pretty good support for my argument. Nope. Non-existance comes from non-information. Proof for your argument will only be available after the information has been available for some time and not being used. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: edick@hotmail.com (Richard Erlacher) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Thu, 29 Nov 2001 21:59:53 GMT Organization: Erlacher Associates Reply-To: edick@hotmail.com Message-ID: <3c06af05.168448768@mindmeld.idcomm.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> X-Newsreader: Forte Free Agent 1.21/32.243 NNTP-Posting-Host: 216.98.199.156 X-Original-NNTP-Posting-Host: 216.98.199.156 X-Trace: 29 Nov 2001 21:59:35 GMT, 216.98.199.156 Lines: 44 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out.visi.com!hermes.visi.com!pulsar.dimensional.com!207.40.197.76.MISMATCH!dimensional.com!mindmeld.idcomm.com Xref: chonsp.franklin.ch comp.arch.fpga:12000 I'm not convinced of this. I'd say the reason that there's no open-source FPGA development system is that there are too few people capable of doing the work who've got the motivation (a) to create the thing, and (b) to maintain it. Has there ever been a well-written well-maintained open-source digital simulator for pre-FPGA parts? No ... Why? Too much work to create and maintain it. Too few people likely to share the work. Why should a job such as this be different. Dick On 28 Nov 2001 10:58:00 -0800, mrgs1000@yahoo.com (Mark) wrote: >Kees van Reeuwijk wrote in message news:<3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com>... >> Hi, >> >> I'm looking for an open-source implementation of the entire synthesis >> path for an FPGA, in particular placement, routing, and generation of a >> configuration file for the FPGA. Any pointers to such software would be >> greatly appreciated. >> >> Alternatively: >> >> I understand that the scarcity of such software is partly because >> vendors do not release enough information. Are there any modern devices >> for which this information *is* available? IOW, if I wanted to implement >> an open-source synthesis tool, which devices should I target? Again, >> recommendations would be greatly appreciated. > >I would venture to say that the primary road block to open-source >tools is that they are too dificult to support and keep current for >people to do for free. There are lots of flows for design entry and >simulation, and new devices are released on a weekly basis. I >occasionaly start using parts before they are released so I would not >be able to wait for open-source tools to have the support. In fact, I >have started designs where the vendors own tools didnt suport the part >I was using. It's a nice dream, but I doubt it will ever become a >reality. > >Mark ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Thu, 29 Nov 2001 22:58:55 -0500 Lines: 231 Message-ID: <3C0703FF.17F10E82@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYSuw4lc3m/1FgWCouqTrrC9xtxooMXDzUWhrNvz4Bp1bJSwacE9w4q X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 30 Nov 2001 03:58:17 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12020 This is likely not to be a fruitful debate. I think it has been hashed here before. But I will be happy to make another round of comments. :) Neil Franklin wrote: > > mrgs1000@yahoo.com (Mark) writes: > > > rickman wrote in message news:<3C065266.E43453F@yahoo.com>... > > > Neil Franklin wrote: > > > > > > > > Hint to vendors: if your part has open source support, it gets more > > > > recommendations ("take that one, it works"), and you get to sell more > > > > of them. I principially buy video and ethernet cards after consultion > > > > the on-line support databases. > > > > > > Designers don't EVER want to compromize their choice of chip based on > > > the tools. That would be more like vacationing in Newark because the bus > > > is cheaper than taking a plane to the Bahamas! > > Which quite a lot of people actually do. Select on price, that is, not > chose Newark. But that was my point. By having to settle for a chip that is not what the designer really wants or needs, he is taking a vacation in a place where he doesn't even want to be! The economies of FPGA sales (remember all of this is decided by the profit of the FPGA company, not the users!) says you cater to your large customers since they make up some 80 to 90% of your profit. > > > The idea that open source tool support will significantly impact the > > > sales of FPGA chips is weak at best. > > Short term they may not. Think long term: they pull in more beginners, > and so in time grow the population of FPGA developers, and so allow > firms to emply more and so make more FPA projects and that sells more > chips. That sounds great, but you missed the significance of my example below. If a high volume user can make $10 more profit on brand R than on brand P, he will not likely let the tools decide for him. Not with a volume of 100,000 or more units. He will churn the design and crack the whip on the engineers and get the design cranked out by hook or by crook. Let's face it, a million here and a million there and pretty soon you are counting real money :) The small volume customers don't count. The high volume customers will ALWAYS pick parts on price, not based on what the engineer LIKES to use. > > > chips in SPITE of the awful toolset they had to use. This was because > > > the chip was $10 cheaper than the other brand. It ended up costing them > > > a lot when they had to make revisions, but this was still the best > > > solution in terms of PROFIT!!! > > If you are at 100'000 or even 1 mio sized series, no doubt this > holds. But at 100 parts chip cost is not relevant. Tool support is. At 100 parts, the user is irrelevant. I don't mean to be mean. But I think both Xilinx and Altera do a pretty good job of supporting the small customer relative to the amount of profit they generate. Try getting Lucent (opps Agere) to chat with you about an annual volume of 100 pieces. HA! > > > > > and new devices are released on a weekly basis. I > > > > > > > > So that makes about 2 falimies per year industrywide to support. Or > > > > simply only support a few of them and only use those. > > > > > > But a familiy has some 10 different parts in it. > > And a Virtex CLB is a Virtex CLB, whether in XCV50, XCV1000 or XC2S200. Now you are showing that you have a lot to learn about the problem. I first heard about 10 years ago that the FPGA companies sell you routing and throw in the logic for FREE. The point is that way more than half the chip is routing. WAY, FAR more than half the software is about the ROUTING, not the CLB. I have written software in school to do logic minimization and such. The real trick is to efficiently place and route a part. This is not software you can write in your spare time. But I would be happy to be proven wrong... > > > Each of those parts has > > > many packages > > Inserting pin out tables is not that much work. > > > > and several speeds. Just getting the speed info (critical) > > > is not an easy problem to solve. Without vendor support, you would be > > > very hard pressed for anyone to trust your data. > > That may be important for the n*100MHz croud. Not everyone is playing > up there. Just all the potential sound processing applications, for > one, 48kHz anyone? 48 kHz x how many channels x how many filter taps etc. Not many designs DON"T push 100 MHz these days. Even at 50 MHz, you have to count your nS or you end up with a critical path that doesn't work when the die warms up to operating temp. > > > It certainly could be done, but the fact that it has not happened yet is > > > a good indicator that it is harder than you seem to believe. > > So long non-availability of information makes it impossible, any "not > happened" is 100% explained. Everything else remains speculation until > that barrier falls. Only a small part of the process is not documented. That would be the final step of generating the bit file. As has been pointed out here before, one of the smaller tasks in designing this sort of software would be reverse engineering the bit file format. If someone would sign up to writing a complete, end to end development system, I would happily spec the bit file for you! Just tell me which part. > > It’s actually even worse than that. Vendors are constantly > > re-characterizing the parts and re-releasing updated timing models for > > previously released parts. > > Again only relevant to the top speed crowd. You are talking about some 80 to 90% of the users, I would bet. > > This brings up another point, in addition to the place and route > > tools, you have to also provide the timing analysis tools. > > You know how many home/edu people overclock CPUs? Raise frequency until > crash, than drop by 10% is the sort of algorithm. It is "good enough" > for the target audience. Tell me again who is the target audience, hobbiest? > > It’s true that new families don’t get released often, but > > when they do, you have to practically throw out your place and route > > software because the architecture changes are too drastic. > > No different from the problems facing the gcc team when supporting > code generators for new processors. They are presently at well over > 20 architectures. And yes, some of the code generators suck. > > > doing hand placement for critical circuits. When I switched from > > Virtex E to Virtex II not only was all of my work in Virtex E > > worthless, it was a hindrance > > I doubt that "worthless". As ex-VirtexE-er you surely learned VirtexII > faster than someone with no experience in placing and so also no > knowledge what sort of pitfalls to look out for. Reuse of knowledge. We won't know for sure how complex this task is until someone trys to do it :) > > > > Does not look like you are an average user there. :-) > > > > > > Actually, I think he is a typical user. I think every place I have > > > worked has used beta versions of the chips at one time or another. > > > To be clearer, I am a typical Tier One user of FPGAs. Meaning that the > > companies I have worked for are high profile international accounts > > for the FPGA companies. > > Your critique may apply to the situation at top commercial facilities. > For home/edu (where I am) I would not expect that to be the case. I would be willing to bet that by the time you got the tools working for a single chip in a single speed grade in a single package, there will be two new families from that vendor. > > know that from a volume standpoint my group uses more FPGAs than any > > other group. > > Present usage. Think a bit further into the future. There are millions > of future developers out there. Presently they are playing around > designing websites. What are they going to go into professionally? > Websites. Now think if a few 10'000 of them were playing around with > FPGAs. Whom will they be presenting their workforce to in 5 years? They will use the parts that offer the best value, not the parts the offer the "coolest" tools. > > plentiful (no longer NDA) but this group would be limited and most > > likely restricted to hobbyists, students, and a few niche markets > > which have little competition. > > And that is already usefull. To the hobbyists! The students get tools for free (as in beer, not speech) or nearly so anyway. > > You can choose to debate this, however, the fact such tools > > don’t exist is pretty good support for my argument. > > Nope. Non-existance comes from non-information. Proof for your > argument will only be available after the information has been > available for some time and not being used. I think you have not really looked at the problem to be solved. As I said above, only the final bit file generation is not disclosed. That can be reverse engineered. So if anyone were serious about this, it could be attempted. > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer > - Intellectual Property is Intellectual Robbery Among your list of avocations do you include FPGA design? Before you get too excited about the tools, don't you think you should learn from what has happened to date? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Sender: hall@BOHOME Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> From: Kelly Hall Message-ID: Lines: 18 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 216.102.104.158 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr13.news.prodigy.com 1007102477 ST000 216.102.104.158 (Fri, 30 Nov 2001 01:41:17 EST) NNTP-Posting-Date: Fri, 30 Nov 2001 01:41:17 EST Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: [[OERXGDTBUKBFH[OZK@_TDAYZOZ@GXOXB_J]Q]KEYUNDQUCCNSUAACY@L[ZX__HGFD]JBJNSFXTOOGA_VWY^_HG@FW_HUTHOH]TBPGCO\P^PLP^@[GLHUK@WLECKFVL^TYG[@RMWQXIWM[SDDYWNLG_G[_BWUCHFY_Y@AS@Q[B\APPF@DCZM_PG_VSCPQZM Date: Fri, 30 Nov 2001 06:41:17 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newscon02.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr13.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11992 Neil Franklin writes: > That may be important for the n*100MHz croud. Not everyone is playing > up there. Just all the potential sound processing applications, for > one, 48kHz anyone? The vendors are giving away decent tools for the low-end FPGAs and CPLDs these days. No excuse for a hobbiest to not be able to make fun stuff in the basement for almost nothing beyond the part price anymore. But heck, if you really want to write an open source tool then go right ahead! How you spend your free time is up to you. Or were you merely complaining that there's no free tool for the newest parts? Kelly ###### From: Kees van Reeuwijk Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Fri, 30 Nov 2001 14:30:09 +0100 Organization: Delft University of Technology Lines: 18 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <3C05F855.D93ECC02@wanabe.nl> NNTP-Posting-Host: lon.pds.twi.tudelft.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tudelft.nl 1007126992 17327 130.161.157.242 (30 Nov 2001 13:29:52 GMT) X-Complaints-To: usenet@news.tudelft.nl NNTP-Posting-Date: Fri, 30 Nov 2001 13:29:52 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newsfeed.wirehub.nl!surfnet.nl!tudelft.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12015 On Thu, 29 Nov 2001 09:47:29 GMT, Reinoud wrote: >Kees van Reeuwijk wrote: >> I understand that the scarcity of such software is partly because >> vendors do not release enough information. > >Exactly. > >> Are there any modern devices for which this information *is* >> available? > >Not really, but there is a workaround (MPGA): > > http://ce.et.tudelft.nl/~reinoud/mpga/README.html Thanks for the pointer, but I'd rather try a non-virtual FPGA first. Neat idea, though :-) ###### From: Kees van Reeuwijk Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Fri, 30 Nov 2001 14:30:09 +0100 Organization: Delft University of Technology Lines: 26 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> NNTP-Posting-Host: lon.pds.twi.tudelft.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tudelft.nl 1007126992 17327 130.161.157.242 (30 Nov 2001 13:29:52 GMT) X-Complaints-To: usenet@news.tudelft.nl NNTP-Posting-Date: Fri, 30 Nov 2001 13:29:52 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!newsfeeds.belnet.be!news.belnet.be!surfnet.nl!tudelft.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12017 On 28 Nov 2001 19:37:56 +0100, Neil Franklin wrote: >P.S. to the @xilinx.com readers here: the often given reason for >bitstream secrecy was that the PROM->FPGA link allows it to be grabbed >and disassembled. With V2 the DES stuff was implemented to fix that >hole. Is there any chance that the V2 bitstream will one day be publically >(= non-NDA) documented? Perhaps an XAPP for those that want to know? Ah, at last a motivation for this secrecy. I have often wondered why they didn't document it. The best I could think of was to make cloning more difficult. >> IOW, if I wanted to implement >> an open-source synthesis tool, which devices should I target? Again, >> recommendations would be greatly appreciated. > >The nearest I have found is to use Virtex/Spartan-II. For these there >exists JBits. This is an API+library to modify/generate bitsreams. It >is totally low-level (individual CLB features), driven by Java code (so >usable to implement own CAE tools), free (as in beer, not as in speech), >not crippled (such as artificially slowed to make an payware version >attractive), written in Java (runs on Linux and BSD with Sun JDK). Thanks for the pointer. It sounds like the next best thing. ###### From: Kees van Reeuwijk Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Fri, 30 Nov 2001 14:30:10 +0100 Organization: Delft University of Technology Lines: 91 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> NNTP-Posting-Host: lon.pds.twi.tudelft.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tudelft.nl 1007126993 17327 130.161.157.242 (30 Nov 2001 13:29:53 GMT) X-Complaints-To: usenet@news.tudelft.nl NNTP-Posting-Date: Fri, 30 Nov 2001 13:29:53 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newscore.univie.ac.at!194.25.134.126.MISMATCH!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!newsfeeds.belnet.be!news.belnet.be!surfnet.nl!tudelft.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12014 On Thu, 29 Nov 2001 10:21:10 -0500, rickman wrote: >Neil Franklin wrote: >> >> mrgs1000@yahoo.com (Mark) writes: >> >> > Kees van Reeuwijk wrote in message news:<3fl90u >> k0l3mmebi1703urlud5e91rou5af@4ax.com>... >> > > >> > > I understand that the scarcity of such software is partly because >> > > vendors do not release enough information. Are there any modern devices >> > >> > I would venture to say that the primary road block to open-source >> > tools is that they are too dificult to support and keep current for >> > people to do for free. >> >> As opposed to tons of video and ethernet chips that the Linux people >> seem to have no great problem with? >> >> Just simply support those chips that members of the open source group >> use. And the software users then buy those parts. >> >> Hint to vendors: if your part has open source support, it gets more >> recommendations ("take that one, it works"), and you get to sell more >> of them. I principially buy video and ethernet cards after consultion >> the on-line support databases. > >I think this is where the analogy between standard hardware support >under a standard OS and FPGA support under a standard tool fails. >Designers don't EVER want to compromize their choice of chip based on >the tools. That would be more like vacationing in Newark because the bus >is cheaper than taking a plane to the Bahamas! > >The idea that open source tool support will significantly impact the >sales of FPGA chips is weak at best. The customers who buy lots of chips >from the FPGA vendors get free tools and often have an FAE parked in >their facility. I worked at one place where they still used brand Z >chips in SPITE of the awful toolset they had to use. This was because >the chip was $10 cheaper than the other brand. It ended up costing them >a lot when they had to make revisions, but this was still the best >solution in terms of PROFIT!!! (brand Z is not meant to be any >particular company!) Fair enough, for a volume application. However, if the FPGA is used for reconfigurable computing, the situation is different. I'm convinced that the first vendor with both a PCI FPGA board and an open-source toolset will become extremely popular in hacker circles. And who knows, it may even become popular in mainstream computing. The big FPGA vendors may not be interested in this market, but I'm surprised that none of the smaller ones has tried this. (Hint, hint :-) >> > There are lots of flows for design entry and >> > simulation, >> >> Just support those that the present maintainers use. And use those >> that are supported. >> >> > and new devices are released on a weekly basis. I >> >> Huh? As far as I see it Xilinx has so far created about 9 families >> (2000 3000 4000/Sparten 4000XL/SpartanXL 5200 6200 Virtex/SpartenII >> VirtexE/SpartanIIE Virtex2) in 15 years. Altera has 8 families >> (MAX3000 MAX7000 MAX9000 FLEX6K FLEX8K FLEX10K/ACEX APEX Mercury) >> in over 10 years. Lucent has IIRC 4 families of ORCA. Atmel 2 >> families (4000 6000). Actel I do not know, as I can not read their >> website (damn Flash and not HTML alternative). And a few other >> irrelevant manufacturers. >> >> So that makes about 2 falimies per year industrywide to support. Or >> simply only support a few of them and only use those. > >But a familiy has some 10 different parts in it. Each of those parts has >many packages and several speeds. Just getting the speed info (critical) >is not an easy problem to solve. Without vendor support, you would be >very hard pressed for anyone to trust your data. > >It certainly could be done, but the fact that it has not happened yet is >a good indicator that it is harder than you seem to believe. I consider timing info as just another part of the now-secret device programming info. However, for reconfigurable computing applications one *could* characterize each individual device and use that (with a safety margin, of course). ###### From: mrgs1000@yahoo.com (Mark) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 09:11:48 -0800 Organization: http://groups.google.com/ Lines: 126 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> NNTP-Posting-Host: 63.88.196.33 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1007140309 23091 127.0.0.1 (30 Nov 2001 17:11:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 30 Nov 2001 17:11:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!nntp-relay.ihug.net!ihug.co.nz!logbridge.uoregon.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12008 Parts of original thread sniped... > That sounds great, but you missed the significance of my example below. > If a high volume user can make $10 more profit on brand R than on brand > P, he will not likely let the tools decide for him. Not with a volume of > 100,000 or more units. He will churn the design and crack the whip on > the engineers and get the design cranked out by hook or by crook. Let's > face it, a million here and a million there and pretty soon you are > counting real money :) > > The small volume customers don't count. The high volume customers will > ALWAYS pick parts on price, not based on what the engineer LIKES to use. > Rick, you are doing a great job of helping me with this debate, but I can only partially agree here. My experience has been that the only time tools enter into the equation is if they are so buggy and slow that they hinder development. I have abandoned FPGA companies based on this. Aside from that, tools do not factor into my selection process at all. I pick an FPGA based on performance and features first (product performance is more important than cost), familiarity with architecture second (this impacts development time, and therefore time to market), and price 3rd (once you have met the customer requirements, and hit the market window, then you want to increase profit margin). Our difference here is do the fact that I work in telecom on large systems with low volumes and 2 year design cycles. I suspect your product is much more commercial, much higher volume. > > > > And a Virtex CLB is a Virtex CLB, whether in XCV50, XCV1000 or XC2S200. > > Now you are showing that you have a lot to learn about the problem. I > first heard about 10 years ago that the FPGA companies sell you routing > and throw in the logic for FREE. The point is that way more than half > the chip is routing. WAY, FAR more than half the software is about the > ROUTING, not the CLB. I have written software in school to do logic > minimization and such. The real trick is to efficiently place and route > a part. This is not software you can write in your spare time. But I > would be happy to be proven wrong... > In the old days, FPGAs were much simpler. They consisted of a perfectly symmetrical array of identical logic blocks. That is not true anymore. The complexity of these devices has gone up exponentially. CLBs are only a fraction of the issue. Routing is becoming much more complex also. > > That may be important for the n*100MHz croud. Not everyone is playing > > up there. Just all the potential sound processing applications, for > > one, 48kHz anyone? > The only case where timing is not critical is if no one else is using your design...meaning it is just your personal toy. A few levels of logic, and a bad placement can break a 25MHz design in the fastest Virtex E. > > > > It certainly could be done, but the fact that it has not happened yet is > > > > a good indicator that it is harder than you seem to believe. > > > > So long non-availability of information makes it impossible, any "not > > happened" is 100% explained. Everything else remains speculation until > > that barrier falls. > > Only a small part of the process is not documented. That would be the > final step of generating the bit file. As has been pointed out here > before, one of the smaller tasks in designing this sort of software > would be reverse engineering the bit file format. If someone would sign > up to writing a complete, end to end development system, I would happily > spec the bit file for you! Just tell me which part. > Exactly, it is all there, you just have to dig a little. I would add that if you are not good enough to reverse engineer the bit file format, you are not good enough to do the PAR. However, I think Xilinx will give you that also. > > > > It’s actually even worse than that. Vendors are constantly > > > re-characterizing the parts and re-releasing updated timing models for > > > previously released parts. > > > > Again only relevant to the top speed crowd. > > You are talking about some 80 to 90% of the users, I would bet. > > > > > This brings up another point, in addition to the place and route > > > tools, you have to also provide the timing analysis tools. > > > > You know how many home/edu people overclock CPUs? Raise frequency until > > crash, than drop by 10% is the sort of algorithm. It is "good enough" > > for the target audience. > Again, timing is always important, unless you are not an engineer, or you are one those sorry engineers whose designs I have had to fix over and over again, both pre-release and post-release. > > > > It’s true that new families don’t get released often, but > > > when they do, you have to practically throw out your place and route > > > software because the architecture changes are too drastic. > > > > No different from the problems facing the gcc team when supporting > > code generators for new processors. They are presently at well over > > 20 architectures. And yes, some of the code generators suck. > > > > > doing hand placement for critical circuits. When I switched from > > > Virtex E to Virtex II not only was all of my work in Virtex E > > > worthless, it was a hindrance > > > > I doubt that "worthless". As ex-VirtexE-er you surely learned VirtexII > > faster than someone with no experience in placing and so also no > > knowledge what sort of pitfalls to look out for. Reuse of knowledge. > Believe me you don’t do multiple several hundred thousand gate FPGAs without understanding the concept of design reuse. Hard macros fix placement and routing so they are not compatible between families. CLBs, Slices, routing switch boxes, routing channels, CLB orientation, switch box orientation, IOBs, IOB switch boxes...are all different between VirtexE and Virtex II. In addition a few design strategies that helped me VirtexE actually hurt me in Virtex II. I couldnt make progress until I abandoned my old way of thinking. Was it as bad as switching to Altera, no, but it was bad. ###### From: mrgs1000@yahoo.com (Mark) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 11:10:06 -0800 Organization: http://groups.google.com/ Lines: 109 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> NNTP-Posting-Host: 63.88.196.33 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1007147406 25321 127.0.0.1 (30 Nov 2001 19:10:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 30 Nov 2001 19:10:06 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!news-hog.berkeley.edu!ucberkeley!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12011 Kees van Reeuwijk wrote in message news:... > On Thu, 29 Nov 2001 10:21:10 -0500, rickman > wrote: > > >Neil Franklin wrote: > >> > >> mrgs1000@yahoo.com (Mark) writes: > >> > >> > Kees van Reeuwijk wrote in message news:<3fl90u > k0l3mmebi1703urlud5e91rou5af@4ax.com>... > >> > > > >> > > I understand that the scarcity of such software is partly because > >> > > vendors do not release enough information. Are there any modern devices > >> > > >> > I would venture to say that the primary road block to open-source > >> > tools is that they are too dificult to support and keep current for > >> > people to do for free. > >> > >> As opposed to tons of video and ethernet chips that the Linux people > >> seem to have no great problem with? > >> > >> Just simply support those chips that members of the open source group > >> use. And the software users then buy those parts. > >> > >> Hint to vendors: if your part has open source support, it gets more > >> recommendations ("take that one, it works"), and you get to sell more > >> of them. I principially buy video and ethernet cards after consultion > >> the on-line support databases. > > > >I think this is where the analogy between standard hardware support > >under a standard OS and FPGA support under a standard tool fails. > >Designers don't EVER want to compromize their choice of chip based on > >the tools. That would be more like vacationing in Newark because the bus > >is cheaper than taking a plane to the Bahamas! > > > >The idea that open source tool support will significantly impact the > >sales of FPGA chips is weak at best. The customers who buy lots of chips > >from the FPGA vendors get free tools and often have an FAE parked in > >their facility. I worked at one place where they still used brand Z > >chips in SPITE of the awful toolset they had to use. This was because > >the chip was $10 cheaper than the other brand. It ended up costing them > >a lot when they had to make revisions, but this was still the best > >solution in terms of PROFIT!!! (brand Z is not meant to be any > >particular company!) > > > Fair enough, for a volume application. > > However, if the FPGA is used for reconfigurable computing, the situation > is different. I'm convinced that the first vendor with both a PCI FPGA > board and an open-source toolset will become extremely popular in hacker > circles. And who knows, it may even become popular in mainstream > computing. > > The big FPGA vendors may not be interested in this market, but I'm > surprised that none of the smaller ones has tried this. (Hint, hint :-) > PCI FPGA cards exist already from 3rd parties. FPGA vendors suck at board design. You don’t want them doing it themselves. Why does the toolset need to be open source for reconfigurable computing? People are doing this now with existing tools. > >> > There are lots of flows for design entry and > >> > simulation, > >> > >> Just support those that the present maintainers use. And use those > >> that are supported. > >> > >> > and new devices are released on a weekly basis. I > >> > >> Huh? As far as I see it Xilinx has so far created about 9 families > >> (2000 3000 4000/Sparten 4000XL/SpartanXL 5200 6200 Virtex/SpartenII > >> VirtexE/SpartanIIE Virtex2) in 15 years. Altera has 8 families > >> (MAX3000 MAX7000 MAX9000 FLEX6K FLEX8K FLEX10K/ACEX APEX Mercury) > >> in over 10 years. Lucent has IIRC 4 families of ORCA. Atmel 2 > >> families (4000 6000). Actel I do not know, as I can not read their > >> website (damn Flash and not HTML alternative). And a few other > >> irrelevant manufacturers. > >> > >> So that makes about 2 falimies per year industrywide to support. Or > >> simply only support a few of them and only use those. > > > >But a familiy has some 10 different parts in it. Each of those parts has > >many packages and several speeds. Just getting the speed info (critical) > >is not an easy problem to solve. Without vendor support, you would be > >very hard pressed for anyone to trust your data. > > > >It certainly could be done, but the fact that it has not happened yet is > >a good indicator that it is harder than you seem to believe. > > I consider timing info as just another part of the now-secret device > programming info. > > However, for reconfigurable computing applications one *could* > characterize each individual device and use that (with a safety margin, > of course). Dude, there is no secret conspiracy, search the archives, the info is out there. Vendors just dont make it easy to find because they dont want to have to support it. If you think it is such a good idea, then go write it yourself. I have no doubt that I could do it, and if I become independantly wealthy I just might. In the mean time, I gota devote most of my time to paying the bills. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 21:51:11 +0100 Organization: My own Private Self Lines: 100 Message-ID: <6u7ks89e4g.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007153471 456 10.0.3.2 (30 Nov 2001 20:51:11 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 30 Nov 2001 20:51:11 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12021 rickman writes: > Neil Franklin wrote: > > > > > > The idea that open source tool support will significantly impact the > > > > sales of FPGA chips is weak at best. > > > > Short term they may not. Think long term: they pull in more beginners, > > and so in time grow the population of FPGA developers, and so allow > > firms to emply more and so make more FPA projects and that sells more > > chips. > > That sounds great, but you missed the significance of my example below. > If a high volume user can make $10 more profit on brand R than on brand High volume yes. But beginners are not high volume. > The small volume customers don't count. The high volume customers will At present. But they are the source that tomorrows high volume people come from. So why hinder them? It is not as if publishing the formats were an large expensive to avoid. > > > > But a familiy has some 10 different parts in it. > > > > And a Virtex CLB is a Virtex CLB, whether in XCV50, XCV1000 or XC2S200. > > Now you are showing that you have a lot to learn about the problem. I > first heard about 10 years ago that the FPGA companies sell you routing > and throw in the logic for FREE. The point is that way more than half > the chip is routing. That is well known here. For Virtex one CLB has 18x48=864 config bits of which well over 700 are routing PIPs according to the JBits docs. So that makes ca 80% routing, as far as config volume goes. > minimization and such. The real trick is to efficiently place and route > a part. This is not software you can write in your spare time. Well, as I am hand routing every single LUT/FF (JBits requires that), so that part is not foreign to me. As for routing, I have not tried that (using JRoute), but it looks doable. > > So long non-availability of information makes it impossible, any "not > > happened" is 100% explained. Everything else remains speculation until > > that barrier falls. > > Only a small part of the process is not documented. That would be the > final step of generating the bit file. As has been pointed out here > before, one of the smaller tasks in designing this sort of software > would be reverse engineering the bit file format. Perhaps I will have to try it. But having official docs from the horses mouth would be a lot better. > If someone would sign > up to writing a complete, end to end development system, Sorry, no chance here. More likely the typical open-source piecemeal production of the next part I (or other participants) want to use. > > > This brings up another point, in addition to the place and route > > > tools, you have to also provide the timing analysis tools. > > > > You know how many home/edu people overclock CPUs? Raise frequency until > > crash, than drop by 10% is the sort of algorithm. It is "good enough" > > for the target audience. > > Tell me again who is the target audience, hobbiest? If I do something definitely, as I am a hobbyist. But there again Linux also started as hobbyist project. It grew out of it. > > Nope. Non-existance comes from non-information. Proof for your > > argument will only be available after the information has been > > available for some time and not being used. > > I think you have not really looked at the problem to be solved. As I > said above, only the final bit file generation is not disclosed. That > can be reverse engineered. So if anyone were serious about this, it > could be attempted. I think it will be. FPGAs are just entering the spotlight of hackers. They are about where microprocessors were 1975. I expect the next 5 years to be similarly furious as the 75-80 was for micros. And yes that is a prediction, we will see if it turns out. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 22:08:53 +0100 Organization: My own Private Self Lines: 48 Message-ID: <6u4rnc9day.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007154533 465 10.0.3.2 (30 Nov 2001 21:08:53 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 30 Nov 2001 21:08:53 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12022 Kelly Hall writes: > The vendors are giving away decent tools for the low-end FPGAs and > CPLDs these days. Sort of. As far any closed-source tool they can not be user-extended can be called decent. > No excuse for a hobbiest to not be able to make fun > stuff in the basement for almost nothing beyond the part price > anymore. > > Or were you merely complaining that there's no free tool for the > newest parts? Open source is not about free as in free beer. It is about free as in no limitations, as in being able to take any idea and realise it, subject only to ones own limits such as skill or time limits. Not being limited by externally imposed limits such as vendor tools OS/language platform selection, and only those features which interest enough users getting the vendor to allocate programmers to them, etc. Just look at the millions who are fleeing the (payed for with the PC) Microsoft OSes to Linux or BSD. That is not about cost (you pay anyway, unless you belong to the few who put together their own PCs). It is about getting software that was made by users, for themselves, with their understanding of what it should do and what has priority to them. As opposed to some vendors marketing department and project managments ideas of what is profitable for the vendor. And people who are used to such software regard vendor-make tools as clunky. So they would prefer open source ones. It is about a large amount of user-brains being better than an small amount of vendor-brains. Same thing as with science vs dogma a few 100 years ago. And yes, such ideas are new to most people, and like anything new they look strange. Until you get used to them, and then they become obvious. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 30 Nov 2001 22:17:02 +0100 Organization: My own Private Self Lines: 44 Message-ID: <6u1yig9cxd.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007155022 465 10.0.3.2 (30 Nov 2001 21:17:02 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 30 Nov 2001 21:17:02 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12023 Kees van Reeuwijk writes: > On 28 Nov 2001 19:37:56 +0100, Neil Franklin > wrote: > > >P.S. to the @xilinx.com readers here: the often given reason for > >bitstream secrecy was that the PROM->FPGA link allows it to be grabbed > > Ah, at last a motivation for this secrecy. Note: that is an somewhat widely spread speculation. I am not aware of an official pronounciation. Problem with above it that anti-fuse FPGA and EEPROM CPLD makers also do not publish, and above does not apply to them. > they didn't document it. The best I could think of was to make cloning > more difficult. Anyone willing to clone, read: set up an manufacturing and sales process, will definitely not be stopped by reverse engineering. For that sort of stopping competition there exists patent law. Third motivation could be cost of documenting. But I do not regard that as large enough to be noticable. So the motivation question is really still open. Anyone @xilinx.com who wants to comment of this? > >The nearest I have found is to use Virtex/Spartan-II. For these there > >exists JBits. This is an API+library to modify/generate bitsreams. It > > Thanks for the pointer. It sounds like the next best thing. At least I manged to help someone with this thread. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Message-ID: <3C082473.549DFA7B@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 202.138.29.23 Lines: 34 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Sat, 01 Dec 2001 11:29:39 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1007166546 203.134.67.67 (Sat, 01 Dec 2001 11:29:06 EST) NNTP-Posting-Date: Sat, 01 Dec 2001 11:29:06 EST Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:12031 Neil Franklin wrote: > > rickman writes: > > > Neil Franklin wrote: > > > > > > > > The idea that open source tool support will significantly impact the > > > > > sales of FPGA chips is weak at best. > > > > > > Short term they may not. Think long term: they pull in more beginners, > > > and so in time grow the population of FPGA developers, and so allow > > > firms to emply more and so make more FPA projects and that sells more > > > chips. > > > > That sounds great, but you missed the significance of my example below. > > If a high volume user can make $10 more profit on brand R than on brand > > High volume yes. But beginners are not high volume. > > > The small volume customers don't count. The high volume customers will > > At present. But they are the source that tomorrows high volume people > come from. So why hinder them? It is not as if publishing the formats > were an large expensive to avoid. I was engineering in analog/rf, and got interested in doing dsp in fpgas a couple of years ago (before web-packs etc). After being p*ssed off by brand @$#! vendors because i wanted cheap/free tools to learn, i went with brand A. Haven't regretted since. Acex devices are wonderful for doing the dsp that i'm doing, and there's no hassles with hand-routing etc. I'll only use X now if there's a very compelling reason, as there's no point in learning new tools when the ones i'm using work ok. ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 1 Dec 2001 01:42:33 GMT Organization: California Institute of Technology, Pasadena Lines: 32 Message-ID: <9u9ci9$q78@gap.cco.caltech.edu> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> NNTP-Posting-Host: yak.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:12032 Peter Alfke writes: >This is a recurring subject, so the answers are also recurring. >We do not encourage or support open-source place-and-route tools >for a variety of reasons. The strongest is: >We understand the difficulty of the task ( believe me, we do! ), >and we do not want to be dragged into a support quagmire. >Since we sell the devices, our users will inevitably demand support >from us, and we cannot provide that for an unlimited number of >homebrew solutions. >We have put many hundreds of man-years into the development of >these tools, and we are (now) proud of their performance. >We are not afraid of competition from smart hackers, we just >know that they will never be able to generate a comprehensive >quality solution and keep up with the fast-paced FPGA development. >No matter how smart they are. And we cannot afford to clean >up after them. The big computer companies could have said the same thing about OS development not so many years ago, and now we have Linux being supported on IBM mainframes. Many companies are now seeing the advantages of open-source software. Linux users know where to go for support and where not to go. I do agree that you must tell people early where their support will come from, and where it won't. -- glen ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sat, 01 Dec 2001 05:01:24 -0500 Lines: 53 Message-ID: <3C08AA74.93C694E1@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVYgG7W8/fMKZMbYbp3YKe3URnULK4nxMMfQDntgcrXG+lgP+5/ArCx2 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Dec 2001 10:00:23 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12028 Mark wrote: > > Parts of original thread sniped... > > The small volume customers don't count. The high volume customers will > > ALWAYS pick parts on price, not based on what the engineer LIKES to use. > > > > Rick, you are doing a great job of helping me with this debate, but I > can only partially agree here. My experience has been that the only > time tools enter into the equation is if they are so buggy and slow > that they hinder development. I have abandoned FPGA companies based on > this. Aside from that, tools do not factor into my selection process > at all. I pick an FPGA based on performance and features first > (product performance is more important than cost), familiarity with > architecture second (this impacts development time, and therefore time > to market), and price 3rd (once you have met the customer > requirements, and hit the market window, then you want to increase > profit margin). Our difference here is do the fact that I work in > telecom on large systems with low volumes and 2 year design cycles. I > suspect your product is much more commercial, much higher volume. Interesting. I made my comments based on the one experience I had with a large company. They make telecom test equipment and have moderately low volumes and design cycles around 6 months to a year (if all goes well). They were very concerned with price. They would do all their designs in HDL without using any unique features of one FPGA brand just so they could "threaten" to switch if they didn't get the price they wanted. When this was explained to me, the example presented did not ring true, but that was their position. Price was very important on most of their products. Of course, functionality had priority. On an OC-192 design they could not get the job done with one brand, so they got raped on price by the other one that worked. I would hazard that they were being a bit overly concerned with price given their volumes. Your approach sounds closer to the optimum to me. But regardless, that is what they are doing and that is what we were talking about. They spend the money and the FPGA vendors market to get that money. Tools are secondary to functionality and price (not necessarily in that order). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sat, 01 Dec 2001 05:17:55 -0500 Lines: 103 Message-ID: <3C08AE53.E1539122@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbbr7u81HdIFu8DeGqbD3HACMO8BGO6cpklcKjgqWjpktm+XkU5bIUf X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Dec 2001 10:16:55 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12042 Neil Franklin wrote: > > rickman writes: > > > Neil Franklin wrote: > > > > > > > > The idea that open source tool support will significantly impact the > > > > > sales of FPGA chips is weak at best. > > > > > > Short term they may not. Think long term: they pull in more beginners, > > > and so in time grow the population of FPGA developers, and so allow > > > firms to emply more and so make more FPA projects and that sells more > > > chips. > > > > That sounds great, but you missed the significance of my example below. > > If a high volume user can make $10 more profit on brand R than on brand > > High volume yes. But beginners are not high volume. > > > The small volume customers don't count. The high volume customers will > > At present. But they are the source that tomorrows high volume people > come from. So why hinder them? It is not as if publishing the formats > were an large expensive to avoid. You are completely missing my point. If you start as a low volume user and move to a company that spends BIG bucks on FPGAs, your approach to FPGA selection and design will change to match the model of the BIG company. You could have been a loyal Ralph's FPGAs customer for the last 5 years, but when you start working at Cisco, you will quickly find that you are going to use Smucker's FPGAs if there is any significant difference to the price/performance. It will not matter a hoot what open source tools you used prior. > > and throw in the logic for FREE. The point is that way more than half > > the chip is routing. > > That is well known here. For Virtex one CLB has 18x48=864 config bits > of which well over 700 are routing PIPs according to the JBits docs. > So that makes ca 80% routing, as far as config volume goes. The point is that this is where the work is in designing the software. I have seen some of the crappy stuff that was passing for place and route awhile back. If it was easy, any FGPA company could have done it. Instead it took them years to even get good at doing their OWN parts. > > minimization and such. The real trick is to efficiently place and route > > a part. This is not software you can write in your spare time. > > Well, as I am hand routing every single LUT/FF (JBits requires that), > so that part is not foreign to me. As for routing, I have not tried > that (using JRoute), but it looks doable. Hand routing is not a program. I can see much more clearly than the computer can and I just started wearing Bifocals, yuck! > Perhaps I will have to try it. But having official docs from the horses > mouth would be a lot better. Please let us know how it goes. JBITs should isolate you from the bit file format issue, no? > > I think you have not really looked at the problem to be solved. As I > > said above, only the final bit file generation is not disclosed. That > > can be reverse engineered. So if anyone were serious about this, it > > could be attempted. > > I think it will be. FPGAs are just entering the spotlight of > hackers. They are about where microprocessors were 1975. I expect the > next 5 years to be similarly furious as the 75-80 was for micros. > > And yes that is a prediction, we will see if it turns out. If you want to do something useful, find a way to support design for partial reconfiguration. As it stands, the last several generations of Xilinx, Lucent, Atmel and perhaps Altera chips have all supported partial reconfiguration. This lets you download just part of an FPGA without affecting the rest. But there is no design software to partition or map your design to the "sections" that will be downloaded. The last board I did needed four FPGAs so that I could load each one with different designs based on the environment found at boot time. I could save a lot of bucks on the next design if I could use one large FPGA and use partial reconfiguration for this same result. A lot of people have suggested that I take a look at JBITs, but I would still have to do all the mapping/partitioning myself. Way too much work. Care to take a look at this? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sat, 01 Dec 2001 05:26:11 -0500 Lines: 41 Message-ID: <3C08B043.539CADFE@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C082473.549DFA7B@iprimus.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVaTF9x2/HqP07jiHs4bxQ8nUE9upNDcUxoG2ZMep1VtWdBEWrVGyG8U X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Dec 2001 10:25:10 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12029 Russell Shaw wrote: > I was engineering in analog/rf, and got interested in doing dsp in fpgas > a couple of years ago (before web-packs etc). After being p*ssed off > by brand @$#! vendors because i wanted cheap/free tools to learn, i went > with brand A. Haven't regretted since. Acex devices are wonderful for > doing the dsp that i'm doing, and there's no hassles with hand-routing > etc. I'll only use X now if there's a very compelling reason, as there's > no point in learning new tools when the ones i'm using work ok. As long as you are mentioning names, I had a very bad experience with brand A in my last design. We had to use about 80% of the chip and found that we could not trust the timing analyzer to give us good data. It was hard enough to meet our target of 80 MHz, but when we DID meet that number in the analyzer and tested on the bench at temperature, we found that the design failed badly, sometimes even at room temp. This was not a logic error, but a timing failure. We chased this so hard that I learned way more about running the tools than I ever wanted to know. It delayed the project schedule by about 3 months as well. The bottom line was that the MaxPlus+II tool appears to be fataly broken. The last I heard, you had to use MaxPlus+II for ACEX designs. Is that still true? Or is ACEX supported by the (non free?) Quartus tools now? I took a hard look at ACEX parts. They don't have the startup current limitation that Spartan II parts do and the price is right. But I am not using that @$#! MaxPlus+II tool again! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Sender: hall@BOHOME Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> From: Kelly Hall User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Message-ID: Lines: 50 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 216.102.104.158 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr14.news.prodigy.com 1007206900 ST000 216.102.104.158 (Sat, 01 Dec 2001 06:41:40 EST) NNTP-Posting-Date: Sat, 01 Dec 2001 06:41:40 EST Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: OP[IBZCEYBUS@^LYMRKNOPDA[X_LPO@FKYYDMREK@YWZUYUBK^RAAEW[QDZ\YQ_IT^C_[EVLDV^NOMOBFFTINWDGGFTKX_DHE@[DRVKC^DQPPOD^HKAHIP[CODFMKGJNYDYIZCZLPI_UWEGS@D^W^B_^J[Y^G\KHBYZC@ESAY[FDPVPEGDA^M]@D]VT_QQVL Date: Sat, 01 Dec 2001 11:41:40 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cyclone2.usenetserver.com!usenetserver.com!newscon06.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr14.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12030 Neil Franklin writes: > Kelly Hall writes: > > > The vendors are giving away decent tools for the low-end FPGAs and > > CPLDs these days. > > Sort of. As far any closed-source tool they can not be user-extended > can be called decent. No argument from me. But my primary concern is finding cheap/free software to support my configurable hardware hobby. I don't care whether the software I don't pay for is free because the part vendor gives it away or because some geeks decided to write some EDA tool in their spare time. I just want to download my HDL into some chip. Although vendor supplied tools are not user-extendable, they seem to work pretty well. Certainly they are better than the open-source alternatives at this point in time. > Open source is not about free as in free beer. It is about free as in > no limitations, as in being able to take any idea and realise it, > subject only to ones own limits such as skill or time limits. It seems to me that you want open-source software for configurable hardware for some political or philosophical agenda. Personally, I want free software for configurable hardware to be able to write VHDL and Verilog and AHDL and ABEL for my small projects at home. If there was no free software for this purpose, I'd find some other project to work on, or return to designing circuits out of 74xx series ICs and PALs. Your needs are sufficient to satisfy my needs, but not necessary to satisfy mine. I wonder if the open-source versus vendor-supplied argument as applied to EDA tools mirrors the situation with professional-quality machinist tools. It's certainly annoying that a good quality Bridgeport milling machine is too expensive for me to put in my garage; and yet, I've worked a several companies that have purchased them and not given it a second thought. Any mill I can afford to own myself is of much lower quality than the Bridgeport. There are several published designs for making your own milling machine at home for little or no cost; however, the quality is highly inferior to that of high- or mid-range commercial equipment. Are you annoyed that high-end EDA tools cost so much, or that the open-source tools are so inferior to the commercial ones? Kelly ###### From: Nial Stewart Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sat, 01 Dec 2001 12:12:48 +0000 Organization: Agilent Lines: 17 Message-ID: <3C08C940.F973010@britain.agilent.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C082473.549DFA7B@iprimus.com.au> <3C08B043.539CADFE@yahoo.com> Reply-To: nials@britain.agilent.com NNTP-Posting-Host: emperor.labs.agilent.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: cswtrans.cos.agilent.com 1007208770 24872 130.29.252.172 (1 Dec 2001 12:12:50 GMT) X-Complaints-To: usenet@cswtrans.cos.agilent.com NNTP-Posting-Date: Sat, 1 Dec 2001 12:12:50 +0000 (UTC) X-Mailer: Mozilla 4.76 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en Cache-Post-Path: emperor.labs.agilent.com!nials@hpqt0797.britain.agilent.com X-Cache: nntpcache 2.4.0b5 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!agilent.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12036 rickman wrote: > > The bottom line was that the MaxPlus+II tool appears to be fataly > broken. The last I heard, you had to use MaxPlus+II for ACEX designs. I've never liked Maxplus2 much, I never really got the feeling that I had control of what's going on, but then I never had to push any designs _really_ hard with it. > Or is ACEX supported by the (non free?) Quartus tools > now? Yes, and it seems a much better tool. Nial. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 01 Dec 2001 19:49:38 +0100 Organization: My own Private Self Lines: 113 Message-ID: <6ug06uai7x.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007232578 598 10.0.3.2 (1 Dec 2001 18:49:38 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 1 Dec 2001 18:49:38 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12043 rickman writes: > Neil Franklin wrote: > > > > rickman writes: > > > > > The small volume customers don't count. The high volume customers will > > > > At present. But they are the source that tomorrows high volume people > > come from. So why hinder them? It is not as if publishing the formats > > were an large expensive to avoid. > > You are completely missing my point. If you start as a low volume user > and move to a company that spends BIG bucks on FPGAs, your approach to > FPGA selection and design will change to match the model of the BIG > company. You could have been a loyal Ralph's FPGAs customer for the last If one goes to an big-user company, yes. I suppose I should describe the stuff I am doing a bit: I am presently working on using FPGAs for cloning historic/EOLed computer architectures. My intention is at some time (perhaps in 2 years) to design an generic FPGA-PC board (that is, an PC motherboard format, uses PC case and power, has standard PC interface connectors and RAM sockets, but FPGA instead of CPU), that will run mine and anyone elses system clones. Should allow any user to just get an board, plug in RAM, put in case, add HD, connect peripherals, download an compiled design, run. A bit like standard PC hardware running multiple OSes. So such a design will end up with quite a large amount of sold boards (and so FPGA chips), but sold to many different users/groups/teams, who will each be designing an different design to run on it. Of course such a system will require any user who wants to take part in one of the designs to get the tools. That will be a large amount of users entering the FPGA place. And each teams founder will be free to chose what tools they want for their individual design. So no Cisco dictates "our standard tool". There are actually a few FPGA CPU and SoC projects, but all seem to be using prototyping boards and then hand-wiring IO. So a standard board could be quite successfull. And have the advantage that one can buy one board and then use multiple designs on it, saving space and cost. http://neil.franklin.ch/Projects/PDP-10/Hardware And no, that is not the traditional FPGA user. But it is going to be part of the FPGA future. PCs were not the traditional microprocessor user in 1975 either, before the microcomputer revolution started. > > Well, as I am hand routing every single LUT/FF (JBits requires that), > > so that part is not foreign to me. As for routing, I have not tried > > that (using JRoute), but it looks doable. > > Hand routing is not a program. But good enough for me. And if someone else wants more, it is open source, user expandable, so they can add that. > > Perhaps I will have to try it. But having official docs from the horses > > mouth would be a lot better. > > Please let us know how it goes. JBITs should isolate you from the bit > file format issue, no? So long I stay with JBits. But it has some drawbacks I would like to be able to avoid. Java being one of them. > > I think it will be. FPGAs are just entering the spotlight of > > hackers. They are about where microprocessors were 1975. I expect the > > next 5 years to be similarly furious as the 75-80 was for micros. > > > > And yes that is a prediction, we will see if it turns out. > > If you want to do something useful, find a way to support design for > partial reconfiguration. Not of much use to me, at present, as I am aiming for an fixed board spec. First learn to walk, then to run. > As it stands, the last several generations of > Xilinx, Lucent, Atmel and perhaps Altera chips have all supported > partial reconfiguration. This lets you download just part of an FPGA > without affecting the rest. Yup. With Virtex single config frames (of which 48 give an column of CLBs). > save a lot of bucks on the next design if I could use one large FPGA and > use partial reconfiguration for this same result. Sounds like it would. > suggested that I take a look at JBITs, but I would still have to do all > the mapping/partitioning myself. Way too much work. For an commercial outfit that could be a problem. > Care to take a look at this? Is not on my forseeable path. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 01 Dec 2001 20:03:41 +0100 Organization: My own Private Self Lines: 69 Message-ID: <6ud71yahki.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007233421 607 10.0.3.2 (1 Dec 2001 19:03:41 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 1 Dec 2001 19:03:41 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12044 Kelly Hall writes: > Neil Franklin writes: > > > Sort of. As far any closed-source tool they can not be user-extended > > can be called decent. > > No argument from me. But my primary concern is finding cheap/free > software to support my configurable hardware hobby. I don't care > > > Open source is not about free as in free beer. It is about free as in > > no limitations, as in being able to take any idea and realise it, > > subject only to ones own limits such as skill or time limits. > > It seems to me that you want open-source software for configurable > hardware for some political or philosophical agenda. More philosophical. I just prefer being unlimited. > want free software for configurable hardware to be able to write VHDL > and Verilog and AHDL and ABEL for my small projects at home. Which is what I (for forseeable future) will be doing. > was no free software for this purpose, I'd find some other project to > work on, or return to designing circuits out of 74xx series ICs and > PALs. There is one difference. I want to do this project I have (computer system cloning), which requires either an FPGA or lots of space/cost using small chips. > I wonder if the open-source versus vendor-supplied argument as applied > to EDA tools mirrors the situation with professional-quality machinist > tools. It's certainly annoying that a good quality Bridgeport milling > machine is too expensive for me to put in my garage; Difference here: the Bridgeport has an high per-issue (manufacturing) cost, making hardware consists of mining/shaping/assembling atoms, that just is expensive. An open source EDA tool can grow in time (may be 10 or more years, Linux OS took 10, the Linux GUIs are not quite there at 5 years) to be professional quality, without having any per-issue costs (as download = replication). That is what makes open source capable of working: reproduction is free, cost is only authoring cost, which is what make professional EDA tools expensive, and open source slow to grow. > Are you annoyed that high-end EDA tools cost so much, No, they have authors to pay. Let those pay them, who want their tools. > or that the > open-source tools are so inferior to the commercial ones? Problem presently is not inferior, but simply non existant. Once they start they will grow. Linux was also primitive when I entered it, 6 years ago. I can put up with primitive tools. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sat, 01 Dec 2001 13:40:56 -0500 Lines: 46 Message-ID: <3C092438.41BD78D9@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C082473.549DFA7B@iprimus.com.au> <3C08B043.539CADFE@yahoo.com> <3C08C940.F973010@britain.agilent.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVbsurOaLeiPA+z8yRCIfyEhI7RAEu53eHC+5qu9ejklEgTBImwzXDxD X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 1 Dec 2001 18:39:49 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12062 Nial Stewart wrote: > > rickman wrote: > > > > > The bottom line was that the MaxPlus+II tool appears to be fataly > > broken. The last I heard, you had to use MaxPlus+II for ACEX designs. > > I've never liked Maxplus2 much, I never really got the feeling that > I had control of what's going on, but then I never had to push any > designs _really_ hard with it. > > > Or is ACEX supported by the (non free?) Quartus tools > > now? > > Yes, and it seems a much better tool. > > Nial. I learned a few things about the tools and software. The tools don't really show you the routing. They just give you a rat's nest of here to there. The 10K chip architecture is supposed to give you predictable delays via a heirarchy of routing. But when push comes to shove, if "you can't get there from here, go somewhere else first and start from there". I think this is what prevented the chip from meeting timing both in analysis and even when we passed analysis, it would fail in temperature testing. ACEX is supported by the paid Quartus tools, but oddly enough, not in the free version. You HAVE to use the MaxPlus+II Baseline if you want free ACEX tools. Too bad. ACEX would be a good solution to the Spartan II startup current problem. :( But I need for my customers to be able to get free tools that work. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 01 Dec 2001 13:48:47 -0800 Message-ID: Lines: 14 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 1 Dec 2001 13:52:34 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!TELOCITY!enews.sgi.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:12057 Neil Franklin writes: > So such a design will end up with quite a large amount of sold boards > (and so FPGA chips), but sold to many different users/groups/teams, who > will each be designing an different design to run on it. Maybe a thousand of them if you're really lucky. But even 10,000 isn't enough to attract the attention of an FPGA vendor, given what the support cost would be. I don't like it either, but it's a fact. If there was a real market for FPGAs with documented bitstreams, there would be a company selling into that market. As I recall, Xilinx actually did try that, and it apparently wasn't sufficiently successful. ###### Message-ID: <3C096929.6FABA57E@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C082473.549DFA7B@iprimus.com.au> <3C08B043.539CADFE@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.118.115 Lines: 41 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Sun, 02 Dec 2001 10:35:05 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1007249706 203.134.67.67 (Sun, 02 Dec 2001 10:35:06 EST) NNTP-Posting-Date: Sun, 02 Dec 2001 10:35:06 EST Organization: iPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:12051 rickman wrote: > > Russell Shaw wrote: > > I was engineering in analog/rf, and got interested in doing dsp in fpgas > > a couple of years ago (before web-packs etc). After being p*ssed off > > by brand @$#! vendors because i wanted cheap/free tools to learn, i went > > with brand A. Haven't regretted since. Acex devices are wonderful for > > doing the dsp that i'm doing, and there's no hassles with hand-routing > > etc. I'll only use X now if there's a very compelling reason, as there's > > no point in learning new tools when the ones i'm using work ok. > > As long as you are mentioning names, I had a very bad experience with > brand A in my last design. We had to use about 80% of the chip and found > that we could not trust the timing analyzer to give us good data. It was > hard enough to meet our target of 80 MHz, but when we DID meet that > number in the analyzer and tested on the bench at temperature, we found > that the design failed badly, sometimes even at room temp. This was not > a logic error, but a timing failure. We chased this so hard that I > learned way more about running the tools than I ever wanted to know. It > delayed the project schedule by about 3 months as well. > > The bottom line was that the MaxPlus+II tool appears to be fataly > broken. The last I heard, you had to use MaxPlus+II for ACEX designs. Is > that still true? Or is ACEX supported by the (non free?) Quartus tools > now? > > I took a hard look at ACEX parts. They don't have the startup current > limitation that Spartan II parts do and the price is right. But I am not > using that @$#! MaxPlus+II tool again! Luckily, my main use of cplds doesn't involve complicated protocol shuffling, so i develop using crash-and-burn (or burn-and crash?) procedure by testing with an oscilloscope after adding onto or modifying the code. The speeds are way slower than the device, and i make sure the vhdl is clean, invoking lpm blocks where possible. I've always got more done using crash-and-burn, than spending hours getting the same things to work in a simulator (hard to interact with external hardware in a vhdl simulator). I've got up to 80% EAB usage, and 40% LC usage so far. ###### Sender: hall@BOHOME Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> <6ud71yahki.fsf@chonsp.franklin.ch> From: Kelly Hall Message-ID: Lines: 25 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 216.102.104.158 X-Complaints-To: abuse@prodigy.net X-Trace: newssvr21.news.prodigy.com 1007252029 ST000 216.102.104.158 (Sat, 01 Dec 2001 19:13:49 EST) NNTP-Posting-Date: Sat, 01 Dec 2001 19:13:49 EST Organization: Prodigy Internet http://www.prodigy.com X-UserInfo1: Q[RGW[SD]JVKBPH]^JKBOW@@YJ_ZTB\MV@BZMVMHQAVTUZ]CLNTCPFK[WDXDHV[K^FCGJCJLPF_D_NCC@FUG^Q\DINVAXSLIFXYJSSCCALP@PB@\OS@BITWAH\CQZKJMMD^SJA^NXA\GVLSRBD^M_NW_F[YLVTWIGAXAQBOATKBBQRXECDFDMQ\DZFUE@\JM Date: Sun, 02 Dec 2001 00:13:49 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!207.115.63.138!newscon04.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com!postmaster.news.prodigy.com!newssvr21.news.prodigy.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12052 Neil Franklin writes: > More philosophical. I just prefer being unlimited. Who doesn't? Today, you are limited by the reality of no useful open-source EDA tools being available anywhere. There are some excellent closed-source EDA tools available, though, and you can obtain them at costs ranging from free to tens of thousands of dollars. > > or that the > > open-source tools are so inferior to the commercial ones? > > Problem presently is not inferior, but simply non existant. > Once they start they will grow. Linux was also primitive when I > entered it, 6 years ago. I can put up with primitive tools. Sounds like a nice idea - it will be interesting to see if it pans out. So far it hasn't, and FPGAs and open-source aren't exactly brand new ideas. I don't mind primitive tools if there's nothing else available. Today, there are excellent tools available that don't cost much. Kelly ###### Message-ID: <3C098B96.897B01CE@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> <6ud71yahki.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 27 Date: Sun, 02 Dec 2001 02:02:12 GMT NNTP-Posting-Host: 209.179.193.91 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1007258532 209.179.193.91 (Sat, 01 Dec 2001 18:02:12 PST) NNTP-Posting-Date: Sat, 01 Dec 2001 18:02:12 PST Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Sat, 01 Dec 2001 18:02:13 PST (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!howland.erols.net!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12049 Neil Franklin wrote: > An open source EDA tool can grow in time (may > be 10 or more years, Linux OS took 10, the Linux GUIs are not quite > there at 5 years) to be professional quality, without having any > per-issue costs (as download = replication). > > That is what makes open source capable of working: reproduction is > free, cost is only authoring cost, which is what make professional > EDA tools expensive, and open source slow to grow. Maybe this is the root cause of our difference of opinion: 5 years is an eternity in this industry. Today, you would (should!) not even consider starting a design with parts that everybody hailed as the newest and greatest just 5 years ago ( XC4000XL, any takers? ) Of course these parts stay in production for many more years, but they are no match for the newer generations. I have publicly used the analogy that 1 year in the evolution of FPGAs is equivalent to 15 years in the aging of a human being. A 4-year old FPGA is like a 60-year old human, competent, but not up to the most demanding assignments. We use Moore's law to come up with ever better, faster, more capable, and effectively much cheaper devices, and the tools have to hang onto ( or lead ) that pace... Peter Alfke ###### Message-ID: <3C098C04.DB45E5B5@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> <6ud71yahki.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 35 Date: Sun, 02 Dec 2001 02:03:50 GMT NNTP-Posting-Host: 209.179.193.91 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1007258630 209.179.193.91 (Sat, 01 Dec 2001 18:03:50 PST) NNTP-Posting-Date: Sat, 01 Dec 2001 18:03:50 PST Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Sat, 01 Dec 2001 18:03:51 PST (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!netnews.com!xfer02.netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12050 Neil Franklin wrote: > An open source EDA tool can grow in time (may > be 10 or more years, Linux OS took 10, the Linux GUIs are not quite > there at 5 years) to be professional quality, without having any > per-issue costs (as download = replication). > > That is what makes open source capable of working: reproduction is > free, cost is only authoring cost, which is what make professional > EDA tools expensive, and open source slow to grow. Maybe this is the root cause of our difference of opinion: 5 years is an eternity in this industry. Today, you would (should!) not even consider starting a design with parts that everybody hailed as the newest and greatest just 5 years ago ( XC4000XL, any takers? ) Of course these parts stay in production for many more years, but they are no match for the newer generations. I have publicly used the analogy that 1 year in the evolution of FPGAs is equivalent to 15 years in the aging of a human being. A 4-year old FPGA is like a 60-year old human, competent, but not up to the most demanding assignments. We use Moore's law to come up with ever better, faster, more capable, and effectively much cheaper devices, and the tools have to hang onto ( or lead ) that pace... Peter Alfke ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 00:59:50 -0500 Lines: 120 Message-ID: <3C09C356.E168EB72@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVadFDhHHi8iLJBKL8UVmlrHsjfWXQvh6zh/vtl1WQUkbUxWbGTcxcps X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Dec 2001 05:59:20 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!feed2.onemain.com!feed1.onemain.com!feed1.newsreader.com!netnews.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12045 Neil Franklin wrote: > I suppose I should describe the stuff I am doing a bit: I am presently > working on using FPGAs for cloning historic/EOLed computer architectures. > My intention is at some time (perhaps in 2 years) to design an generic > FPGA-PC board (that is, an PC motherboard format, uses PC case and power, > has standard PC interface connectors and RAM sockets, but FPGA instead > of CPU), that will run mine and anyone elses system clones. Should allow > any user to just get an board, plug in RAM, put in case, add HD, connect > peripherals, download an compiled design, run. A bit like > standard PC hardware running multiple OSes. > > So such a design will end up with quite a large amount of sold boards > (and so FPGA chips), but sold to many different users/groups/teams, who > will each be designing an different design to run on it. > > Of course such a system will require any user who wants to take part > in one of the designs to get the tools. That will be a large amount of > users entering the FPGA place. And each teams founder will be free to > chose what tools they want for their individual design. So no Cisco > dictates "our standard tool". > > There are actually a few FPGA CPU and SoC projects, but all seem to be > using prototyping boards and then hand-wiring IO. So a standard board > could be quite successfull. And have the advantage that one can buy > one board and then use multiple designs on it, saving space and cost. To the best of my knowledge, there is not much demand for an FPGA based SOC. The main purpose of SOC is to allow complex embedded systems to made at low cost. Doing it on an FPGA will not keep the cost down. There may be some advantage to having a "universal" hardware platform for initial development, but I think you have vastly overestimated the market for the FPGA motherboard you are describing. As you have defined it, it would be a PC that runs slower, requires that you put massive effort into NRE and will likely cost much more than a top end PC. FPGAs of any size are much more expensive than a PC CPU. Unless the user needs to solve a very special purpose application, there will be no performance gain. Ask Ray A. As far as I am aware, most if not all of his designs run at very high processing rates that Intel would envy. But they are specially designed to solve only one problem. Even if you have a "universal" hardware platform, you still only have a small target audience with problems that can't be done on standard hardware. Besides, having a "standard" board will be limited by the standard. Many applications that need FPGA horsepower have little or no need for PCI or other PC busses, they are just too slow. Earlier this year I bid on a DSP application using a small (but pricey) FPGA to do FFTs at a rate that was difficult in DSP chips. But the added NRE of the FPGA development made me the high bidder. FPGAs are typically used for processing where nothing else will work, not because they are inherently cheap to build. Hey, if users wanted to do processing on FPGAs, they would be buying some of my DSP boards by the droves. My boards have Flash, fast SRAM and IO which can all be controlled by the FPGA if you want. "Just" design your own downloads! I will even leave the DSP off the board if you want to save $50 on the price. > http://neil.franklin.ch/Projects/PDP-10/Hardware > > And no, that is not the traditional FPGA user. But it is going to be > part of the FPGA future. PCs were not the traditional microprocessor > user in 1975 either, before the microcomputer revolution started. > > > > Well, as I am hand routing every single LUT/FF (JBits requires that), > > > so that part is not foreign to me. As for routing, I have not tried > > > that (using JRoute), but it looks doable. > > > > Hand routing is not a program. > > But good enough for me. And if someone else wants more, it is open > source, user expandable, so they can add that. I think this is where we are missing each other. You are asking for open source tools. If you don't need routing, then you can write what you need for everything but the bit file generation which is given to you. So where is the problem? > > > Perhaps I will have to try it. But having official docs from the horses > > > mouth would be a lot better. > > > > Please let us know how it goes. JBITs should isolate you from the bit > > file format issue, no? > > So long I stay with JBits. But it has some drawbacks I would like to > be able to avoid. Java being one of them. If this is the only drawback, then let me know and I will be happy to suppliment your tools with my open source bit file generator. That will be the easy part. I don't want to rain on your parade, but we have heard from posters here before about open source tools. But it is a bit like the weather, everybody talks about it... It sounds to me like your real application is the design of a universal FPGA based motherboard. This does not require the use of open source tools. I suggest that you consider your real goal and find the best path to it. Now that I think about it, you can build what you want without designing a mother board. Many PCs still support the Slot 1 (or is it Slot A?) architecture. You can design a Slot 1 module that interfaces to a standard PC motherboard as if it were a Pentium (or Athlon), have a bus to memory etc. at up to 266 MHz, and not have to deal with any of the groady stuff like emulating the North or South bridges. You even get to control the power voltage from the module! Sounds like the simple approach to me! :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 01:03:37 -0500 Lines: 43 Message-ID: <3C09C439.793E95F9@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <6u4rnc9day.fsf@chonsp.franklin.ch> <6ud71yahki.fsf@chonsp.franklin.ch> <3C098B96.897B01CE@earthlink.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZRBNUILgI5aIh1eX2qRdsuIoRryelq6Jxi4QK5AgGfSbuMnVEn4cMK X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Dec 2001 06:03:05 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12046 Peter Alfke wrote: > > Neil Franklin wrote: > > > An open source EDA tool can grow in time (may > > be 10 or more years, Linux OS took 10, the Linux GUIs are not quite > > there at 5 years) to be professional quality, without having any > > per-issue costs (as download = replication). > > > > That is what makes open source capable of working: reproduction is > > free, cost is only authoring cost, which is what make professional > > EDA tools expensive, and open source slow to grow. > > Maybe this is the root cause of our difference of opinion: > 5 years is an eternity in this industry. Today, you would (should!) not even > consider starting a design with parts that everybody hailed as the newest > and greatest just 5 years ago ( XC4000XL, any takers? ) > Of course these parts stay in production for many more years, but they are > no match for the newer generations. I have publicly used the analogy that 1 > year in the evolution of FPGAs is equivalent to 15 years in the aging of a > human being. A 4-year old FPGA is like a 60-year old human, competent, but > not up to the most demanding assignments. Peter, you should be careful in your analogies... ;) > We use Moore's law to come up with ever better, faster, more capable, and > effectively much cheaper devices, and the tools have to hang onto ( or lead > ) that pace... > Peter Alfke -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> From: hamish@cloud.net.au Subject: Re: Is there a full open-source synthesis path for any FPGA? Newsgroups: comp.arch.fpga References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> User-Agent: tin/1.5.8-20010221 ("Blue Water") (UNIX) (Linux/2.2.18 (i586)) Date: 02 Dec 2001 10:29:43 GMT Lines: 30 NNTP-Posting-Host: 203.164.66.244 X-Trace: 1007288983 19497 203.164.66.244 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!logbridge.uoregon.edu!newsfeed.dacom.co.kr!intgwlon.nntp.telstra.net!news1.optus.net.au!optus!spool01.syd.optusnet.com.au!spool.optusnet.com.au!210.49.20.119.MISMATCH!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12060 Peter Alfke wrote: > We have put many hundreds of man-years into the development of these tools, and > we are (now) proud of their performance. We are not afraid of competition from > smart hackers, we just know that they will never be able to generate a > comprehensive quality solution and keep up with the fast-paced FPGA development. > No matter how smart they are. And we cannot afford to clean up after them. > My opinion, yours may differ... (My opinion (only) follows. You touched a raw nerve of mine here.) Keeping up with the hardware is difficult, yes. But I wouldn't be so bold as to say that open source developers will _never_ be able to produce a comprehensive, quality solution. A few years ago you may have said the same about operating systems, but look where Linux is now. So after Linux became popular, people said that there would never be a good graphical desktop for it because that wasn't something hackers were interested in, but two such desktops now exist (KDE and GNOME). On the subject of Linux, let me put you on the spot Peter :-) and ask you when Xilinx will get serious about Linux. EDA tools for Linux are already available from Synplicity, Synopsys, Mentor/ModelTech and others. Apart from Xilinx tools (and perhaps ClearCase), I could work all day on Linux now. regards, Hamish -- Hamish Moffatt VK3SB ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 02 Dec 2001 16:56:07 +0100 Organization: My own Private Self Lines: 116 Message-ID: <6uitbp4nvs.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007308567 707 10.0.3.2 (2 Dec 2001 15:56:07 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Dec 2001 15:56:07 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12063 rickman writes: > Neil Franklin wrote: > > working on using FPGAs for cloning historic/EOLed computer architectures. > > SOC. The main purpose of SOC is to allow complex embedded systems to > made at low cost. Traditional use of SoCs yes. > Doing it on an FPGA will not keep the cost down. A lot cheaper (and a lot less work per copy) than using 100s or 1000s of 74xx(x) plus needed board/case/powersupply. Not to mention assembly costs. > may be some advantage to having a "universal" hardware platform for > initial development, but I think you have vastly overestimated the > market for the FPGA motherboard you are describing. There exists lots of people who can download an bitfile (if download tools are provided with it. Quite a few that can learn coding. And far less are prepared to go ordering/assembling parts and wiring them. Look at the ratio of homebrew vs premade (altair, apple) computers around 1975/6/7. > As you have defined > it, it would be a PC that runs slower, requires that you put massive > effort into NRE and will likely cost much more than a top end PC. Note the "historic/EOLed" in my above text. Implementing 386/later in FPGA would be inferior (by about 6 years) to Intels current offerings. But for systems that are EOLed, i.e. not buyable unless you try to get one second hand, FPGA SoC can be very cheap. And the originals are seldom (few made, many lost), large, guzzle electricity, require cooling, break down often, no spares. > FPGAs of any size are much more expensive than a PC CPU. Yes, but easier to get than something not any more existant. > > So long I stay with JBits. But it has some drawbacks I would like to > > be able to avoid. Java being one of them. > > If this is the only drawback, Nope. Just the the one that came to mind yesterday evening. There are others: no Virtex-E (faster and cheaper) support, can not be freely copied (give copy to every user who wants one), bug I run into (small but annoying) has not got enough priority to have Xilinx fix it (with o s I could fix it), etc. Just the typical mix of small stuff that adds up to make any closed source frustrating to anyone who has once tasted the fruits of open source. > then let me know and I will be happy to > suppliment your tools with my open source bit file generator. That will > be the easy part. Well if it is easy, I can do it myself :-). > I don't want to rain on your parade, but we have heard from posters here > before about open source tools. But it is a bit like the weather, > everybody talks about it... So it was also with OSes until Linux happend. EDA tools will happen. Just give them time. > It sounds to me like your real application > is the design of a universal FPGA based motherboard. Presently my real application is my design for running on such an board (and being developed on an normal prototype board). Custom board will follow after, to let more users use the design with less hassle. > Now that I think about it, you can build what you want without designing > a mother board. Many PCs still support the Slot 1 (or is it Slot A?) > architecture. Slot 1 is Intel, Slot A is AMD. Implementing any chip or circuit using Slot 1 signalling is illegal per patent law. Intel ist just at the moment active at suing VIA for doing that (making an chipset for P4 motherboards). > standard PC motherboard as if it were a Pentium (or Athlon), have a bus They seem to be all 32/64bit, which is a bad match for 36/72bit stuff. > to memory etc. at up to 266 MHz, and not have to deal with any of the > groady stuff like emulating the North or South bridges. Directly drive SDRAM off of the FPGA. There exist XAPPs on that. > You even get to > control the power voltage from the module! Sounds like the simple > approach to me! :) More hassle than use, IMHO. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 12:38:09 -0500 Lines: 61 Message-ID: <3C0A6701.B481DEEB@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVakBuzAFmDdC8kGSFxi0fOlzUrTC8aJWfaeh/pLLuikNBcWWO1pBrUk X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Dec 2001 17:37:37 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12065 hamish@cloud.net.au wrote: > > Peter Alfke wrote: > > We have put many hundreds of man-years into the development of these tools, and > > we are (now) proud of their performance. We are not afraid of competition from > > smart hackers, we just know that they will never be able to generate a > > comprehensive quality solution and keep up with the fast-paced FPGA development. > > No matter how smart they are. And we cannot afford to clean up after them. > > > My opinion, yours may differ... > > (My opinion (only) follows. You touched a raw nerve of mine here.) > > Keeping up with the hardware is difficult, yes. But I wouldn't be so bold > as to say that open source developers will _never_ be able to produce > a comprehensive, quality solution. A few years ago you may have said > the same about operating systems, but look where Linux is now. So > after Linux became popular, people said that there would never be > a good graphical desktop for it because that wasn't something hackers > were interested in, but two such desktops now exist (KDE and GNOME). > > On the subject of Linux, let me put you on the spot Peter :-) and > ask you when Xilinx will get serious about Linux. EDA tools for > Linux are already available from Synplicity, Synopsys, Mentor/ModelTech > and others. Apart from Xilinx tools (and perhaps ClearCase), I could > work all day on Linux now. > > regards, > Hamish > -- > Hamish Moffatt VK3SB We keep hearing about how Linux is a great example of how open source tools are practical. But the two problems are so different. Designing and maintaining an OS or even a compiler is much less impacted by the base product changes than would be FPGA development tools. If I understand these tools correctly, the changes required to port from a Pentium III to an Athlon or a P4 are minimal. But consider the changes required to port a P&R tool between the XC4000 family and an Altera APEX20K!!! Perhaps I am overstating the problem. But so far we are only talking about it (every six months or so). Until someone makes an effort and writes such a tool, we will never know. I believe there are some open source efforts to write front end tools for HDLs. This is very comparible to the stuff being done in the OS domain. How many of us are using these tools? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 12:41:59 -0500 Lines: 50 Message-ID: <3C0A67E7.26F5C460@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZibAaXzF+t1MNrEg8RuEKpBIxFph3+iD9k1aX2R4Tp11tmV86drQ/4 X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Dec 2001 17:41:26 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!43758!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12064 hamish@cloud.net.au wrote: > > Peter Alfke wrote: > > We have put many hundreds of man-years into the development of these tools, and > > we are (now) proud of their performance. We are not afraid of competition from > > smart hackers, we just know that they will never be able to generate a > > comprehensive quality solution and keep up with the fast-paced FPGA development. > > No matter how smart they are. And we cannot afford to clean up after them. > > > My opinion, yours may differ... > > (My opinion (only) follows. You touched a raw nerve of mine here.) > > Keeping up with the hardware is difficult, yes. But I wouldn't be so bold > as to say that open source developers will _never_ be able to produce > a comprehensive, quality solution. A few years ago you may have said > the same about operating systems, but look where Linux is now. So > after Linux became popular, people said that there would never be > a good graphical desktop for it because that wasn't something hackers > were interested in, but two such desktops now exist (KDE and GNOME). > > On the subject of Linux, let me put you on the spot Peter :-) and > ask you when Xilinx will get serious about Linux. EDA tools for > Linux are already available from Synplicity, Synopsys, Mentor/ModelTech > and others. Apart from Xilinx tools (and perhaps ClearCase), I could > work all day on Linux now. > > regards, > Hamish > -- > Hamish Moffatt VK3SB I forgot to mention that I second the vote to use Linux for EDA. I currently have to deal with Windows crashes some 3 or 4 times a day with some of the software I am using. I may be at the point of wanting to start over and reinstall Windows from scratch. I just wish I had a second option. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 12:57:04 -0500 Lines: 86 Message-ID: <3C0A6B70.2D17BD9@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVa69dleo0HLKIJiWN6ajcQmC+b88M6LODy+r9IvhhAxtexciDdegCOy X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 2 Dec 2001 17:56:33 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12070 Neil Franklin wrote: > > rickman writes: > > then let me know and I will be happy to > > suppliment your tools with my open source bit file generator. That will > > be the easy part. > > Well if it is easy, I can do it myself :-). Well then, end of discussion. Let us know when you are done. I would be interested in seeing how it went. > > I don't want to rain on your parade, but we have heard from posters here > > before about open source tools. But it is a bit like the weather, > > everybody talks about it... > > So it was also with OSes until Linux happend. EDA tools will happen. > Just give them time. Just give who time? I thought YOU were going to do it? > > Now that I think about it, you can build what you want without designing > > a mother board. Many PCs still support the Slot 1 (or is it Slot A?) > > architecture. > > Slot 1 is Intel, Slot A is AMD. Implementing any chip or circuit using > Slot 1 signalling is illegal per patent law. Intel ist just at the > moment active at suing VIA for doing that (making an chipset for P4 > motherboards). And Via has a defence of having bought a company that HAS a licence for this. I don't know why Intel thinks this is not valid. Mostly it is chest thumping and an effort to scare off the Via customers. Your boards would most likely be flying under Intel's radar. I don't think they would spend the money to take you to court for using their patents to emulate a PDP-10. > > standard PC motherboard as if it were a Pentium (or Athlon), have a bus > > They seem to be all 32/64bit, which is a bad match for 36/72bit stuff. Just curious, who would want an emulation of EOL'd computers and how large is the market? Also don't you have the same issues with emulating a VAX instruction set as duplicating the Slot I interface? > > to memory etc. at up to 266 MHz, and not have to deal with any of the > > groady stuff like emulating the North or South bridges. > > Directly drive SDRAM off of the FPGA. There exist XAPPs on that. That is what is done on the North Bridge. The CPU interface runs at the speed of the SDRAM and the North Bridge is just electrical/arbitration to connect the two. It also matches speed to the other high speed busses such as AGP. But if you want, you can bring this inside the FPGA. But this is more work. My point was to try to minimize the work to get SOMETHING out sooner. But then I think in terms of commerciallizing things, not as a hobbiest. > > You even get to > > control the power voltage from the module! Sounds like the simple > > approach to me! :) > > More hassle than use, IMHO. Didn't you see the grin? Good luck with your project. Let us know how it goes!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 02 Dec 2001 22:30:51 +0100 Organization: My own Private Self Lines: 119 Message-ID: <6uelmd48dw.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> <3C0A6B70.2D17BD9@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007328651 987 10.0.3.2 (2 Dec 2001 21:30:51 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 2 Dec 2001 21:30:51 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12071 rickman writes: > Neil Franklin wrote: > > > > rickman writes: > > > then let me know and I will be happy to > > > suppliment your tools with my open source bit file generator. That will > > > be the easy part. > > > > Well if it is easy, I can do it myself :-). > > Well then, end of discussion. Let us know when you are done. I would be > interested in seeing how it went. Will take a bit of time. But I will sure report it here. > > > I don't want to rain on your parade, but we have heard from posters here > > > before about open source tools. But it is a bit like the weather, > > > everybody talks about it... > > > > So it was also with OSes until Linux happend. EDA tools will happen. > > Just give them time. > > Just give who time? I thought YOU were going to do it? Oops s/them/us/. Like in all open source I will be one of multiple doing it. > > Slot 1 is Intel, Slot A is AMD. Implementing any chip or circuit using > > Slot 1 signalling is illegal per patent law. Intel ist just at the > > moment active at suing VIA for doing that (making an chipset for P4 > > motherboards). > > And Via has a defence of having bought a company that HAS a licence for > this. Ah? I never heard that bit. Most likely the journalist I read did not either. Good news. I rather like VIA (this computer and my previous one have/had their chipsets). > I don't know why Intel thinks this is not valid. Mostly it is > chest thumping and an effort to scare off the Via customers. Could be. They have got a reputation of using dirty tricks. > would most likely be flying under Intel's radar. I don't think they > would spend the money to take you to court for using their patents to > emulate a PDP-10. Most likely. I am peanuts for them. :-) > > > standard PC motherboard as if it were a Pentium (or Athlon), have a bus > > > > They seem to be all 32/64bit, which is a bad match for 36/72bit stuff. > > Just curious, who would want an emulation of EOL'd computers Because todays commercially available choice of systems (PC/Windows, Mac/MacOS, PC-or-Mac/Linux-or-BSD) is not exactly large. There exist quite a few old systems which I and others would like to revive and add new featires and see what we can make out of them. Think of it as experimenting in alternative evolutions. > large is the market? I expect about 10 systems times each 1000-3000 machines. > Also don't you have the same issues with emulating > a VAX instruction set as duplicating the Slot I interface? Instruction sets are not patentable (not even copyrightable). A few sets are not implementable without breaking patents on particular features (MIPS non aligned data handling instructions come to mind, dito PDP-11 instruction pointer as last arithmetic register), but most have no such limits, or the patents have recieved their 17 year death. No trouble there. > > > to memory etc. at up to 266 MHz, and not have to deal with any of the > > > groady stuff like emulating the North or South bridges. > > > such as AGP. But if you want, you can bring this inside the FPGA. But > this is more work. My point was to try to minimize the work to get > SOMETHING out sooner. But then I think in terms of commerciallizing > things, not as a hobbiest. My method to save time is to actually have no bus at all. Rather SDRAM sockets and set of standard IO connectors driven directly (or with only a bit of analog stuff between) from the FPGA. "Bus" is only internal, longlines or even user multiplexers. Also gives maximal flexibility to different architectures. > > > You even get to > > > control the power voltage from the module! Sounds like the simple > > > approach to me! :) > > > > More hassle than use, IMHO. > > Didn't you see the grin? I overlooked it. > Good luck with your project. Let us know how it goes!!! I will. Promise. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Message-ID: <3C0A9157.699E3FD8@gornall.net> From: Simon Gornall Organization: Me, Myself, and I X-Mailer: Mozilla 4.78 [en] (X11; U; Linux 2.4.8-26mdk i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 98 Date: Sun, 02 Dec 2001 20:38:47 +0000 NNTP-Posting-Host: 213.121.101.88 X-Trace: NewsReader 1007327407 213.121.101.88 (Sun, 02 Dec 2001 21:10:07 GMT) NNTP-Posting-Date: Sun, 02 Dec 2001 21:10:07 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!dispose.news.demon.net!demon!btnet-peer0!btnet-feed5!btnet!NewsPeer!Fusion!NewsReader.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12079 rickman wrote: > > We keep hearing about how Linux is a great example of how open source > tools are practical. But the two problems are so different. Designing > and maintaining an OS or even a compiler is much less impacted by the > base product changes than would be FPGA development tools. If I > understand these tools correctly, the changes required to port from a > Pentium III to an Athlon or a P4 are minimal. But consider the changes > required to port a P&R tool between the XC4000 family and an Altera > APEX20K!!! You may or may not be correct in your general view, but the above argument is not sufficiently valid to help your point. Comparing the (P3 -> P4 or Athlon changes) vs the (XC4000 -> Apex20k changes) is comparing apples to oranges. A better illustration would be that Gcc can compile code for a wider variety of architecture types: ix86, avr (8-bit micro), arm (branch predication within most instructions), i860, hp 9000 'Snakes' mips rx000, ppc, m68k, m88k, ns32k, sparc (windowed regs), vax(!), etc. Not only does it cope with lots of weirdo architectures, each with their own best-way of doing things, but it does it well, in a well- defined manner (machine descriptions). It defines a many-one-many architecture for the source-intermediate-object states which allowed it to become both truly portable and an automatic cross- compiler. GNU then developed the gnu super-optimiser. This is a tool that tries every way the compiler can code basic ops, given the machine description of a new machine type, and the best compiled code ends up as a template for the compiler. So: o It handles lots of (very) different architecture types o It optimises the operations for each architecture o It is completely open o It is (on some platforms) better than the vendor's compiler I would say the compiler analogy is a pretty good one, as far as it goes. Substitute FPGA families for machines and resource descriptions (CLBs, carry chains, blockrams, long paths, 4-luts, 3-luts etc.) for machine descriptions and I think it clicks into place quite well. I also think it'd be a very hard project to undertake. It would take a braver man than I to say it would be "impossible" or "will never happen" though... > Perhaps I am overstating the problem. But so far we are only talking > about it (every six months or so). Until someone makes an effort and > writes such a tool, we will never know. I believe there are some open > source efforts to write front end tools for HDLs. This is very > comparible to the stuff being done in the OS domain. How many of us are > using these tools? One could look at: http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html http://www.eecg.toronto.edu/~vaughn/vpr/e64.html (routing images) as a darn good start. I mailed the guy who wrote the package about a year ago though, and he said specifying the 'resource descriptions' as I refer to them above is by far the hardest problem, because of course you have to specify the constraints under which the resources operate as well as the method by which you instantiate the constraint on the resource. FPGA's are the new 80's PC's ---------------------------- I do feel there is some merit in the statement that FPGA's are now at the point where PC's were at 15 years ago. I would have never thought I could design my own CPU at home, on a PC. Now though, it's pretty darn cheap, and the effort-level isn't that high to start getting results. I'm (painfully :-) aware that the black voodoo that all you experts know (about the internals of the CLB's etc) is required to squeeze the very last performance out of an FPGA, but I have a 32-bit CPU running at 50MHz+ in a spartan-2 which I'm quite proud of for a first project :-)) I have a (much more ambitious) longer-term project in mind, which (if I ever finish it) will be quite a useful little device in my industry. Perhaps even commercially viable, although that's a loong way away. My point is that I can play and learn, whereas 2 years ago, I would have (a) not tried, and (b) paid a fortune for a dedicated piece of hardware to do the same job... All my designs will use Xilinx parts, because they're cheap to work with (Thankyou BurchEd :-) and the s/w is downloadable. I would *really* like to not have to reboot into Win2k to run the tools though - in fact the main obstacle to the development of my "project" is that my Linux box is usually busy doing things, and I don't want to interrupt it to play on the FPGA stuff. Guess I should buy another computer ... ATB, Simon. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 23:15:41 -0500 Lines: 171 Message-ID: <3C0AFC6D.521298D0@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVa7lQldZU+qqAsDR6V3s7fgeaqeqPlyxyDptFlFYoCDnK2PCYeZY2BL X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 3 Dec 2001 04:15:10 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!cpk-news-hub1.bbnplanet.com!news.gtei.net!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12072 Simon Gornall wrote: > > rickman wrote: > > > > We keep hearing about how Linux is a great example of how open source > > tools are practical. But the two problems are so different. Designing > > and maintaining an OS or even a compiler is much less impacted by the > > base product changes than would be FPGA development tools. If I > > understand these tools correctly, the changes required to port from a > > Pentium III to an Athlon or a P4 are minimal. But consider the changes > > required to port a P&R tool between the XC4000 family and an Altera > > APEX20K!!! > > You may or may not be correct in your general view, but the above > argument is not sufficiently valid to help your point. Comparing > the (P3 -> P4 or Athlon changes) vs the (XC4000 -> Apex20k changes) > is comparing apples to oranges. > > A better illustration would be that Gcc can compile code for a > wider variety of architecture types: ix86, avr (8-bit micro), arm > (branch predication within most instructions), i860, hp 9000 'Snakes' > mips rx000, ppc, m68k, m88k, ns32k, sparc (windowed regs), vax(!), > etc. > > Not only does it cope with lots of weirdo architectures, each with > their own best-way of doing things, but it does it well, in a well- > defined manner (machine descriptions). It defines a many-one-many > architecture for the source-intermediate-object states which > allowed it to become both truly portable and an automatic cross- > compiler. > > GNU then developed the gnu super-optimiser. This is a tool that > tries every way the compiler can code basic ops, given the machine > description of a new machine type, and the best compiled code ends > up as a template for the compiler. > > So: > o It handles lots of (very) different architecture types > o It optimises the operations for each architecture > o It is completely open > o It is (on some platforms) better than the vendor's compiler > > I would say the compiler analogy is a pretty good one, as far as it > goes. Substitute FPGA families for machines and resource descriptions > (CLBs, carry chains, blockrams, long paths, 4-luts, 3-luts etc.) > for machine descriptions and I think it clicks into place quite well. > > I also think it'd be a very hard project to undertake. It would take a > braver man than I to say it would be "impossible" or "will never happen" > though... That may all be true. But I still maintain that place and route software is inherently more complex than complilers. The tasks required to convert C language instructions to machine code for a given, well defined architecture is conceptually straight forward and well understood by nearly anyone graduating with a computer science degree. On the other hand, place and route algorithms are in a class of problems known as NP complete if my schooling has not failed me (or my memory). This means essentially that you can NEVER deterministically find the best solution to the problem for a realistic application given the state of technology in the foreseeable future. At least this is true until we are using Quantum computing which can explore all solution sets simultaneously. The difference in problem statment means that the algorithms for solving them and the means of developing them are very, very different. The suboptimal solution hunt will always require custom algorithms and special tuning that are far more device specific than what is done to write a code optimizer for a processor. You obviously understand compliers pretty well. But what do you know about designing place and route software? I don't profess to be an expert, but this is a very different animal than writing a compiler. > > Perhaps I am overstating the problem. But so far we are only talking > > about it (every six months or so). Until someone makes an effort and > > writes such a tool, we will never know. I believe there are some open > > source efforts to write front end tools for HDLs. This is very > > comparible to the stuff being done in the OS domain. How many of us are > > using these tools? > > One could look at: > > http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html > http://www.eecg.toronto.edu/~vaughn/vpr/e64.html (routing images) > > as a darn good start. I mailed the guy who wrote the package about a > year ago though, and he said specifying the 'resource descriptions' > as I refer to them above is by far the hardest problem, because of > course you have to specify the constraints under which the resources > operate as well as the method by which you instantiate the constraint > on the resource. This is encouraging. But how does it compare to the commercial tools? They don't say what the "chip" is. I assume it is an imaginary one, the routing appears to be very, very simplistic. Most FPGAs have multiple levels of routing and important limitations on how you can use that routing. I expect this would greatly complicate routing algorithms. But then maybe I am overstating the complexity of P&R algorithms. But they have been the bane of FPGA design for as long as there have been FPGAs. If you have a chip that runs 20% slower and have tools that optimize the P&R to give 20% better results, you will be able to meet or beat your competition. I am sure that every FPGA company works very hard to improve the P&R tools. > FPGA's are the new 80's PC's > ---------------------------- > > I do feel there is some merit in the statement that FPGA's are now at > the point where PC's were at 15 years ago. I would have never thought > I could design my own CPU at home, on a PC. Now though, it's pretty > darn cheap, and the effort-level isn't that high to start getting > results. I'm (painfully :-) aware that the black voodoo that all you > experts know (about the internals of the CLB's etc) is required to > squeeze the very last performance out of an FPGA, but I have a 32-bit > CPU running at 50MHz+ in a spartan-2 which I'm quite proud of for a > first project :-)) Congrats, that is impressive indeed. I don't even like to think about the "black voodoo" that some designers know. The last project I worked on for a company required lots of BV to overcome the poor toolset. It almost made me quit the FPGA game. > I have a (much more ambitious) longer-term project in mind, which (if > I ever finish it) will be quite a useful little device in my industry. > Perhaps even commercially viable, although that's a loong way away. My > point is that I can play and learn, whereas 2 years ago, I would have > (a) not tried, and (b) paid a fortune for a dedicated piece of hardware > to do the same job... I am glad that FPGAs have allowed you to design your own hardware. > All my designs will use Xilinx parts, because they're cheap to work with > (Thankyou BurchEd :-) and the s/w is downloadable. I would *really* like > to not have to reboot into Win2k to run the tools though - in fact the > main obstacle to the development of my "project" is that my Linux box > is usually busy doing things, and I don't want to interrupt it to play > on the FPGA stuff. Guess I should buy another computer ... > > ATB, > Simon. I would love to run something other than Windows myself. I have booted my machine four times today and I am shopping for a new laptop partly so I won't have to reinstall everything to get around this problem. But none of that changes the viability of open source tools for FPGA design. Perhaps the availability of free (as in beer) tools and low cost hardware will encourage more "amature" work in the tool area and we will start to see some open source tools. But I don't expect to see them being used much professionally during my career. I have about 10 - 15 years left. We will see if anything changes my mind by then. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Sun, 02 Dec 2001 23:21:23 -0500 Lines: 32 Message-ID: <3C0AFDC3.18C9B71F@yahoo.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> <3C0A6B70.2D17BD9@yahoo.com> <6uelmd48dw.fsf@chonsp.franklin.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVZNuDNWRx9VzTg/L68dFD5c5IFTWgvvd15aYstBy1CaFdzY1uVaZ9gq X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 3 Dec 2001 04:20:50 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12073 Neil Franklin wrote: > > rickman writes: > > such as AGP. But if you want, you can bring this inside the FPGA. But > > this is more work. My point was to try to minimize the work to get > > SOMETHING out sooner. But then I think in terms of commerciallizing > > things, not as a hobbiest. > > My method to save time is to actually have no bus at all. Rather > SDRAM sockets and set of standard IO connectors driven directly > (or with only a bit of analog stuff between) from the FPGA. "Bus" > is only internal, longlines or even user multiplexers. Also gives > maximal flexibility to different architectures. Exactly what do you consider to be a "standard" IO connector? I assumed that you meant PCI, ISA, IDE ect. If you want to put all that interface inside of the FPGA that will require more work on your part to design the interfaces. If you use an existing MB, you only have to design your CPU with a single bus interface. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### Message-ID: <3C0B48E5.1944346D@gornall.net> From: Simon Gornall Organization: Me, Myself, and I X-Mailer: Mozilla 4.78 [en] (X11; U; Linux 2.4.8-26mdk i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> <3C0AFC6D.521298D0@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 118 Date: Mon, 03 Dec 2001 09:41:57 +0000 NNTP-Posting-Host: 213.121.101.88 X-Trace: NewsReader 1007372460 213.121.101.88 (Mon, 03 Dec 2001 09:41:00 GMT) NNTP-Posting-Date: Mon, 03 Dec 2001 09:41:00 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!dispose.news.demon.net!demon!btnet-peer0!btnet-feed5!btnet!NewsPeer!Fusion!NewsReader.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12078 rickman wrote: > > Simon Gornall wrote: > > [Reasons why GCC is a good but limited analogy to FPGA P&R] > > That may all be true. But I still maintain that place and route software > is inherently more complex than complilers. No argument here! > The tasks required to > convert C language instructions to machine code for a given, well > defined architecture is conceptually straight forward and well > understood by nearly anyone graduating with a computer science degree. > On the other hand, place and route algorithms are in a class of problems > known as NP complete if my schooling has not failed me (or my memory). > This means essentially that you can NEVER deterministically find the > best solution to the problem for a realistic application given the state > of technology in the foreseeable future. At least this is true until we > are using Quantum computing which can explore all solution sets > simultaneously. Well, not quite. NP-Complete means you're both NP and NP-hard. "NP" means a "Non-deterministic turing machine can solve the problem in Polynomial time". In practice, this means the solution will take a loooong time, because most NP problems involve either an enormous number of iterations to get the answer, or they have a lot of variables, increasing the search space. Sometimes (as in FPGA routing, I'd expect) both :-( Polynomials can get big very rapidly when you have "lots" of potential solutions to examine :-(( There is the interesting factor that if you solve one NP problem, you can in theory solve them all, because any NP problem can be transformed into any other in polynomial time as well... > The difference in problem statment means that the algorithms for solving > them and the means of developing them are very, very different. The > suboptimal solution hunt will always require custom algorithms and > special tuning that are far more device specific than what is done to > write a code optimizer for a processor. I did a PhD using neural networks to map feature spaces into decision trees. My major discovery was that the relaxation-labelling equations that were developed for optic-flow are actually an instance of the Hopfield neural network solution set. I'd expect that behind the scenes, you'd probably need a peer-voting scheme with conventional constraint-based logic as inputs to multiple types of solver - for example, you could have a genetic algorithm, a K-nearest-neighbour and a neural network all providing possible solutions to localised routing, with a second tier above making the decision as to which one to "accept" as a potential solution - the one that best matches the other localised areas. I worked on some similar stuff when I was a post-Doc. > You obviously understand compliers pretty well. But what do you know > about designing place and route software? I don't profess to be an > expert, but this is a very different animal than writing a compiler. Very little :-) It seems to me that the routing is the problem though, and there are *lots* of techniques to try and maximise global "fit" over local minima in the solution space. > > > One could look at: > > > > http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html > > http://www.eecg.toronto.edu/~vaughn/vpr/e64.html (routing images) > > > > as a darn good start. I mailed the guy who wrote the package about a > > year ago though, and he said specifying the 'resource descriptions' > > as I refer to them above is by far the hardest problem, because of > > course you have to specify the constraints under which the resources > > operate as well as the method by which you instantiate the constraint > > on the resource. > > This is encouraging. But how does it compare to the commercial tools? > They don't say what the "chip" is. I assume it is an imaginary one, the > routing appears to be very, very simplistic. Most FPGAs have multiple > levels of routing and important limitations on how you can use that > routing. I expect this would greatly complicate routing algorithms. It will, but not necessarily to the level you expect. A constraint is a constraint - whether it spans one CLB block or 4 or 16 doesn't really matter. What does matter is the weighting given to how you would use the resource, but that's part of the problem... > But then maybe I am overstating the complexity of P&R algorithms. But > they have been the bane of FPGA design for as long as there have been > FPGAs. If you have a chip that runs 20% slower and have tools that > optimize the P&R to give 20% better results, you will be able to meet or > beat your competition. I am sure that every FPGA company works very hard > to improve the P&R tools. I'm not actually claiming it would be easy :-) I said I thought it would be hard. I do think it's in the realm of the possible though. At the moment I have too much to do (I'm building a radio telescope and writing the s/w to control it - I can do that in Linux so it takes priority over the FPGA stuff) Vaughn founded a company that's been bought by Altera, so he works for them now. It'll be interesting to see if 'vpr' will stick around. Grab a copy now! > But none of that changes the viability of open source tools for FPGA > design. Perhaps the availability of free (as in beer) tools and low cost > hardware will encourage more "amature" work in the tool area and we will > start to see some open source tools. But I don't expect to see them > being used much professionally during my career. I have about 10 - 15 > years left. We will see if anything changes my mind by then. Agreed. I'm working on the premise that if Xilinx get moaned at often enough, they will eventually listen. If only companies were as predictable as FPGA routing :-) ATB, Simon. ###### Message-ID: <3C0BD3D8.7C03AE1F@exponentmedia.deletethis.com> From: Andy Peters X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 Date: Mon, 03 Dec 2001 19:34:53 GMT NNTP-Posting-Host: 24.221.131.16 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1007408093 24.221.131.16 (Mon, 03 Dec 2001 11:34:53 PST) NNTP-Posting-Date: Mon, 03 Dec 2001 11:34:53 PST Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Mon, 03 Dec 2001 11:34:56 PST (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12097 Neil Franklin wrote: > Presently my real application is my design for running on such an > board (and being developed on an normal prototype board). Custom board > will follow after, to let more users use the design with less hassle. What's a "normal prototype board"? Don't tell me you're gonna wire-wrap this thing. Question: which open-source PCB layout tool will you be using for your custom circuit-board layout? Comment: all of the freeware/inexpensive board-layout tools suck, for many reasons. > Directly drive SDRAM off of the FPGA. There exist XAPPs on that. You don't need an XAPP for that. Just read any SDRAM data sheet. Piece of cake. I hope that non-lazy college professors will start having their students design DDR SDRAM controllers instead of "Traffic Controllers" and "Vending Machines." --andy ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 03 Dec 2001 23:00:55 +0100 Organization: My own Private Self Lines: 39 Message-ID: <6u667oq7zc.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007416855 499 10.0.3.2 (3 Dec 2001 22:00:55 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Dec 2001 22:00:55 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12101 Simon Gornall writes: > FPGA's are the new 80's PC's > I do feel there is some merit in the statement that FPGA's are now at > the point where PC's were at 15 years ago. Ah, someone to my liking :-). > I would *really* like > to not have to reboot into Win2k to run the tools though - in fact the > main obstacle to the development of my "project" is that my Linux box > is usually busy doing things, and I don't want to interrupt it to play > on the FPGA stuff. Guess I should buy another computer ... You seem to not know that you can develop for Virtex (without -E) and those Spartan-II models that have equivalent Virtex sizes under Linux. I am initially targetting the same BurchED board, and I have been 100% Microsoft-free for 5 years now. And I do not have a Solaris box either. The trick is to use Xilixes JBits toolsset. It is also a free (as in beer) download from Xilinx. Only problem is that since 2.6 the installer craps out under some Linux distributions (Debian and Slackware for sure), so one needs to borrow time on an Solaris box to do the install there, then .tar.gz it and unpack on Linux. JBits is a bit unusual in that is is totally low-level (you trigger individual chip features). For a look at how using it is like, try my project source at: http://neil.franklin.ch/Projects/PDP-10/pdp10.java -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 03 Dec 2001 23:04:30 +0100 Organization: My own Private Self Lines: 40 Message-ID: <6u3d2sq7td.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> <3C0A6B70.2D17BD9@yahoo.com> <6uelmd48dw.fsf@chonsp.franklin.ch> <3C0AFDC3.18C9B71F@yahoo.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007417070 499 10.0.3.2 (3 Dec 2001 22:04:30 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Dec 2001 22:04:30 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12102 rickman writes: > Neil Franklin wrote: > > > > My method to save time is to actually have no bus at all. Rather > > SDRAM sockets and set of standard IO connectors driven directly > > (or with only a bit of analog stuff between) from the FPGA. "Bus" > > is only internal, longlines or even user multiplexers. Also gives > > maximal flexibility to different architectures. > > Exactly what do you consider to be a "standard" IO connector? Oops. That term can be misunderstood. :-) > I assumed > that you meant PCI, ISA, IDE ect. I was thinking of VGA, PS/2, LPT, RS232, FDD, IDE, Ethernet and so on. > If you want to put all that interface > inside of the FPGA that will require more work on your part to design > the interfaces. As I have got to clone the register sets of the historic IO devices, actually implementing the functionality should follow. > If you use an existing MB, you only have to design your > CPU with a single bus interface. And then port the old systems OS to an totally new memory map and IO devices. I know from the original historic systems developers who are following my project, that such an port was for them a multi-year job. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: 03 Dec 2001 23:08:07 +0100 Organization: My own Private Self Lines: 30 Message-ID: <6uzo50ot2w.fsf@chonsp.franklin.ch> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> <3C0BD3D8.7C03AE1F@exponentmedia.deletethis.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1007417287 499 10.0.3.2 (3 Dec 2001 22:08:07 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 3 Dec 2001 22:08:07 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:12103 Andy Peters writes: > Neil Franklin wrote: > > > Presently my real application is my design for running on such an > > board (and being developed on an normal prototype board). Custom board > > will follow after, to let more users use the design with less hassle. > > What's a "normal prototype board"? Don't tell me you're gonna wire-wrap > this thing. Present intended board is the BurchED XC2S200 prototype board. For the newest revicion (B5) that gives 8 20pin connectors. What I will be putting on them I will decide when I am so far. > Question: which open-source PCB layout tool will you be using for your > custom circuit-board layout? Not decided. Not even investigated the issue yet. As said: first coding for the BurchED, parallel developing some tools. Then when users want to use the design (in perhaps 2 years) a board will be needed. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Mon, 03 Dec 2001 12:19:40 -0800 Organization: Xilinx Lines: 18 Message-ID: <3C0BDE5C.A0FE96A3@xilinx.com> References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6uy9kqa6v0.fsf@chonsp.franklin.ch> <3C065266.E43453F@yahoo.com> <6un115i2yd.fsf@chonsp.franklin.ch> <3C0703FF.17F10E82@yahoo.com> <6u7ks89e4g.fsf@chonsp.franklin.ch> <3C08AE53.E1539122@yahoo.com> <6ug06uai7x.fsf@chonsp.franklin.ch> <3C09C356.E168EB72@yahoo.com> <6uitbp4nvs.fsf@chonsp.franklin.ch> <3C0BD3D8.7C03AE1F@exponentmedia.deletethis.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; U; PPC) X-Accept-Language: en To: Andy Peters Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!TELOCITY!enews.sgi.com!nntp.wetware.com!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12109 Andy Peters wrote: > > Directly drive SDRAM off of the FPGA. There exist XAPPs on that. > > You don't need an XAPP for that. Just read any SDRAM data sheet. Piece > of cake. I hope that non-lazy college professors will start having > their students design DDR SDRAM controllers instead of "Traffic > Controllers" and "Vending Machines." Agreed, but I would still encourage FPGA users to consult the free app notes ( Xilinx labels them XAPP ). They are sometimes very good, sometimes so-so, but they usually are well-documented, and they are FREE. And you can do with them whatever you like, just don't ignore them off-hand. Peter Alfke, Xilinx Applications ###### Message-ID: <3C0BFC7B.9042BAC2@gornall.net> From: Simon Gornall Organization: Me, Myself, and I X-Mailer: Mozilla 4.78 [en] (X11; U; Linux 2.4.8-26mdk i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> <6u667oq7zc.fsf@chonsp.franklin.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 Date: Mon, 03 Dec 2001 22:28:11 +0000 NNTP-Posting-Host: 213.121.101.88 X-Trace: NewsReader 1007418435 213.121.101.88 (Mon, 03 Dec 2001 22:27:15 GMT) NNTP-Posting-Date: Mon, 03 Dec 2001 22:27:15 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!newsgate.cistron.nl!fr.clara.net!heighliner.fr.clara.net!opentransit.net!proxad.net!news-hub.cableinet.net!blueyonder!btnet-peer!btnet-peer0!btnet-feed5!btnet!NewsPeer!Fusion!NewsReader.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12113 Neil Franklin wrote: > > Simon Gornall writes: > > > FPGA's are the new 80's PC's > > > I do feel there is some merit in the statement that FPGA's are now at > > the point where PC's were at 15 years ago. > > Ah, someone to my liking :-). > > > I would *really* like > > to not have to reboot into Win2k to run the tools though - in fact the > > main obstacle to the development of my "project" is that my Linux box > > is usually busy doing things, and I don't want to interrupt it to play > > on the FPGA stuff. Guess I should buy another computer ... > > You seem to not know that you can develop for Virtex (without -E) and > those Spartan-II models that have equivalent Virtex sizes under Linux. Thanks for the info, Neil, I'll look into it :-) ATB, Simon. ###### Message-ID: <3c0cb6bc$0$21612$afc38c87@news.optusnet.com.au> From: hamish@cloud.net.au Subject: Re: Is there a full open-source synthesis path for any FPGA? Newsgroups: comp.arch.fpga References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> <3C0AFC6D.521298D0@yahoo.com> User-Agent: tin/1.5.8-20010221 ("Blue Water") (UNIX) (Linux/2.2.18 (i586)) Date: 04 Dec 2001 11:42:52 GMT Lines: 23 NNTP-Posting-Host: 203.164.66.244 X-Trace: 1007466172 21612 203.164.66.244 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!spool01.syd.optusnet.com.au!spool.optusnet.com.au!210.49.20.119.MISMATCH!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12131 rickman wrote: > On the other hand, place and route algorithms are in a class of problems > known as NP complete if my schooling has not failed me (or my memory). > This means essentially that you can NEVER deterministically find the > best solution to the problem for a realistic application given the state > of technology in the foreseeable future. At least this is true until we > are using Quantum computing which can explore all solution sets > simultaneously. This may be true, but it says nothing of the ability of the open source community to deliver a PAR tool equivalent in quality to Xilinx's or Altera's. After all, neither Xilinx or Altera are delivering a PAR tool which can deterministically find the best solution, as far as I can tell :-) Of course the chip vendors will always have the inside information on the chip. In fact, they are the only ones with the information on the chip presently, since they don't release enough details for anyone else to create a bitstream. Hamish -- Hamish Moffatt VK3SB ###### From: Kees van Reeuwijk Newsgroups: comp.arch.fpga Subject: Re: Is there a full open-source synthesis path for any FPGA? Date: Tue, 04 Dec 2001 12:52:49 +0100 Organization: Delft University of Technology Lines: 35 Message-ID: References: <3fl90uk0l3mmebi1703urlud5e91rou5af@4ax.com> <6u4rnebv23.fsf@chonsp.franklin.ch> <6u1yig9cxd.fsf@chonsp.franklin.ch> <3C07FE5E.F449946@xilinx.com> <3c0a0297$0$19497$afc38c87@news.optusnet.com.au> <3C0A6701.B481DEEB@yahoo.com> <3C0A9157.699E3FD8@gornall.net> <3C0AFC6D.521298D0@yahoo.com> NNTP-Posting-Host: lon.pds.twi.tudelft.nl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tudelft.nl 1007466740 356 130.161.157.242 (4 Dec 2001 11:52:20 GMT) X-Complaints-To: usenet@news.tudelft.nl NNTP-Posting-Date: Tue, 4 Dec 2001 11:52:20 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!isdnet!surfnet.nl!tudelft.nl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:12133 On Sun, 02 Dec 2001 23:15:41 -0500, rickman wrote: >That may all be true. But I still maintain that place and route software >is inherently more complex than complilers. The tasks required to >convert C language instructions to machine code for a given, well >defined architecture is conceptually straight forward and well >understood by nearly anyone graduating with a computer science degree. >On the other hand, place and route algorithms are in a class of problems >known as NP complete if my schooling has not failed me (or my memory). >This means essentially that you can NEVER deterministically find the >best solution to the problem for a realistic application given the state >of technology in the foreseeable future. At least this is true until we >are using Quantum computing which can explore all solution sets >simultaneously. Code generation for standard processors is not nearly as simple as you suggest here. Even in the good old days of simple processors such as the PDP 11, there was the fundamentally hard problem of register assignment (which nowadays is only a solved problem in the sense that there are pretty good heuristics, the processors try to help, and there are worse problems). Modern processors have goodies like multiple levels of caches, branch prediction, out-of-order execution, vector units, and SMP. They all complicate code generation; sometimes a lot. It is far from trivial to generate the instruction sequence that requires the minimal number of processor cycles to execute, and that's even true for sane architectures like the ARM and Sparc. The i386 something else again. IMHO it's more a matter of acceptance. A program that is twice as large as is necessary or is half as fast as is possible is readily accepted for most applications. On the other hand, an FPGA configuration that uses twice the CLBs necessary or requires halving the clock frequency is often not acceptable.