From: "Philippe Robert" Newsgroups: comp.arch.fpga Subject: Decoupling capacitors on Virtex II Date: Fri, 9 Nov 2001 10:59:05 -0000 Lines: 20 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 NNTP-Posting-Host: 213.254.164.196 Message-ID: <3bebb7ef$1@peer1.news.newnet.co.uk> X-Trace: peer1.news.newnet.co.uk 1005303791 213.254.164.196 (9 Nov 2001 11:03:11 GMT) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!t-online.de!colt.net!newspeer.clara.net!news.clara.net!peer1.news.newnet.co.uk Xref: chonsp.franklin.ch comp.arch.fpga:11420 Hi there, I found an application note on the Xilinx website (xapp158) about decoupling capacitors. It is explained that high frequency and mid-frequency capacitors are required. For the high frequency capacitor, I will use 100nF. It says in that app to fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! Can someone tell me of my calculation is right ? For mid-frequency caps, I will use 10uF tant, but the app note does not say how many of them to fit. Does anyone know ? Thanks for your help. Philippe. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Fri, 09 Nov 2001 11:48:14 -0500 Lines: 45 Message-ID: <3BEC08CE.765E98CF@yahoo.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVamwm+/7onwSdyYe9sanqbTUgG7hC0rEk8M3/03SAgdz8gth6ehKcQQ X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 9 Nov 2001 16:48:22 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11371 Philippe Robert wrote: > > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > Can someone tell me of my calculation is right ? > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > how many of them to fit. > Does anyone know ? > > Thanks for your help. > Philippe. I personally think that Xilinx is using a lot of overkill in their goal of 1 cap per vcc. This is a noble goal, but rather impractical on the packages with very fine pitch balls. When there are two or three pins together, I would use one 100 nF cap per clump of pins. How many 10 uF caps to use is not really the right question. With the bulk medium freq caps, you only need one per board. That is because they have high impedance at high frequencies. The cap impedance is much higher than the circuit impedance even when at the other side of the board from the chip. So you can get by with a single bulk cap per board. Just use one that is large enough and has a low ESR. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Fri, 09 Nov 2001 10:11:27 -0800 Organization: Xilinx Lines: 127 Message-ID: <3BEC1C4F.4E6243EB@xilinx.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC08CE.765E98CF@yahoo.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!5053956!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!skynet.be!skynet.be!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news.city-guide.com!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11377 Rick, Folks are really getting in trouble with inadequate decoupling. Howard Johnson states that as the frequency doubles, the bypassing increases by 8 times (cube of frequency). If the method used to figure out how to bypass is the "brute force" method used by Howard Johnson (ie use all 0.1 uF and just use lots of them) (and many others, including our own App 158 to some extent), the requirements get ridiculous, as you well note. In fact I have a document for our FAE's called: "Bypass, How???" that outlines the situation. Ask your FAE for it if you are interested, or email me directly. It is a text file. Lately we have decided to go to a more advanced bypassing approach, used by Intel and others on their motherboards. The first app note that will use this information will apply to Virtex II, and newer chips. I would call it the "take advantage of the series resonance" approach. This is where you match up the minimum impedance points of three of four values of capacitors with the frequency peaks in your design. This requires an a priori knowledge of where the peaks will occur, or measurement of the board after it is built with a spectrum analyzer. You then pick and choose specific cap values from specific manufacturers that are most effective at the frequencies of interest. There are simulation tools that can help in the design of a frequency selective bypassing arrangement as well. We have used this method, and shown the number of bypass caps may be reduced from ~ 100 0.1uF's on the board, to ~64 total of four separate values, with a reduction of the p-p noise on the supplies. Obviously, this requires that you know what your design is going to do in the frequency domain, which makes it impossible for us to recommend anything at all, except to follow a procedure to get the answer that is unique to your design. There are also some exciting advances in pcb laminate materials for buried bypass (high K inner layers -- Zycon(tm?r?) by Hadco for example) that provide a great deal of decoupling without all of the discrete devices. As a distributed capacitor array, you almost don't care about frequency content, until you get to the lower frequencies the material can not deal with. At 3 nF/sq inch, a 100 sq inch board is 0.3uF for all of the devices, so a number of larger value caps are probably required. I suspect the basic "general purpose do everything for everyone non-serializer/deserializer" IO's are going to hit the ceiling at 1 Gb/s (they already have), so the bypassing we are looking at will not change radically as it did when we went from Virtex E to Virtex II (with a doubling or quadrupling of all speeds). Thus the bypassing solutions now have a chance to catch up with the technology. The core logic has always been intrinsically self-bypassed for the highest frequencies (which may explain why the industry never seems to change the bypass solution for the core after 20 years!), so the lower frequencies will always remain the ones that require the external caps. These may be chosen in exactly the same way as the IO caps, based on frequency of the current to the core. Some other common mistakes are running traces to the caps (makes them useless), having a single via from the plane to the end of the pad (not as good as two vias, or via in pad), and locating the caps too far from the chip, and having a good bypass solution for the fpga, and forgetting all of the other really new high speed chips on the board that no one told you also need even better bypass solutions. As to how many 10uF, or 47 uF (whatever your favorite value is) you need, we use one 47uF per Vcco bank on our general purpose break out boards. I have seen customer boards with as many as two 47 uF per bank, and an additional 470 uF per bank. It all depends on their data patterns, and the frequency content of those data patterns. If you change from all 1's to all 0's every millisecond, then you have a real 'thump' of current at a 1KHz rate. That may require a fairly large capacitor. Austin rickman wrote: > Philippe Robert wrote: > > > > Hi there, > > > > I found an application note on the Xilinx website (xapp158) about decoupling > > capacitors. It is explained that high frequency and mid-frequency capacitors > > are required. > > > > For the high frequency capacitor, I will use 100nF. It says in that app to > > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > > Can someone tell me of my calculation is right ? > > > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > > how many of them to fit. > > Does anyone know ? > > > > Thanks for your help. > > Philippe. > > I personally think that Xilinx is using a lot of overkill in their goal > of 1 cap per vcc. This is a noble goal, but rather impractical on the > packages with very fine pitch balls. When there are two or three pins > together, I would use one 100 nF cap per clump of pins. > > How many 10 uF caps to use is not really the right question. With the > bulk medium freq caps, you only need one per board. That is because they > have high impedance at high frequencies. The cap impedance is much > higher than the circuit impedance even when at the other side of the > board from the chip. So you can get by with a single bulk cap per board. > Just use one that is large enough and has a low ESR. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "pete dudley" Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Fri, 9 Nov 2001 12:34:51 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 X-Complaints-To: newsabuse@supernews.com Lines: 48 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sn-xit-03!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11426 Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF tantalums. We use terminated differential signalling for the high speed stuff if possible to cancel the ground bounce and use slew rate control on the rest. On the highest end of the switching spectrum the ground/power planes help you and my guess is that 100pF or smaller chip caps do nothing for you. Once we built some multiprocessor boards that ran about 150MHz but the caps were bad so we removed all of them. The boards ran fine without any decoupling. I'd like to try that experiment again with high speed fpga's. I like Austin's idea of tuning the caps to the operating frequency. -- Pete Dudley Arroyo Grande Systems "Philippe Robert" wrote in message news:3bebb7ef$1@peer1.news.newnet.co.uk... > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > Can someone tell me of my calculation is right ? > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > how many of them to fit. > Does anyone know ? > > Thanks for your help. > Philippe. > > > ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Fri, 9 Nov 2001 23:12:49 -0000 Message-ID: <1005353517.18151.0.nnrp-08.9e9832fa@news.demon.co.uk> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC08CE.765E98CF@yahoo.com> <3BEC1C4F.4E6243EB@xilinx.com> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 1005353517 nnrp-08:18151 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Lines: 19 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!193.190.198.17.MISMATCH!newsfeeds.belnet.be!news.belnet.be!newsfeed.icl.net!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11438 "Austin Lesea" wrote > Some other common mistakes are running traces to the caps (makes them useless), > having a single via from the plane to the end of the pad (not as good as two vias, > or via in pad), and locating the caps too far from the chip, and having a good > bypass solution for the fpga, and forgetting all of the other really new high > speed chips on the board that no one told you also need even better bypass > solutions. Also choose the lowest inductance package/via combination and max the cap within that setup. And replace 0805, etc types by 0508, etc types. ###### Message-ID: <3BEC6DB5.C5CCA83A@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.119.102 Organization: iPrimus Australia - http://www.iprimus.com.au Lines: 27 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Sat, 10 Nov 2001 10:58:45 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1005350288 203.134.67.67 (Sat, 10 Nov 2001 10:58:08 EST) NNTP-Posting-Date: Sat, 10 Nov 2001 10:58:08 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:11404 pete dudley wrote: > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > tantalums. > > We use terminated differential signalling for the high speed stuff if > possible to cancel the ground bounce and use slew rate control on the rest. > > On the highest end of the switching spectrum the ground/power planes help > you and my guess is that 100pF or smaller chip caps do nothing for you. > > Once we built some multiprocessor boards that ran about 150MHz but the caps > were bad so we removed all of them. The boards ran fine without any > decoupling. I'd like to try that experiment again with high speed fpga's. > > I like Austin's idea of tuning the caps to the operating frequency. With *thin* layers (such as in 8 layer boards etc), all the caps can be left off except one electro per board. The VCC and GND planes must be adjacent to provide very low planar transmission line impedance (lumped capacitance is meaningless at fast edges). A bit of track to bypass caps and vias hardly matters relative to the inductance in many internal bond wires. ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 12 Nov 2001 09:13:49 +0000 Organization: TRW Automotive Technical Centre Lines: 31 Sender: Thompsm@977845-DT Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1005556295 38724720 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!41012!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11465 "Philippe Robert" writes: > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > Can someone tell me of my calculation is right ? > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > how many of them to fit. > Does anyone know ? > For some good discussion on *designing* your power distribution system, which becomes essential when the rules of thumb wear out, see this page, especially the top two papers... sorry it's a long link! http://groups.yahoo.com/group/si-list/files/Signal%20Integrity%20Documents/Published%20SI%20Papers%20from%20Sun/ Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Mon, 12 Nov 2001 07:57:06 -0800 Organization: Xilinx Lines: 39 Message-ID: <3BEFF152.82BA8450@xilinx.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!cyclone.swbell.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11467 Russell, You must enjoy dangerous living .... And, the inductance of the flip chip packages is 5 to 8 times less than that of the wire bonded packages as there are no wires, just hundreds and hundreds of tiny solder balls over the entire top surface of the die connecting to ground and Vcc's. Austin Russell Shaw wrote: > pete dudley wrote: > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > > tantalums. > > > > We use terminated differential signalling for the high speed stuff if > > possible to cancel the ground bounce and use slew rate control on the rest. > > > > On the highest end of the switching spectrum the ground/power planes help > > you and my guess is that 100pF or smaller chip caps do nothing for you. > > > > Once we built some multiprocessor boards that ran about 150MHz but the caps > > were bad so we removed all of them. The boards ran fine without any > > decoupling. I'd like to try that experiment again with high speed fpga's. > > > > I like Austin's idea of tuning the caps to the operating frequency. > > With *thin* layers (such as in 8 layer boards etc), all the caps > can be left off except one electro per board. The VCC and GND planes > must be adjacent to provide very low planar transmission line > impedance (lumped capacitance is meaningless at fast edges). > > A bit of track to bypass caps and vias hardly matters relative > to the inductance in many internal bond wires. ###### Message-ID: <3BF068F4.F78E7495@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 210.50.119.65 Lines: 50 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Tue, 13 Nov 2001 11:27:32 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1005611224 203.134.67.67 (Tue, 13 Nov 2001 11:27:04 EST) NNTP-Posting-Date: Tue, 13 Nov 2001 11:27:04 EST Organization: IPrimus Customer - reports relating to abuse should be sent to abuse@iprimus.com.au Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:11526 It should be easy to verify if your board will be ok. Just remove the caps around one chip, power-up, and look at glitch levels on the pins/pads with a high-speed cro (you'll need to have a good ground-pin on the cro probe). If the glitching is less than 10% of VCC, or adding the caps makes little difference, the caps aren't really needed. Its important that the power-ground planes are large in area, and adjacent (higher capacitance, lower pulse impedance). Standard 2/4-layer board probably wouldn't be good enough. Austin Lesea wrote: > > Russell, > > You must enjoy dangerous living .... > > And, the inductance of the flip chip packages is 5 to 8 times less than that of > the wire bonded packages as there are no wires, just hundreds and hundreds of tiny > solder balls over the entire top surface of the die connecting to ground and > Vcc's. > > Austin > > Russell Shaw wrote: > > > pete dudley wrote: > > > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > > > tantalums... > > > > > > We use terminated differential signalling for the high speed stuff if > > > possible to cancel the ground bounce and use slew rate control on the rest. > > > > > > On the highest end of the switching spectrum the ground/power planes help > > > you and my guess is that 100pF or smaller chip caps do nothing for you. > > > > > > Once we built some multiprocessor boards that ran about 150MHz but the caps > > > were bad so we removed all of them. The boards ran fine without any > > > decoupling. I'd like to try that experiment again with high speed fpga's. > > > > > > I like Austin's idea of tuning the caps to the operating frequency. > > > > With *thin* layers (such as in 8 layer boards etc), all the caps > > can be left off except one electro per board. The VCC and GND planes > > must be adjacent to provide very low planar transmission line > > impedance (lumped capacitance is meaningless at fast edges). > > > > A bit of track to bypass caps and vias hardly matters relative > > to the inductance in many internal bond wires. ###### From: "Philippe Robert" Newsgroups: comp.arch.fpga References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> Subject: Re: Decoupling capacitors on Virtex II Date: Thu, 15 Nov 2001 14:04:25 -0000 Lines: 79 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 NNTP-Posting-Host: 213.254.164.196 Message-ID: <3bf3ccab@peer1.news.newnet.co.uk> X-Trace: peer1.news.newnet.co.uk 1005833387 213.254.164.196 (15 Nov 2001 14:09:47 GMT) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!dispose.news.demon.net!demon!diablo.netcom.net.uk!netcom.net.uk!btnet-peer!btnet!newspeer.clara.net!news.clara.net!peer1.news.newnet.co.uk Xref: chonsp.franklin.ch comp.arch.fpga:11596 Hi all, Thanks for your answers. It did help me. I have to confess that I have just been graduated and in consequence I do not have much experience. There is something that confuses me is that you guys are talking about bypass or decoupling capacitors. What's the difference ? Do you have any recent book to advice me about PCBs and high speed systems ? Thanks for your help again. Philippe. "Russell Shaw" wrote in message news:3BF068F4.F78E7495@iprimus.com.au... > It should be easy to verify if your board will be ok. Just remove > the caps around one chip, power-up, and look at glitch levels on > the pins/pads with a high-speed cro (you'll need to have a good > ground-pin on the cro probe). If the glitching is less than 10% > of VCC, or adding the caps makes little difference, the caps > aren't really needed. Its important that the power-ground > planes are large in area, and adjacent (higher capacitance, > lower pulse impedance). Standard 2/4-layer board probably > wouldn't be good enough. > > Austin Lesea wrote: > > > > Russell, > > > > You must enjoy dangerous living .... > > > > And, the inductance of the flip chip packages is 5 to 8 times less than that of > > the wire bonded packages as there are no wires, just hundreds and hundreds of tiny > > solder balls over the entire top surface of the die connecting to ground and > > Vcc's. > > > > Austin > > > > Russell Shaw wrote: > > > > > pete dudley wrote: > > > > > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > > > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > > > > tantalums... > > > > > > > > We use terminated differential signalling for the high speed stuff if > > > > possible to cancel the ground bounce and use slew rate control on the rest. > > > > > > > > On the highest end of the switching spectrum the ground/power planes help > > > > you and my guess is that 100pF or smaller chip caps do nothing for y ou. > > > > > > > > Once we built some multiprocessor boards that ran about 150MHz but the caps > > > > were bad so we removed all of them. The boards ran fine without any > > > > decoupling. I'd like to try that experiment again with high speed fpga's. > > > > > > > > I like Austin's idea of tuning the caps to the operating frequency. > > > > > > With *thin* layers (such as in 8 layer boards etc), all the caps > > > can be left off except one electro per board. The VCC and GND planes > > > must be adjacent to provide very low planar transmission line > > > impedance (lumped capacitance is meaningless at fast edges). > > > > > > A bit of track to bypass caps and vias hardly matters relative > > > to the inductance in many internal bond wires. ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 15 Nov 2001 14:20:32 +0000 Organization: TRW Automotive Technical Centre Lines: 27 Sender: Thompsm@977845-DT Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> <3bf3ccab@peer1.news.newnet.co.uk> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1005833883 39382394 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!62159!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11582 "Philippe Robert" writes: > Hi all, > > Thanks for your answers. It did help me. > I have to confess that I have just been graduated and in consequence I do > not have much experience. There is something that confuses me is that you > guys are talking about bypass or decoupling capacitors. > What's the difference ? > None in my experience. > Do you have any recent book to advice me about PCBs and high speed systems ? > Try High Speed Digital design - a handbook of black magic by Howard Johnson and Martin Graham. Buying link from Howard Johnson's site http://www.signalintegrity.com/books.htm Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Thu, 15 Nov 2001 11:10:17 -0500 Organization: http://extra.newsguy.com Lines: 20 Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> <3bf3ccab@peer1.news.newnet.co.uk> NNTP-Posting-Host: p-426.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!pln-e!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews2 Xref: chonsp.franklin.ch comp.arch.fpga:11607 In article <3bf3ccab@peer1.news.newnet.co.uk>, PhilippeR@sundance.com says... > Hi all, > > Thanks for your answers. It did help me. > I have to confess that I have just been graduated and in consequence I do > not have much experience. There is something that confuses me is that you > guys are talking about bypass or decoupling capacitors. > What's the difference ? Decoupling capacitors go from power to ground to decouple the sink (local voltage) from the inductance of the source (power network). Bypass capacitors go from power to ground to bypass AC noise from power to ground. It's all how you were brought up and how you look at things. ;-) Actually, both are useful ways to look at the same problem. ---- Keith ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Thu, 15 Nov 2001 08:40:51 -0800 Organization: Xilinx Lines: 85 Message-ID: <3BF3F013.BB63BA62@xilinx.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> <3bf3ccab@peer1.news.newnet.co.uk> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!arclight.uoregon.edu!enews.sgi.com!nntp.wetware.com!attbt1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11586 More to consider than just bypassing.... http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck Austin Philippe Robert wrote: > Hi all, > > Thanks for your answers. It did help me. > I have to confess that I have just been graduated and in consequence I do > not have much experience. There is something that confuses me is that you > guys are talking about bypass or decoupling capacitors. > What's the difference ? > > Do you have any recent book to advice me about PCBs and high speed systems ? > > Thanks for your help again. > Philippe. > > "Russell Shaw" wrote in message > news:3BF068F4.F78E7495@iprimus.com.au... > > It should be easy to verify if your board will be ok. Just remove > > the caps around one chip, power-up, and look at glitch levels on > > the pins/pads with a high-speed cro (you'll need to have a good > > ground-pin on the cro probe). If the glitching is less than 10% > > of VCC, or adding the caps makes little difference, the caps > > aren't really needed. Its important that the power-ground > > planes are large in area, and adjacent (higher capacitance, > > lower pulse impedance). Standard 2/4-layer board probably > > wouldn't be good enough. > > > > Austin Lesea wrote: > > > > > > Russell, > > > > > > You must enjoy dangerous living .... > > > > > > And, the inductance of the flip chip packages is 5 to 8 times less than > that of > > > the wire bonded packages as there are no wires, just hundreds and > hundreds of tiny > > > solder balls over the entire top surface of the die connecting to ground > and > > > Vcc's. > > > > > > Austin > > > > > > Russell Shaw wrote: > > > > > > > pete dudley wrote: > > > > > > > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface > mount, like > > > > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up > to 10uF > > > > > tantalums... > > > > > > > > > > We use terminated differential signalling for the high speed stuff > if > > > > > possible to cancel the ground bounce and use slew rate control on > the rest. > > > > > > > > > > On the highest end of the switching spectrum the ground/power planes > help > > > > > you and my guess is that 100pF or smaller chip caps do nothing for y > ou. > > > > > > > > > > Once we built some multiprocessor boards that ran about 150MHz but > the caps > > > > > were bad so we removed all of them. The boards ran fine without any > > > > > decoupling. I'd like to try that experiment again with high speed > fpga's. > > > > > > > > > > I like Austin's idea of tuning the caps to the operating frequency. > > > > > > > > With *thin* layers (such as in 8 layer boards etc), all the caps > > > > can be left off except one electro per board. The VCC and GND planes > > > > must be adjacent to provide very low planar transmission line > > > > impedance (lumped capacitance is meaningless at fast edges). > > > > > > > > A bit of track to bypass caps and vias hardly matters relative > > > > to the inductance in many internal bond wires. ###### Message-ID: <3BF80423.1BA8B2B0@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> <3bf3ccab@peer1.news.newnet.co.uk> <3BF3F013.BB63BA62@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 18 Date: Sun, 18 Nov 2001 18:55:31 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1006109733 62.254.210.251 (Sun, 18 Nov 2001 18:55:33 GMT) NNTP-Posting-Date: Sun, 18 Nov 2001 18:55:33 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!btnet-peer1!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11658 Austin Lesea wrote: > More to consider than just bypassing.... > > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck > > Austin > Nice checklist although the "simulation" rqeuirements presuppose access to a SPICE engine. Is there a freeware/opensource/public-domain implemetation ? Only one quibble on TI (= TextIntegrity): Are you really recommending milliFarad (e.g. 4.7mF) caps ? Perhaps its a misprint for 4.7MF :-). ###### From: ian.dedic@acg.fujitsu-fme.com (Ian Dedic) Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 19 Nov 2001 06:31:56 -0800 Organization: http://groups.google.com/ Lines: 73 Message-ID: <1476aea8.0111190631.44d5adef@posting.google.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> NNTP-Posting-Host: 193.112.220.1 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1006180317 20841 127.0.0.1 (19 Nov 2001 14:31:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 19 Nov 2001 14:31:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-out.visi.com!hermes.visi.com!hub.org!hub.org!news.gv.tsc.tdk.com!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11674 It's a common misconception that smaller value decouplers are "better" at high frequencies, in fact it's the inductance that matters. This is indirectly linked to value by physical size, but if you compare 100nF and 10nF in 0805 packages they have the same inductance (HF decoupling performance), and the 100nF will be 10x better at lower frequencies. Yes the self-resonant frequency will be lower, but once inductance takes over the impedance (which is what matters) is the same. It all depends over what frequency range you want to keep the supply impedance low; if you need a wide range things get difficult. And the more different capacitor sizes and values you use, the more the chance of getting nasty resonances between the inductance of one and the capacitance of another. In RF and microwave they don't care about performance below 100's of MHz, so the smallest value capacitor will perform just as well as a larger one and may be better because it's available in a smaller case size. With high-speed digital circuits the lower frequency of the noise can be kHz depending on what processing is going on (for example, at the frame rate in some systems). Adding a small number of lower-value capacitors has little effect, because the most important factor is the total equivalent series inductance. Inter-plane capacitance has negligible inductance, but also pretty small capacitace -- fine at RF frequencies, but less useful in the 10's to 100's of MHz region. We work on design of (among other things) high-speed CMOS DACs, and have to get low supply impedance over a frequency range of kHz to GHz. In the region from a few MHz upwards, the best approach is a large number of physically small high-value surface-mount ceramics (eg. 0805 or smaller, 1uF or greater) which provide charge for both high-speed edges and lower frequencies without any resonances. Plus of course a large value low ESR elctrolytic (eg. 330uF OSCON) to provide the charge below a few MHz. Ian Dedic Chief Engineer Mixed Signal Division Fujitsu Microelectronics Europe "Falk Brunner" wrote in message news:<9sh63h$1249vl$1@ID-84877.news.dfncis.de>... > "Philippe Robert" schrieb im Newsbeitrag > news:3bebb7ef$1@peer1.news.newnet.co.uk... > > Hi there, > > > > I found an application note on the Xilinx website (xapp158) about > decoupling > > capacitors. It is explained that high frequency and mid-frequency > capacitors > > are required. > > > > For the high frequency capacitor, I will use 100nF. It says in that app to > > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > > 100nF isnt that good at HIGH frequencys. Remember, the higher the > capacitance, the higher the (parasitic) inductance of a cap. > And since the Virtex-II are damm fast devices, I would use 10nF caps. Not > 10x10nF, but lets say at least 4 10nF caps to decouple the core. Also > remember, the higher the value of a decoupling cap, you can place them more > far away from the VCC pins. Usually, you have a cascade of caps, 10nF, > 100nF, 10uF 1000uF. > > > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > > Hmm, try redestributiing the capacitance into less caps, but dont forget to > use small ones (10nF or lower) for the "really" high frequencys. In > microwave engineering they use sometimes even 100pF instead of 1nF because > of the lower inductance. > And dont forget a good ground-VCC planes. In your layer stacking, the > GND-VCC planes should be close together, forming a superb high frequncy > capacitor. ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Mon, 19 Nov 2001 10:20:30 -0500 Lines: 86 Message-ID: <3BF9233E.64D3DFFC@yahoo.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVb9nXP3FNxKvAQQr/ajmhXaNUh6zf/zeRfoxCTysRwhz2wRIcEJ+L4B X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 19 Nov 2001 15:20:26 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11654 Ian, You are a man after my own heart. You seem to actually understand what is going on rather than just having learned a few "rules of thumb". So many people who design power distibution never actually read the capacitor data sheets and have no true understanding of how they work at high frequencies. I agree 100% with everything you said, expecially the part about using a single large value, low ESR device on the board. I have read several people here say that you need multiple tantalums per chip which is nonsense. The only reason (that I know) of placing caps near the load is to minimize the effects of inductance in the power distibution. But since the large, bulk caps have very high inductance relative to the power distribution, there is no need to keep them close to the load. So you can use one large device anywhere on the board. Another point that often escapes designers is that it does not matter if your noise frequecies are above the self resonant point of the cap. At those frequencies the cap is actually an inductor. But as long as the impedance is low, it still acts to decouple the noise. So for high freqs, the only relevant factor is the total impedance to ground. By keeping this impedance low at the frequencies of the noise, you will get good decoupling and a quiet power plane. So lots of MLCC caps are good and more are better. As you say, the value is not so important, moreso the physical size. Ceramic 100 nF, 0603 caps work great and don't clutter up the board with bulk. Ian Dedic wrote: > > It's a common misconception that smaller value decouplers are "better" > at high frequencies, in fact it's the inductance that matters. This is > indirectly linked to value by physical size, but if you compare 100nF > and 10nF in 0805 packages they have the same inductance (HF decoupling > performance), and the 100nF will be 10x better at lower frequencies. > > Yes the self-resonant frequency will be lower, but once inductance > takes over the impedance (which is what matters) is the same. It all > depends over what frequency range you want to keep the supply > impedance low; if you need a wide range things get difficult. And the > more different capacitor sizes and values you use, the more the chance > of getting nasty resonances between the inductance of one and the > capacitance of another. > > In RF and microwave they don't care about performance below 100's of > MHz, so the smallest value capacitor will perform just as well as a > larger one and may be better because it's available in a smaller case > size. With high-speed digital circuits the lower frequency of the > noise can be kHz depending on what processing is going on (for > example, at the frame rate in some systems). > > Adding a small number of lower-value capacitors has little effect, > because the most important factor is the total equivalent series > inductance. Inter-plane capacitance has negligible inductance, but > also pretty small capacitace -- fine at RF frequencies, but less > useful in the 10's to 100's of MHz region. > > We work on design of (among other things) high-speed CMOS DACs, and > have to get low supply impedance over a frequency range of kHz to GHz. > In the region from a few MHz upwards, the best approach is a large > number of physically small high-value surface-mount ceramics (eg. 0805 > or smaller, 1uF or greater) which provide charge for both high-speed > edges and lower frequencies without any resonances. Plus of course a > large value low ESR elctrolytic (eg. 330uF OSCON) to provide the > charge below a few MHz. > > Ian Dedic > > Chief Engineer > Mixed Signal Division > Fujitsu Microelectronics Europe -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Mon, 19 Nov 2001 07:48:54 -0800 Organization: Xilinx Lines: 28 Message-ID: <3BF929E6.435A8726@xilinx.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC6DB5.C5CCA83A@iprimus.com.au> <3BEFF152.82BA8450@xilinx.com> <3BF068F4.F78E7495@iprimus.com.au> <3bf3ccab@peer1.news.newnet.co.uk> <3BF3F013.BB63BA62@xilinx.com> <3BF80423.1BA8B2B0@algor.co.uk> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en]C-CCK-MCD (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!TELOCITY!enews.sgi.com!nntp.wetware.com!attdv1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11655 Microfarads = uF .... Will go fix it. There are some shareware programs for evaluating bypass caps. (For those without spice, but hey, Berkeley Spice is free ....). I'll see if I can find the reference... Austin Rick Filipkiewicz wrote: > Austin Lesea wrote: > > > More to consider than just bypassing.... > > > > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck > > > > Austin > > > > Nice checklist although the "simulation" rqeuirements presuppose access to a SPICE > engine. Is there a freeware/opensource/public-domain implemetation ? > > Only one quibble on TI (= TextIntegrity): Are you really recommending milliFarad > (e.g. 4.7mF) caps ? Perhaps its a misprint for 4.7MF :-). ###### Message-ID: <3BF95D18.F2249F53@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 27 Date: Mon, 19 Nov 2001 19:27:24 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@tek.com X-Trace: news-west.eli.net 1006198044 192.65.17.17 (Mon, 19 Nov 2001 12:27:24 MST) NNTP-Posting-Date: Mon, 19 Nov 2001 12:27:24 MST Organization: Tektronix NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!telocity-west!TELOCITY!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11715 The best comment in this thread so far IMHO. Thanks, Rick. Smaller valued caps can give lower impedances at higher frequencies but if one looks at the datasheets from Kemet or AVX or Vishay, you'll find that lower capacitance values don't necessarily give you (much) better high frequency impedence. A good look at the Z vs F curves will shed some light on how good a cap can be at high frequencies. And just as the bulk, low ESR tantalum caps go, higher value (1uF for instance) capacitors may not have a good enough impedance near 1GHz to deal with those <1nS switching transients. The impedance versus frequency information is sometimes tough to find but it's out there. The LICA array from AVX is one example where the attempt to provide best-of-class high frequency performance is made; the practicality might be limited, though. rickman wrote: > Another point that often escapes designers is that it does not matter if > your noise frequecies are above the self resonant point of the cap. At > those frequencies the cap is actually an inductor. But as long as the > impedance is low, it still acts to decouple the noise. So for high > freqs, the only relevant factor is the total impedance to ground. By > keeping this impedance low at the frequencies of the noise, you will get > good decoupling and a quiet power plane. So lots of MLCC caps are good > and more are better. As you say, the value is not so important, moreso > the physical size. Ceramic 100 nF, 0603 caps work great and don't > clutter up the board with bulk. ###### Message-ID: <3BFC4849.240265B9@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 53 Date: Thu, 22 Nov 2001 00:35:22 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 1006389326 62.254.210.251 (Thu, 22 Nov 2001 00:35:26 GMT) NNTP-Posting-Date: Thu, 22 Nov 2001 00:35:26 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!btnet-peer1!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11752 rickman wrote: > Ian, > > You are a man after my own heart. You seem to actually understand what > is going on rather than just having learned a few "rules of thumb". So > many people who design power distibution never actually read the > capacitor data sheets and have no true understanding of how they work at > high frequencies. > > I agree 100% with everything you said, expecially the part about using a > single large value, low ESR device on the board. I have read several > people here say that you need multiple tantalums per chip which is > nonsense. The only reason (that I know) of placing caps near the load is > to minimize the effects of inductance in the power distibution. But > since the large, bulk caps have very high inductance relative to the > power distribution, there is no need to keep them close to the load. So > you can use one large device anywhere on the board. > > Another point that often escapes designers is that it does not matter if > your noise frequecies are above the self resonant point of the cap. At > those frequencies the cap is actually an inductor. But as long as the > impedance is low, it still acts to decouple the noise. So for high > freqs, the only relevant factor is the total impedance to ground. By > keeping this impedance low at the frequencies of the noise, you will get > good decoupling and a quiet power plane. So lots of MLCC caps are good > and more are better. As you say, the value is not so important, moreso > the physical size. Ceramic 100 nF, 0603 caps work great and don't > clutter up the board with bulk. > > If the the rule that high speed decouplers should be placed as close as possible to the chip's power pins [I've heard ~1cm] isn't just more voodoo then its rationale must be inductance again ? One other query I've got is that it seems that what's called decoupling really covers 2 things: o Stopping high frequency noise generated externally from getting into the chip via the power pins. o Dealing with self-injected noise from the chip driving very fast edges into capacitive loads. In the second case, with edges in the 1-2 nsec range or faster it would appear to me that the frequencies we are dealing with have 500MHz+ components. In other words even 0402 caps will appear inductive ? ###### Message-ID: <3BFC5BCB.67B981FC@home.com> From: William L Hunter Jr Reply-To: wlhunterjr@home.com X-Mailer: Mozilla 4.7 [en]C-NECCK (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II References: <3bebb7ef$1@peer1.news.newnet.co.uk> <3BEC08CE.765E98CF@yahoo.com> <3BEC1C4F.4E6243EB@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 Date: Thu, 22 Nov 2001 01:58:46 GMT NNTP-Posting-Host: 24.14.78.158 X-Complaints-To: abuse@home.net X-Trace: news2.rdc2.tx.home.com 1006394326 24.14.78.158 (Wed, 21 Nov 2001 17:58:46 PST) NNTP-Posting-Date: Wed, 21 Nov 2001 17:58:46 PST Organization: Excite@Home - The Leader in Broadband http://home.com/faster Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!news-in-sanjose!newshub2.rdc1.sfba.home.com!news.home.com!news2.rdc2.tx.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11801 Austin Lesea wrote: > Some other common mistakes are running traces to the caps (makes them useless), > having a single via from the plane to the end of the pad (not as good as two vias, > or via in pad), and locating the caps too far from the chip, and having a good > bypass solution for the fpga, and forgetting all of the other really new high > speed chips on the board that no one told you also need even better bypass > solutions. Austin please elaborate on the common mistakes!! Not knowing any better I have always heard the following What is the recommended way to connect decoupling caps??? "To provide proper decoupling, connection should be made from the device Vcc or GND pin to the decoupling cap, then from the cap to the Vcc or GND plane. and placing SMT caps on the opposite side of the board from the SMT devices, two vias are required per connection, one to get from the SMT device to the cap and another to get from the cap to the plane. A better solution is to move the caps to the top side of the board where possible." Thanks Bill ###### From: rickman Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Wed, 21 Nov 2001 23:21:24 -0500 Lines: 52 Message-ID: <3BFC7D44.8A9C96CA@yahoo.com> References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: UmFuZG9tSVakvB1f85h37wpqzp/LXzPz8X9MXRlflYie4SSqBu37NsbEO5Xd7GAl X-Complaints-To: abuse@rcn.com NNTP-Posting-Date: 22 Nov 2001 04:21:21 GMT X-Mailer: Mozilla 4.7 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!newsfeeder.inwind.it!inwind.it!nntp.infostrada.it!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!feed1.news.rcn.net!rcn!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11750 Rick Filipkiewicz wrote: > > If the the rule that high speed decouplers should be placed as close as > possible to the chip's power pins [I've heard ~1cm] isn't just more voodoo > then its rationale must be inductance again ? I am not clear what you are saying here. I was not saying that it is good to be inductive. I am saying that it does not matter if the cap is inductive, as long as the total impedance (including any trace impedance) is low. The impedance finds a sharp minimum at the self resonant frequency and then starts increasing again as frequency increases. Above this self resonant frequency the cap is net inductive. But the cap is still an effective decoupling component until the impedance rises enough to interfere with its operation. This can easily be 10X the freq of self inductance. > One other query I've got is that it seems that what's called decoupling > really covers 2 things: > > o Stopping high frequency noise generated externally from getting into the > chip via the power pins. > > o Dealing with self-injected noise from the chip driving very fast edges > into capacitive loads. > > In the second case, with edges in the 1-2 nsec range or faster it would > appear to me that the frequencies we are dealing with have 500MHz+ > components. In other words even 0402 caps will appear inductive ? When you say "driving very fast edges into capacitive loads" I assume you are talking about the current spike required from the power bus to change the voltage on an output. Yes this has very fast frequency components. But the impedance of a cap is still effective in reducing the amplitude of the voltage spike on the power bus even when the cap is above the self resonant freq. The AVX chart shows an 0805 MLCC cap as having about 3 or 4 ohms impedance at 500 Mhz. With some 20 mA switching on that power pin, you will see less than 0.1 volt of noise. The fact that it is inductive reactance does not matter! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ###### From: "Philippe Robert" Newsgroups: comp.arch.fpga References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> Subject: Re: Decoupling capacitors on Virtex II Date: Thu, 22 Nov 2001 09:38:02 -0000 Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 NNTP-Posting-Host: 213.254.164.196 Message-ID: <3bfcc90f@peer1.news.newnet.co.uk> X-Trace: peer1.news.newnet.co.uk 1006422287 213.254.164.196 (22 Nov 2001 09:44:47 GMT) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!teaser.fr!proxad.net!news-hub.cableinet.net!blueyonder!newspeer.clara.net!news.clara.net!peer1.news.newnet.co.uk Xref: chonsp.franklin.ch comp.arch.fpga:11769 Hi, I am more like in the VHDL engineer...and let me tell you that you guys give me hard work to follow all that you say !!! But it is very interesting. I have ordered the book that HW Johnson wrote. I think I will need to spend a bit of time reading it. > Hmm, try redestributiing the capacitance into less caps, but dont forget to > use small ones (10nF or lower) for the "really" high frequencys. In > microwave engineering they use sometimes even 100pF instead of 1nF because > of the lower inductance. > And dont forget a good ground-VCC planes. In your layer stacking, the > GND-VCC planes should be close together, forming a superb high frequncy > capacitor. Is it a question of impedance between the two planes ? Thanks again to all of you for your help. Philippe. ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 22 Nov 2001 13:39:48 +0000 Organization: TRW Automotive Technical Centre Lines: 30 Sender: Thompsm@977845-DT Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> <3BFC7D44.8A9C96CA@yahoo.com> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1006436207 3018836 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!16147!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11749 rickman writes: > When you say "driving very fast edges into capacitive loads" I assume > you are talking about the current spike required from the power bus to > change the voltage on an output. Yes this has very fast frequency > components. But the impedance of a cap is still effective in reducing > the amplitude of the voltage spike on the power bus even when the cap is > above the self resonant freq. The AVX chart shows an 0805 MLCC cap as > having about 3 or 4 ohms impedance at 500 Mhz. With some 20 mA switching > on that power pin, you will see less than 0.1 volt of noise. The fact > that it is inductive reactance does not matter! > Just be careful that the way you mount the capacitors doesn't add too muc more inductance to the capacitor's inherent inductance. Vias on the end of traces from the cap pads can be 4nH. My last design I had caps mounted on a large plane pad with several (3-4) vias through each end. This should add 1nH ish. Then you are relying on the planes having a low spreading inductance to deliver the power to the chip, which must also be mounted on *really* short traces. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Thu, 22 Nov 2001 14:29:16 -0800 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> <3BFC7D44.8A9C96CA@yahoo.com> X-Newsreader: Forte Agent 1.6/32.525 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 53 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!hub1.nntpserver.com!telocity-west!TELOCITY!sn-xit-03!sn-post-02!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11770 On 22 Nov 2001 13:39:48 +0000, Martin Thompson wrote: > >Just be careful that the way you mount the capacitors doesn't add too >muc more inductance to the capacitor's inherent inductance. Vias on >the end of traces from the cap pads can be 4nH. My last design I had >caps mounted on a large plane pad with several (3-4) vias through each >end. This should add 1nH ish. > >Then you are relying on the planes having a low spreading inductance >to deliver the power to the chip, which must also be mounted on >*really* short traces. > >Cheers, >Martin Martin, I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3 volt island was part of a split plane (3.3 under fpga's, 5 volt plane elsewhere) with a 0.005 inch dielectric between power plane and ground plane. Just for fun, I designed a few SMA connector footprints into the board so I could access the power planes. On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt pours looked, as near as I could measure, like ideal capacitors of the expected values, with just a tad of inductance at the SMA connector transition. Otherwise, no sign of ringing or edge effects. I then started adding the bypass caps, here and there. As close as I could measure, the effective capacitance increased by the added C value, no matter where I put them. Again, no sign of ringing or distance effects. So I conclude that the planes themselves are the ultimate high-speed bypass, and the caps provide the longer-term energy storage. After all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty low-impedance thing. So we put maybe four 0805, 0.1 uf ceramics per FPGA, one per every few smaller chips, and a couple of 10 volt tantalums per board, and don't worry much about exactly where they go. Manufacturing hates vias in pads, so we extend a short 20 mil trace before we hit the via. On a running board, measuring the signals at the SMA connectors verifies that things are quiet. Given this, the often cited Sun papers are pretty much nonsense; they fixate on simulating caps but ignore the planes. John ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 23 Nov 2001 09:46:18 +0000 Organization: TRW Conekt Lines: 68 Sender: Thompsm@977845-DT Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> <3BFC7D44.8A9C96CA@yahoo.com> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1006508593 3282101 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!119905!news.imp.ch!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11748 John Larkin writes: > I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3 > volt island was part of a split plane (3.3 under fpga's, 5 volt plane > elsewhere) with a 0.005 inch dielectric between power plane and ground > plane. Just for fun, I designed a few SMA connector footprints into > the board so I could access the power planes. > That was something I had pondered doing recently also, glad someone else did the hard work though :-) > On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt > pours looked, as near as I could measure, like ideal capacitors of the > expected values, with just a tad of inductance at the SMA connector > transition. Otherwise, no sign of ringing or edge effects. > As expected with a 5thou spacing. Things get a bit more tricky is you are doing 4 layer 1.6mm boards, as the spreading inductance gets more significant then. > I then started adding the bypass caps, here and there. As close as I > could measure, the effective capacitance increased by the added C > value, no matter where I put them. Again, no sign of ringing or > distance effects. > > So I conclude that the planes themselves are the ultimate high-speed > bypass, and the caps provide the longer-term energy storage. After > all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty > low-impedance thing. > And so long as the caps are closer (in time) than the edge you are trying to support, things are fine! For example if we take speed of propogation equal to 1/2 speed of light in free space (which is conservative), a 1ns edge is 15 cm "long", so if your caps are within 7.5cm the edge will "see" them fine. Or is my physics flawed? > So we put maybe four 0805, 0.1 uf ceramics per FPGA, one per every few > smaller chips, and a couple of 10 volt tantalums per board, and don't > worry much about exactly where they go. Manufacturing hates vias in > pads, so we extend a short 20 mil trace before we hit the via. On a > running board, measuring the signals at the SMA connectors verifies > that things are quiet. > I didn;t end up putting the vias in the pads, just extended a plane fill out from the pad and stuck the vias in there. This may have been no better than a trace, but it made it easier to get multiple vias in. You results imply that that might be overkill anyway though. > Given this, the often cited Sun papers are pretty much nonsense; they > fixate on simulating caps but ignore the planes. > I wouldn't go as far as nonsense (but then I'm not a PDS guru), but I agree that the planes are neglected in the one I have next to me. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: Fri, 23 Nov 2001 10:36:53 -0800 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> <3BFC7D44.8A9C96CA@yahoo.com> X-Newsreader: Forte Agent 1.6/32.525 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 68 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-01!supernews.com!news.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11772 On 23 Nov 2001 09:46:18 +0000, Martin Thompson wrote: >John Larkin writes: > > >> I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3 >> volt island was part of a split plane (3.3 under fpga's, 5 volt plane >> elsewhere) with a 0.005 inch dielectric between power plane and ground >> plane. Just for fun, I designed a few SMA connector footprints into >> the board so I could access the power planes. >> > >That was something I had pondered doing recently also, glad someone >else did the hard work though :-) > >> On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt >> pours looked, as near as I could measure, like ideal capacitors of the >> expected values, with just a tad of inductance at the SMA connector >> transition. Otherwise, no sign of ringing or edge effects. >> > >As expected with a 5thou spacing. Things get a bit more tricky is you >are doing 4 layer 1.6mm boards, as the spreading inductance gets more >significant then. > Even on 4-layer boards, we specify a very thin dielectric layer between the power and ground planes to get the best plane effects. The PCB fab houses don't seem to mind. >> I then started adding the bypass caps, here and there. As close as I >> could measure, the effective capacitance increased by the added C >> value, no matter where I put them. Again, no sign of ringing or >> distance effects. >> >> So I conclude that the planes themselves are the ultimate high-speed >> bypass, and the caps provide the longer-term energy storage. After >> all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty >> low-impedance thing. >> > >And so long as the caps are closer (in time) than the edge you are >trying to support, things are fine! For example if we take speed of >propogation equal to 1/2 speed of light in free space (which is >conservative), a 1ns edge is 15 cm "long", so if your caps are within >7.5cm the edge will "see" them fine. Or is my physics flawed? The TDR we used has a net risetime of about 30 ps, or about 0.1" resolution inside FR4. Yes, it surprised me that the bypass cap location made no discernable difference to the impedance seen at the SMA test point. I think the FR4 material is lossy enough to smear out any reflections (or, in the frequency domain, kill the Q of any resonances, which would be well into the GHz range here). I embarked on this because (besides it being fun) I had just finished a board that, using the usual ROTs, had something like 200 bypass caps, and it occurred to me that a) this was silly and b) I had never designed a multilayer board that actually failed because of insufficient logic bypasses. Hey, I'm an engineer; I don't have to understand it, I only have to make it work! John ###### From: Martin Thompson Newsgroups: comp.arch.fpga Subject: Re: Decoupling capacitors on Virtex II Date: 26 Nov 2001 09:43:58 +0000 Organization: TRW Conekt Lines: 43 Sender: Thompsm@977845-DT Message-ID: References: <3bebb7ef$1@peer1.news.newnet.co.uk> <9sh63h$1249vl$1@ID-84877.news.dfncis.de> <1476aea8.0111190631.44d5adef@posting.google.com> <3BF9233E.64D3DFFC@yahoo.com> <3BFC4849.240265B9@algor.co.uk> <3BFC7D44.8A9C96CA@yahoo.com> NNTP-Posting-Host: 194.74.228.66 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: fu-berlin.de 1006767638 4923948 194.74.228.66 (16 [98603]) User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.1 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.mailgate.org!skynet.be!skynet.be!fu-berlin.de!uni-berlin.de!194.74.228.66!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11819 John Larkin writes: > > Even on 4-layer boards, we specify a very thin dielectric layer > between the power and ground planes to get the best plane effects. The > PCB fab houses don't seem to mind. > How thin do you go on 4 layer boards? And what track widths/impedances/heights above planes do you end up with on the tracking layer? > > The TDR we used has a net risetime of about 30 ps, or about 0.1" > resolution inside FR4. Yes, it surprised me that the bypass cap > location made no discernable difference to the impedance seen at the > SMA test point. I think the FR4 material is lossy enough to smear out > any reflections (or, in the frequency domain, kill the Q of any > resonances, which would be well into the GHz range here). > FR4 is certainly more lossy at those sort of frequencies. And the skin effect will cause resistive losses also I imagine. > I embarked on this because (besides it being fun) I had just finished > a board that, using the usual ROTs, had something like 200 bypass > caps, and it occurred to me that a) this was silly and b) I had never > designed a multilayer board that actually failed because of > insufficient logic bypasses. > :-) Good reasons! > Hey, I'm an engineer; I don't have to understand it, I only have to > make it work! > Once we understand it we can then persuade others that they don't 200 caps also.... Cheers, Martin