From: ndeshmukh@yahoo.com (nitin) Newsgroups: comp.arch.fpga Subject: Carry chain in Virtex II Date: 9 Nov 2001 00:47:14 -0800 Organization: http://groups.google.com/ Lines: 15 Message-ID: <7685aa5c.0111090047.1f62ab47@posting.google.com> NNTP-Posting-Host: 164.129.1.38 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1005295634 14411 127.0.0.1 (9 Nov 2001 08:47:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 9 Nov 2001 08:47:14 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11432 Anybody have any ideas why Virtex II CLB has two carry chains passing through it linking two slices and each and propagating in columns from top to bottom...? Why didn't they link all fourslices in just one chain and joined CLBs in one column together and so on in different columns... It would be nice if some one with some insight into this matter can shed some light on it... Thanx in advance... Ciao, Nitin ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Carry chain in Virtex II Date: 10 Nov 2001 19:54:00 +0100 Organization: My own Private Self Lines: 56 Message-ID: <6ulmhefodz.fsf@chonsp.franklin.ch> References: <7685aa5c.0111090047.1f62ab47@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005418440 506 10.0.3.2 (10 Nov 2001 18:54:00 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 10 Nov 2001 18:54:00 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11445 ndeshmukh@yahoo.com (nitin) writes: > Anybody have any ideas why Virtex II CLB has two carry chains passing > through it linking two slices and each and propagating in columns from > top to bottom...? > > Why didn't they link all fourslices in just one chain and joined CLBs > in one column together and so on in different columns... Well this is spaeculation (but well founded). In the original Virtex there ae 2 slices and also 2 carry chains, each going CLB to CLB taking only one slice per CLB. Studying the info in XAPP151 is becomes obvious that the actial transistors are layed out in an "butterfly" configuration, with the 2 slices left and right of the routing! Sort of like this: .----|----|||||----|----. | .--|--. ||||| .--|--. | | | C | ||||| | C | | | `--|--' ||||| `--|--' | | Slice 1 ||||| Slice 0 | | | ||||| | | CLB | | ||||| | | -----|-----||------|----- -----|-------|-----|----- -----|------|||----|----- -----|-----||------|----- routing - and | -----|-------||----|----- -----|----||-------|----- | | ||||| | | `----|----|||||----|----' carry1^ ^carry0 So having carry going through both slices would require it to meander through the chip, massively increasing distance and so slowing it down. I suspect Virtex-2 to have 2 slices each side of routing, so I assume this to also apply there. > It would be nice if some one with some insight into this matter can > shed some light on it... Hope it helped. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: ndeshmukh@yahoo.com (nitin) Newsgroups: comp.arch.fpga Subject: Re: Carry chain in Virtex II Date: 12 Nov 2001 01:22:53 -0800 Organization: http://groups.google.com/ Lines: 61 Message-ID: <7685aa5c.0111120122.1669b40c@posting.google.com> References: <7685aa5c.0111090047.1f62ab47@posting.google.com> <6ulmhefodz.fsf@chonsp.franklin.ch> NNTP-Posting-Host: 164.129.1.38 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1005556973 5704 127.0.0.1 (12 Nov 2001 09:22:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 12 Nov 2001 09:22:53 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11493 Hi... well i suppose the floor planning of the slices within a CLB is driven by the fact that they were going to have two carry chains through it... so they put two this side & two that side... other wise why not all four in a column...? Ciao, Nitin. Neil Franklin wrote in message news:<6ulmhefodz.fsf@chonsp.franklin.ch>... > ndeshmukh@yahoo.com (nitin) writes: > > > Anybody have any ideas why Virtex II CLB has two carry chains passing > > through it linking two slices and each and propagating in columns from > > top to bottom...? > > > > Why didn't they link all fourslices in just one chain and joined CLBs > > in one column together and so on in different columns... > > Well this is spaeculation (but well founded). > > In the original Virtex there ae 2 slices and also 2 carry chains, > each going CLB to CLB taking only one slice per CLB. > > Studying the info in XAPP151 is becomes obvious that the actial > transistors are layed out in an "butterfly" configuration, with the 2 > slices left and right of the routing! > > Sort of like this: > > > .----|----|||||----|----. > | .--|--. ||||| .--|--. | > | | C | ||||| | C | | > | `--|--' ||||| `--|--' | > | Slice 1 ||||| Slice 0 | > | | ||||| | | CLB > | | ||||| | | > -----|-----||------|----- > -----|-------|-----|----- > -----|------|||----|----- > -----|-----||------|----- routing - and | > -----|-------||----|----- > -----|----||-------|----- > | | ||||| | | > `----|----|||||----|----' > carry1^ ^carry0 > > > So having carry going through both slices would require it to meander > through the chip, massively increasing distance and so slowing it down. > > I suspect Virtex-2 to have 2 slices each side of routing, so I assume > this to also apply there. > > > > It would be nice if some one with some insight into this matter can > > shed some light on it... > > Hope it helped. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Carry chain in Virtex II Date: 12 Nov 2001 21:19:08 +0100 Organization: My own Private Self Lines: 32 Message-ID: <6u7ksvg2tf.fsf@chonsp.franklin.ch> References: <7685aa5c.0111090047.1f62ab47@posting.google.com> <6ulmhefodz.fsf@chonsp.franklin.ch> <7685aa5c.0111120122.1669b40c@posting.google.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1005596348 413 10.0.3.2 (12 Nov 2001 20:19:08 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 12 Nov 2001 20:19:08 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11501 ndeshmukh@yahoo.com (nitin) writes: > well i suppose the floor planning of the slices within a CLB is > driven by the fact that they were going to have two carry chains > through it... so they put two this side & two that side... other wise > why not all four in a column...? Because the aspect ration of the CLBs would get problematic. XC3000 and XC4000 have 2x1 LUTs/CLB XC5200 has 4x1 LUTs/CLB Virtex has 2x2 LUTs/CLB Virtex-2 has 4x2 LUTs/CLB Having a "square" was obviously considered better in Virtex. And 4x2 is the nearest possible with 8 LUTs/CLB. Do not forget that having "high" CLBs with 8x1 ratio would result in less dense horizontal wiring, or require wider (and so asymmetrical) wiring bundles in horizontal direction. Alteras FLEX chips actually do this so (8x1 or 10x1), because they are adapted CPLD designs (with the product term array replaced by PIPs and the ORs replaced by LUTs). OTOH Atmel has 1x1 CLBs. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: ndeshmukh@yahoo.com (nitin) Newsgroups: comp.arch.fpga Subject: Re: Carry chain in Virtex II Date: 15 Nov 2001 02:04:28 -0800 Organization: http://groups.google.com/ Lines: 34 Message-ID: <7685aa5c.0111150204.4d37e078@posting.google.com> References: <7685aa5c.0111090047.1f62ab47@posting.google.com> <6ulmhefodz.fsf@chonsp.franklin.ch> <7685aa5c.0111120122.1669b40c@posting.google.com> <6u7ksvg2tf.fsf@chonsp.franklin.ch> NNTP-Posting-Host: 164.129.1.38 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1005818668 8364 127.0.0.1 (15 Nov 2001 10:04:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Nov 2001 10:04:28 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!37481047!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11604 Hi... Yeah i guess this should be the reason. Thanx... Ciao, Nitin. Neil Franklin wrote in message news:<6u7ksvg2tf.fsf@chonsp.franklin.ch>... > ndeshmukh@yahoo.com (nitin) writes: > > > well i suppose the floor planning of the slices within a CLB is > > driven by the fact that they were going to have two carry chains > > through it... so they put two this side & two that side... other wise > > why not all four in a column...? > > Because the aspect ration of the CLBs would get problematic. > > XC3000 and XC4000 have 2x1 LUTs/CLB > XC5200 has 4x1 LUTs/CLB > Virtex has 2x2 LUTs/CLB > Virtex-2 has 4x2 LUTs/CLB > > Having a "square" was obviously considered better in Virtex. And 4x2 > is the nearest possible with 8 LUTs/CLB. > > Do not forget that having "high" CLBs with 8x1 ratio would result in > less dense horizontal wiring, or require wider (and so asymmetrical) > wiring bundles in horizontal direction. > > Alteras FLEX chips actually do this so (8x1 or 10x1), because they > are adapted CPLD designs (with the product term array replaced by > PIPs and the ORs replaced by LUTs). > > OTOH Atmel has 1x1 CLBs.