From: bazaillion@yahoo.com Newsgroups: comp.arch.fpga Subject: How dense are FPGA/CPLD's Date: Sat, 03 Nov 2001 20:04:51 GMT Organization: Posted via Supernews, http://www.supernews.com Message-ID: <3be44c04.109339469@news.charter.net> X-Newsreader: Forte Free Agent 1.21/32.243 X-Complaints-To: newsabuse@supernews.com Lines: 18 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11186 Hello, I am new to FPGA/PLA/CPLD technology. I have a couple questions about them. (1) How dense can you get these (How many gates)? (2) Hiw much are they typically if you are buy small quantities 1-5 for prototyping? (3) Are they dense enough to build a CPU or a 3d VGA display chip with these? or maybe multiple chips. Thanks, -M. Bazaillion ###### From: Rene Tschaggelar Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: Sun, 04 Nov 2001 23:29:35 +0100 Organization: Ing.Buero R.Tschaggelar Lines: 41 Message-ID: <3BE5C14F.5987DA5F@dplanet.ch> References: <3be44c04.109339469@news.charter.net> NNTP-Posting-Host: dialup-61-71.dplanet.ch Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: duba04h09-0.dplanet.ch 1004912686 20908 212.35.61.71 (4 Nov 2001 22:24:46 GMT) X-Complaints-To: usenet@dplanet.ch NNTP-Posting-Date: 4 Nov 2001 22:24:46 GMT X-Mailer: Mozilla 4.5 [en] (WinNT; I) X-Accept-Language: en,de-CH Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.dplanet.ch!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11207 They range from a few dozend FF = a few hundred gates to several millions. There are EEPROM based chips and SRAM based chips. The boundary is somwhere at 128 FF's. The higher density ones use SRAM then. For small scale development, the chip costs are nil compared to the time and perhaps money spent on the software. eg 20$ for 30k gates. Yes, you can build a cpu or a 3D engine, but these are not the projects to start with. A thick chip with 10million gates also requires a thick machine with 1G RAM and software for a few k$. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com bazaillion@yahoo.com wrote: > > Hello, > > I am new to FPGA/PLA/CPLD technology. > > I have a couple questions about them. > > (1) How dense can you get these (How many gates)? > > (2) Hiw much are they typically if you are buy small quantities 1-5 > for prototyping? > > (3) Are they dense enough to build a CPU or a 3d VGA display chip > with these? or maybe multiple chips. > > Thanks, > -M. Bazaillion ###### From: kevinbraceusenet@hotmail.com (Kevin Brace) Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: 4 Nov 2001 22:40:24 -0800 Organization: http://groups.google.com/ Lines: 151 Message-ID: References: <3be44c04.109339469@news.charter.net> NNTP-Posting-Host: 4.54.125.167 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1004942424 18993 127.0.0.1 (5 Nov 2001 06:40:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 5 Nov 2001 06:40:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11222 bazaillion@yahoo.com wrote in message news:<3be44c04.109339469@news.charter.net>... > Hello, > > I am new to FPGA/PLA/CPLD technology. > > I have a couple questions about them. > > > (1) How dense can you get these (How many gates)? > Although, I don't use a CPLD myself, a fairly large CPLD can fit about 10,000 gates. Most CPLDs are EEPROM-based, which means that it can be reprogramed a lot of times, and it will be active immediately upon power on. Manufacturers of CPLD include Altera (http://www.altera.com), Cypress (http://www.cypress.com), Lattice (http://www.latticesemi.com), and Xilinx (http://www.xilinx.com). Most FPGAs are much larger than CPLDs. However, manufacturers of FPGAs really have a bad habit of inflating the gate count the chip can realistically fit. For example, an FPGA I use called Xilinx Spartan-II 150,000 "system gate" part (XC2S150), although Xilinx (http://www.xilinx.com) claims that part can fit 150,000 "system gates", the realistical gate count (not using vendor proprietary features) is about 30,000 to 35,000 gates. Yes, Xilinx's "system gate" inflates the realistically achievable gate count by about 5 times. Xilinx's rival Altera (http://www.altera.com) also inflates the gate count, but in my opinion, the gate count inflation seems to be about 2 to 3 times. Spartan-IIs are low-end FPGAs, but a high-end FPGA like Xilinx Virtex-II 6M system gate part (XC2V6000) should be able to fit more than 1M realistical gates, if my assumption is correct. Xilinx and Altera FPGAs are based on SRAM, so a Configuration PROM (EEPROM based) has to be attached to program the FPGA when the power is turned on. There are other FPGA manufacturers that make FPGAs based on antifuse like Actel (http://www.actel.com) and Quicklogic (http://www.quicklogic.com), but antifuse FPGA I think are hard to use for prototyping because once you program antifuse FPGAs, it cannot be programmed again. That's because in antifuse FPGAs, you burn off fuses inside the FPGA to program the FPGA. Nowadays, antifuse FPGAs are not popular as SRAM FPGAs, because their density is relatively small compared to SRAM FPGAs, and hard to use for prototyping. > (2) Hiw much are they typically if you are buy small quantities 1-5 > for prototyping? Let's say that you want to purchase one Xilinx Spartan-II 150,000 "system gate" part (XC2S150) from a Xilinx distributor. At Insight Electronics order website (http://www.insight-electronics.com/order/index.html), you can type in a part number. If you type in XC2S150, it gives you a list of various XC2S150 with different package options and speed grades. Yes, because Spartan-IIs are geared as a low-cost FPGA, it only costs between $20 to $40 per chip. You also have to purchase a Configuration PROM (XC18V01), which costs about $23. However, if you try to buy a high-end FPGA like Xilinx Virtex-II 6M system gate part (type in XC2V6000), only one chip will cost you between $4,000 to $6,000. Yes, $4,000 to $6,000 may sound a lot, but for some applications where the production volume is extremely small (let's say a specialized communication equipment), buying a couple of Virtex-IIs will likely be cheaper than fabricating a custom chip (an ASIC). Recent FPGAs use packages like PQFP or BGA, which requires a specialized equipment to solder it onto a PCB (especially BGA package). Therefore, I think it will be much more practical to purchase a prototype board with an FPGA on it. My recommendation will be that you should pick up one from Insight Electronics (http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml) with Spartan-II on it. One of them is a standalone one with Spartan-II on it, and one with a Spartan-II on a PCI card (the one I use). For design tools, you can use Xilinx ISE WebPack which is free, supports all Spartan-II devices, and comes with a simulator called ModelSim XE-Starter. I think you should not initially consider paying for tools because if you paid $1,000 for tools, and you didn't like designing hardware with an FPGA afterall, you will still be holding the bag with useless software. At least a free tool won't have such a risk. Other CPLD and FPGA vendors also offer free design tools, but Xilinx is the only one that offers a free simulator. It is far easier to find bugs running a simulator than actually firing up the actual FPGA, especially as the design gets bigger and more complex. To design circuits for an FPGA, you should learn languages like Verilog or VHDL. I will recommend learning Verilog, but I am sure some people will say VHDL. It really doesn't matter which one you learn. One thing I can say from my experience is that a lot of books about Verilog and VHDL available out there are not well written. Examples inside the book are too trivial, too boring, or too difficult to understand. > > (3) Are they dense enough to build a CPU or a 3d VGA display chip > with these? or maybe multiple chips. > > Thanks, > -M. Bazaillion You can obtain some homegrown CPUs from websites like http://www.fpgacpu.org, http://www.free-ip.com, and http://www.opencores.org. Whether or not the CPUs use get from those websites are worthy playing around is another question. Those CPUs are pretty small, so they should be able to fit inside most Spartan-II based prototype boards. However, my guess is that you are thinking of whether or not an x86 processor might fit inside an FPGA. Probably a 4 to 5 years old x86 processor might fit inside one Xilinx Virtex-II 6M system gate part, and if one is not enough, you can use multiple of them. In fact, because of high cost of fabricating an ASIC, more designers use multiple of high density FPGAs to debug it initially before committing to an ASIC. That way you have less chance to making a mistake when creating an ASIC. At 0.18u process, it costs $300,000 of NRE (Non-Recurring Engineering) charge to fabricate an ASIC for volume production. At 0.13u process, NRE charge will approach $1 million . . . Even one small mistake can be fatal, because you are talking of paying another $300,000 (in 0.18u) to fabricate an ASIC for volume production. For a 3D graphics chip, again a 4 to 5 years old one should fit inside a Xilinx Virtex-II 6M system gate part, but you will have to put an external RAMDAC outside of the chip because an FPGA doesn't contain one (TI and IBM used to make high-end RAMDACs about 4 to 5 years ago). Regards, Kevin Brace (don't respond to me directly, respond within the newsgroup) ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: 05 Nov 2001 21:31:41 +0100 Organization: My own Private Self Lines: 111 Message-ID: <6u668pufgy.fsf@chonsp.franklin.ch> References: <3be44c04.109339469@news.charter.net> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 1004992303 580 10.0.3.2 (5 Nov 2001 20:31:43 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 5 Nov 2001 20:31:43 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:11231 kevinbraceusenet@hotmail.com (Kevin Brace) writes: > bazaillion@yahoo.com wrote in message news:<3be44c04.109339469@news.charter.net>... > > > > (1) How dense can you get these (How many gates)? > > Most FPGAs are much larger than CPLDs. > However, manufacturers of FPGAs really have a bad habit of inflating > the gate count the chip can realistically fit. > For example, an FPGA I use called Xilinx Spartan-II 150,000 "system > gate" part (XC2S150), although Xilinx (http://www.xilinx.com) claims > that part can fit 150,000 "system gates", the realistical gate count > (not using vendor proprietary features) is > about 30,000 to 35,000 gates. > Yes, Xilinx's "system gate" inflates the realistically achievable gate > count by about 5 times. > Xilinx's rival Altera (http://www.altera.com) also inflates the gate > count, but in my opinion, the gate count inflation seems to be about 2 > to 3 times. Perhaps a small hint at how these numbers got so inflated: In the days on FPGAs without BRAMs the numbers were fairly realistic. Since BRAMs the vendors "cheat" by counting them as an obscene amount of gates. Bad if you have no use for BRAMs. The difference you observe in Xilinx "times 5" and Altera "times 3" is due to Altera having less BRAMs. Example: The Xilinx data sheet for Virtex XCV200 (= Spartan-II XC2S200 sizewise) lists 236'000 system gates without further comment. But the XCV200E explicitely lists 306'000 system gates _and_ as 63'500 logic gates. As both of these have identical amounts of logic this gives you for XC2S200 1/3 logic part! > Spartan-IIs are low-end FPGAs, but a high-end FPGA like Xilinx > Virtex-II 6M system gate part (XC2V6000) should be able to fit more > than 1M realistical gates, if my assumption is correct. The factor is most likely larger, as they have even more BRAMs, not to forget them multipliers which also distort the "true" (= logic) numbers even more. > > (3) Are they dense enough to build a CPU or a 3d VGA display chip > > with these? or maybe multiple chips. > > However, my guess is that you are thinking of whether or not > an x86 processor might fit inside an FPGA. > Probably a 4 to 5 years old x86 processor might fit inside one Xilinx > Virtex-II 6M system gate part, and if one is not enough, you can use > multiple of them. My own calculations on this: Define XCV200 or XC2S200 to be 63'500 logic gates (= 254'000 transistors) plus 14 BRAMs a 4kbit (= 6kByte). That assuming all BRAMs as cache and none as logic. For an XCV1000 take 5 times logic (1'250'000 transitors) and 2 times cache. For an XCV3200E take 3 times logic (3'750'000 transistors) and annother 4 times cache. For an XC2V10000 (largest) take double logic (7'500'000 transistors). All the above factors taken from LUT count growth. This compares with Intel CPUs as follows: 80386 ca 250'000 transistors, no cache, all logic 80486 ca 1'000'000 transistors, >6*8*8k = ~300'000 of them for 8kByte cache, 700'000 lest for logic Pentium ca 3'500'000 transistors, >6*8*16k = ~600'000 for cache PentiumII 5'500'000 transistors, cache most likely irrelevant So a XC2S200 is basically a 386 with an 486es cache. XCV1000 is about an dual 486. XCV3200E is a bit better than Pentium. XC2V10000 should even have reserves on an PII. All that is assuming that you do not want to downgrade the logic gate numbers by about 1.5. Speed seems to be also about same ballpark of 30..100MHz for 368/486 in the XC2S200, but lagging when comparing XCV3200E with the fastest Pentiums of 266MHz or XC2V10000 with 4/500MHz PIIs. I suppose it is the routing PIPs in the FPGAs that are losing us the speed race. P.S. I am presently implementing[1] an DEC PDP-10 1970s mainframe, aiming for an XC2S200 or XCV300, and seem to be at the right size. That is for processor and all peripherals. But I am using JBits tool, which is very space efficient, but a lot of work to use. [1] http://neil.franklin.ch/Projects/PDP-10/ > to put an external RAMDAC outside of the chip because an FPGA doesn't > contain one (TI and IBM used to make high-end RAMDACs about 4 to 5 > years ago). Try Brooktree. They seem to be the large RAMDAC people these days. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: Rene Tschaggelar Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: Wed, 07 Nov 2001 21:03:47 +0100 Organization: Ing.Buero R.Tschaggelar Lines: 25 Message-ID: <3BE993A3.F854175D@dplanet.ch> References: <3be44c04.109339469@news.charter.net> NNTP-Posting-Host: dialup-53-213.dplanet.ch Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: duba04h09-0.dplanet.ch 1005163436 24108 212.35.53.213 (7 Nov 2001 20:03:56 GMT) X-Complaints-To: usenet@dplanet.ch NNTP-Posting-Date: 7 Nov 2001 20:03:56 GMT X-Mailer: Mozilla 4.5 [en] (WinNT; I) X-Accept-Language: en,de-CH Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.dplanet.ch!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11300 A few corrections : Altera FPGA's can be EEPROM or SRAM based depending on the density. I wouldn't learn Verilog nor VHDL to start with but use the graphic editors provided. They allow rather complex stuff and are self-documenting. Rene Kevin Brace wrote: > > Xilinx and Altera FPGAs are based on SRAM, so a Configuration PROM > (EEPROM based) has to be attached to program the FPGA when the power > is turned on. > To design circuits for an FPGA, you should learn languages like > Verilog or VHDL. > I will recommend learning Verilog, but I am sure some people will say > VHDL. ###### From: kevinbraceusenet@hotmail.com (Kevin Brace) Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: 7 Nov 2001 19:35:23 -0800 Organization: http://groups.google.com/ Lines: 42 Message-ID: References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> NNTP-Posting-Host: 4.54.124.224 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1005190523 20091 127.0.0.1 (8 Nov 2001 03:35:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 8 Nov 2001 03:35:23 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11353 Rene Tschaggelar wrote in message news:<3BE993A3.F854175D@dplanet.ch>... > A few corrections : > > Altera FPGA's can be EEPROM or SRAM based depending on the density. > As far as I know, all FPGA devices from Altera are SRAM-based. Perhaps you are talking about MAX series which is EEPROM-based, but I will call MAX a CPLD because they are product term based devices. Although it is not always correct, I still think it is a fairly accurate way to categorize programmable devices that most CPLDs are based on EEPROM and most FPGAs are based on SRAM or antifuse. Occasionally there is an exception like Actel/GateField's EEPROM-based FPGA called ProASIC. It looks like an interesting device, but I don't hear or see it that often. > I wouldn't learn Verilog nor VHDL to start with but use the graphic > editors provided. They allow rather complex stuff and are > self-documenting. > > > Rene > > > I think that depends on the person. I find HDL easier to work than with schematic entry. I don't have any good memories of working with schematic entry. Especially, if you have to design a state machine. Regards, Kevin Brace (don't respond to me directly, respond within the newsgroup) ###### Message-ID: <3BEA5DFB.55BC544E@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 203.134.138.188 Organization: iPrimus Australia - http://www.iprimus.com.au Lines: 46 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Thu, 08 Nov 2001 21:27:07 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1005215205 203.134.67.67 (Thu, 08 Nov 2001 21:26:45 EST) NNTP-Posting-Date: Thu, 08 Nov 2001 21:26:45 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!2599062!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!skynet.be!skynet.be!news-out.visi.com!hermes.visi.com!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:11331 Kevin Brace wrote: > > Rene Tschaggelar wrote in message news:<3BE993A3.F854175D@dplanet.ch>... > > A few corrections : > > > > Altera FPGA's can be EEPROM or SRAM based depending on the density. > > > > As far as I know, all FPGA devices from Altera are SRAM-based. > Perhaps you are talking about MAX series which is EEPROM-based, but I > will call MAX a CPLD because they are product term based devices. > Although it is not always correct, I still think it is a fairly > accurate way to categorize programmable devices that most CPLDs are > based on EEPROM and most FPGAs are based on SRAM or antifuse. > Occasionally there is an exception like Actel/GateField's EEPROM-based > FPGA called ProASIC. There's a .pdf on the altera site that categorizes FPGAs as things with segmented interconnects, whereas CPLDs don't have segments, making routing easier. > It looks like an interesting device, but I don't hear or see it that > often. > > > I wouldn't learn Verilog nor VHDL to start with but use the graphic > > editors provided. They allow rather complex stuff and are > > self-documenting. > > > > > > Rene > > > > > > > > I think that depends on the person. > I find HDL easier to work than with schematic entry. > I don't have any good memories of working with schematic entry. > Especially, if you have to design a state machine. > > Regards, > > Kevin Brace (don't respond to me directly, respond within the > newsgroup) ###### Message-ID: <3BEA9A8E.45B7B465@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> <3BEA5DFB.55BC544E@iprimus.com.au> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 26 Date: Thu, 08 Nov 2001 14:40:22 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 1005230422 24.13.238.93 (Thu, 08 Nov 2001 06:40:22 PST) NNTP-Posting-Date: Thu, 08 Nov 2001 06:40:22 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!6736!news.imp.ch!uni-erlangen.de!fu-berlin.de!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11316 THat's pretty funny coming from Altera. If you look at the routing structure of an Altera FPGA, it looks remarkably CPLD-like. I think a better definition would focus on the structure of the logic elements. FPGAs tend to have small logic elements, typically 4 inputs where CPLDs tyupically have fairly wide and-or structures reminiscent of the original MMI PALs Russell Shaw wrote: > > There's a .pdf on the altera site that categorizes FPGAs as things > with segmented interconnects, whereas CPLDs don't have segments, > making routing easier. > > -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759 ###### Message-ID: <3BEAAC84.C422C6BE@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> <3BEA5DFB.55BC544E@iprimus.com.au> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 19 Date: Thu, 08 Nov 2001 16:02:19 GMT NNTP-Posting-Host: 209.179.247.142 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1005235339 209.179.247.142 (Thu, 08 Nov 2001 08:02:19 PST) NNTP-Posting-Date: Thu, 08 Nov 2001 08:02:19 PST Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Thu, 08 Nov 2001 07:58:19 PST (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!deine.net!newsfeed.direct.ca!look.ca!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11326 Russell Shaw wrote: > > There's a .pdf on the altera site that categorizes FPGAs as things > with segmented interconnects, whereas CPLDs don't have segments, > making routing easier. Beware of marketing fluff. They just wanted to indicate a distinction from Xilinx, while the two companies were embroiled in a patent war. "If it looks like an FPGA, behaves like an FPGA, is generally considered to be an FPGA", then they might as well call it an FPGA, and admit that they copied the Xilinx concept. Well, the patent fight is settled. Altera paid up, and perhaps they will now use a more reasonable nomenclature. Peter Alfke ###### Message-ID: <3BEB1B6F.60B00C6D@iprimus.com.au> From: Russell Shaw X-Mailer: Mozilla 4.75 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> <3BEA5DFB.55BC544E@iprimus.com.au> <3BEAAC84.C422C6BE@earthlink.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: 203.134.138.248 Organization: iPrimus Australia - http://www.iprimus.com.au Lines: 20 X-Original-NNTP-Posting-Host: 127.0.0.1 Date: Fri, 09 Nov 2001 10:55:27 +1100 NNTP-Posting-Host: 203.134.67.67 X-Trace: news0.optus.net.au 1005263693 203.134.67.67 (Fri, 09 Nov 2001 10:54:53 EST) NNTP-Posting-Date: Fri, 09 Nov 2001 10:54:53 EST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed1.cidera.com!Cidera!newsfeed.media.kyoto-u.ac.jp!news1.optus.net.au!optus!news0.optus.net.au!news.iprimus.com.au Xref: chonsp.franklin.ch comp.arch.fpga:11397 Peter Alfke wrote: > > Russell Shaw wrote: > > > > > There's a .pdf on the altera site that categorizes FPGAs as things > > with segmented interconnects, whereas CPLDs don't have segments, > > making routing easier. > > Beware of marketing fluff. > They just wanted to indicate a distinction from Xilinx, while the two companies were embroiled in a > patent war. > "If it looks like an FPGA, behaves like an FPGA, is generally considered to be an FPGA", then they > might as well call it an FPGA, and admit that they copied the Xilinx concept. > Well, the patent fight is settled. Altera paid up, and perhaps they will now use a more reasonable > nomenclature. What was the patent over? ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: How dense are FPGA/CPLD's Date: Thu, 08 Nov 2001 17:10:56 -0800 Organization: Xilinx Lines: 14 Message-ID: <3BEB2D20.B3431FAF@xilinx.com> References: <3be44c04.109339469@news.charter.net> <3BE993A3.F854175D@dplanet.ch> <3BEA5DFB.55BC544E@iprimus.com.au> <3BEAAC84.C422C6BE@earthlink.net> <3BEB1B6F.60B00C6D@iprimus.com.au> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en To: Russell Shaw Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:11374 Russell Shaw wrote: > What was the patent over? (This refers to the Xilinx vs Altera lawsuit.) I refuse to go into the merits and demerits of the case. But the main bone of contention was the Xilinx ( Ross Freeman ) patent #4 870 302 and its re-issue RE 34,363. I bet Altera would give you a different answer. Thank God it's over. Xilinx received a (token) $20M settlement from Altera. Only the lawyers got rich... Peter Alfke