From: donald.stauffer@kodak.com (Don Stauffer) Newsgroups: comp.arch.fpga Subject: Probing BGA Designs Date: 25 Oct 2001 14:46:55 -0700 Organization: http://groups.google.com/ Lines: 8 Message-ID: NNTP-Posting-Host: 165.170.128.66 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1004046416 25651 127.0.0.1 (25 Oct 2001 21:46:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 25 Oct 2001 21:46:56 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10963 Does anyone have experience debugging FPGA designs in BGA packages at the board-level? Since there are no pins, what have people found that works? Any ideas are greatly appreciated, including advice on DFT at the board level (unused I/O routed to test pins, SignalTap/ChipScope, etc.). Thanks, Don ###### From: Ben Popoola Newsgroups: comp.arch.fpga Subject: Re: Probing BGA Designs Date: Fri, 26 Oct 2001 11:29:29 +0100 Organization: University of Sussex Lines: 13 Message-ID: <3BD93B09.BB1D6569@sussex.ac.uk> References: NNTP-Posting-Host: engg100-63.engg.susx.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: ames.central.susx.ac.uk 1004091788 3539 139.184.100.63 (26 Oct 2001 10:23:08 GMT) X-Complaints-To: news@sussex.ac.uk NNTP-Posting-Date: Fri, 26 Oct 2001 10:23:08 +0000 (UTC) X-Mailer: Mozilla 4.78 [en] (WinNT; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!1215663!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!opentransit.net!newsfeed.icl.net!dispose.news.demon.net!demon!diablo.theplanet.net!btnet-peer!btnet!peer.news.eu-x.com!server2.netnews.ja.net!newshost.central.susx.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10909 Don Stauffer wrote: > Does anyone have experience debugging FPGA designs in BGA packages at > the board-level? Since there are no pins, what have people found that > works? Any ideas are greatly appreciated, including advice on DFT at > the board level (unused I/O routed to test pins, SignalTap/ChipScope, > etc.). > > Thanks, > Don ###### From: Ben Popoola Newsgroups: comp.arch.fpga Subject: Re: Probing BGA Designs Date: Fri, 26 Oct 2001 11:31:19 +0100 Organization: University of Sussex Lines: 18 Message-ID: <3BD93B77.2037E2E3@sussex.ac.uk> References: NNTP-Posting-Host: engg100-63.engg.susx.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: ames.central.susx.ac.uk 1004091898 3539 139.184.100.63 (26 Oct 2001 10:24:58 GMT) X-Complaints-To: news@sussex.ac.uk NNTP-Posting-Date: Fri, 26 Oct 2001 10:24:58 +0000 (UTC) X-Mailer: Mozilla 4.78 [en] (WinNT; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!dispose.news.demon.net!demon!diablo.theplanet.net!btnet-peer!btnet!peer.news.eu-x.com!server2.netnews.ja.net!newshost.central.susx.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10907 Hi, I suggested that you learn about the JTAG interface of IC's. A good place to start is the texas instruments web site (www.ti.com) and look for the downloadedable book ' The JTAG Primer' there. Ben Don Stauffer wrote: > Does anyone have experience debugging FPGA designs in BGA packages at > the board-level? Since there are no pins, what have people found that > works? Any ideas are greatly appreciated, including advice on DFT at > the board level (unused I/O routed to test pins, SignalTap/ChipScope, > etc.). > > Thanks, > Don ###### From: Mike Treseler Newsgroups: comp.arch.fpga Subject: Re: Probing BGA Designs Date: Fri, 26 Oct 2001 10:47:58 -0700 Organization: Fluke Networks Lines: 16 Message-ID: <3BD9A1CE.559A6897@flukenetworks.com> References: NNTP-Posting-Host: slick.tc.fluke.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.4.4-4GB i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!evrtwa1-snf1.gtei.net!news.gtei.net!fluke!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10936 Don Stauffer wrote: > > Does anyone have experience debugging FPGA designs in BGA packages at > the board-level? Since there are no pins, what have people found that > works? Any ideas are greatly appreciated, including advice on DFT at > the board level (unused I/O routed to test pins, SignalTap/ChipScope, > etc.). Have every BGA net (used or not) include a probeable pin, feedthru or other component. Have the vendor verify the bare board to the netlist before it is loaded. --Mike Treseler ###### From: "AME" Newsgroups: comp.arch.fpga Subject: Re: Probing BGA Designs Date: Fri, 26 Oct 2001 17:11:11 -0700 Organization: http://extra.newsguy.com Lines: 16 Message-ID: <9rcti402kck@enews3.newsguy.com> References: <3BD93B77.2037E2E3@sussex.ac.uk> NNTP-Posting-Host: p-620.newsdawg.com X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2479.0006 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2479.0006 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!small.news.tele.dk!209.155.233.16!pln-e!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews3 Xref: chonsp.franklin.ch comp.arch.fpga:10998 "Ben Popoola" wrote in message news:3BD93B77.2037E2E3@sussex.ac.uk... > I suggested that you learn about the JTAG interface of IC's. A good > place to start is the texas instruments web site (www.ti.com) and look > for the downloadedable book ' The JTAG Primer' there. Can you provide a link to this document? A search for "the jtag primer" returns nothing. Thank you, -Martin