From: gautam_awasthi@yahoo.co.in (Gautam) Newsgroups: comp.arch.fpga Subject: PLLs & DLLs Date: 14 Oct 2001 21:20:21 -0700 Organization: http://groups.google.com/ Lines: 1 Message-ID: NNTP-Posting-Host: 164.129.1.38 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1003119622 5172 127.0.0.1 (15 Oct 2001 04:20:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Oct 2001 04:20:22 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!t-online.de!nntp-relay.ihug.net!ihug.co.nz!news-hog.berkeley.edu!ucberkeley!newsfeed.stanford.edu!sn-xit-01!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10677 From a FPGA User Perspective, How does Altera PLL differ from Xilinx DLL? ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: PLLs & DLLs Date: Mon, 15 Oct 2001 10:00:16 -0700 Organization: Xilinx Lines: 32 Message-ID: <3BCB161F.6E691E11@xilinx.com> References: Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 8bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10662 Falk wrote: > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. Let me correct some misconceptions here. PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, •correct the clock duty cycle to 50-50, •provide four clock phases ( 0, 90, 180, 270 degrees ) •provide two double-frequency outputs with opposite phase •keep all these independent outputs phase-aligned •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. Sorry for the long posting, but I find this really exciting. It's more than just a DLL. And, please, don't accuse me of marketing. This is meant to be engineering information ! Peter Alfke, Xilinx Applications ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: PLLs & DLLs Date: Mon, 15 Oct 2001 10:09:45 -0700 Organization: Xilinx Lines: 127 Message-ID: <3BCB1859.AA112A31@xilinx.com> References: <3BCB161F.6E691E11@xilinx.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------1B7FE0667DBB1029B584DBC2" X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!netnews.com!xfer02.netnews.com!newsfeed1.cidera.com!Cidera!portc01.blue.aol.com!news.gtei.net.MISMATCH!washdc3-snh1.gtei.net!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10661 --------------1B7FE0667DBB1029B584DBC2 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit I wish to emphasize Peter's point, "We have not come to bury PLL's, but to praise them." But when it comes down to the dirty real world, PLL's are fussy, and DLL's are not. That doesn't mean that PLL's are any less useful: they are required in many cases. http://www.icst.com/pdf/ics8735-01.pdf Is a good example of a PLL. Separate package, can control the singal integrity, power supplies, etc. Drop that 100 to 300 ps of jitter from that FPGA based PLL right down to practically nothing for those timing critical signals. http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf Oh, and even better for getting rid of the residual jitter from a DCM. The DCM jitter is all random at extremely high frequencies which get attenuated 100 fold by a good PLL. Austin Peter Alfke wrote: > Falk wrote: > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. > > Let me correct some misconceptions here. > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > > As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > > I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > > So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, > •correct the clock duty cycle to 50-50, > •provide four clock phases ( 0, 90, 180, 270 degrees ) > •provide two double-frequency outputs with opposite phase > •keep all these independent outputs phase-aligned > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) > •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > > Sorry for the long posting, but I find this really exciting. It's more than just a DLL. > And, please, don't accuse me of marketing. This is meant to be engineering information ! > > Peter Alfke, Xilinx Applications --------------1B7FE0667DBB1029B584DBC2 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit I wish to emphasize Peter's point,

"We have not come to bury PLL's, but to praise them."

But when it comes down to the dirty real world, PLL's are fussy, and DLL's are not.

That doesn't mean that PLL's are any less useful:  they are required in many cases.

 http://www.icst.com/pdf/ics8735-01.pdf

Is a good example of a PLL.  Separate package, can control the singal integrity, power supplies, etc.  Drop that 100 to 300 ps of jitter from that FPGA based PLL right down to practically nothing for those timing critical signals.

 http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf

Oh, and even better for getting rid of the residual jitter from a DCM.  The DCM jitter is all random at extremely high frequencies which get attenuated 100 fold by a good PLL.

Austin

Peter Alfke wrote:

Falk wrote:

> The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip>

Let me correct some misconceptions here.

PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated.

As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections.

I just finished writing an article for our techXclusives and we just  updated  the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ).

So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ):

•eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay,
•correct the clock duty cycle to 50-50,
•provide four clock phases ( 0, 90, 180, 270 degrees )
•provide two double-frequency outputs with opposite phase
•keep all these independent outputs phase-aligned
•on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14,  15, or 16.
•on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output )
•and - best of all- create a programmable phase shift,  described as a multiple of the clock period divided by 256,  that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation.  Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance.

Sorry for the long posting, but I find this really exciting. It's more than just a DLL.
And, please, don't accuse me of marketing. This is meant to be engineering information !

Peter Alfke, Xilinx Applications

--------------1B7FE0667DBB1029B584DBC2-- ###### From: Graham Newsgroups: comp.arch.fpga Subject: Re: PLLs & DLLs Date: Tue, 16 Oct 2001 07:40:54 GMT Message-ID: <3bcbe0a2.60847393@news.geccs.gecm.com> References: <3BCB161F.6E691E11@xilinx.com> X-Newsreader: Forte Free Agent 1.21/32.243 NNTP-Posting-Host: ect4075.ct.edinbr.gecm.com X-Trace: 16 Oct 2001 08:29:45 GMT, ect4075.ct.edinbr.gecm.com Lines: 45 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!diablo.theplanet.net!dispose.news.demon.net!demon!btnet-peer0!btnet-feed5!btnet!newreader.ukcore.bt.net!pull.gecm.com!ect4075.ct.edinbr.gecm.com Xref: chonsp.franklin.ch comp.arch.fpga:10714 Peter If the input clock to the Digital Clock Manager is removed for a time greater than 100 ms (say 60 sec) , will the DCM output a locked clock when the input clock is re-applied ?. The Virtex and Virtex-E cannot handle an input clock which has been stopped for 100ms or more, without the DLL needing to be reset On Mon, 15 Oct 2001 10:00:16 -0700, Peter Alfke wrote: > > >Falk wrote: > >> The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. > >Let me correct some misconceptions here. > >PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > >As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > >I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > >So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > >•eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, >•correct the clock duty cycle to 50-50, >•provide four clock phases ( 0, 90, 180, 270 degrees ) >•provide two double-frequency outputs with opposite phase >•keep all these independent outputs phase-aligned >•on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. >•on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) >•and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > >Sorry for the long posting, but I find this really exciting. It's more than just a DLL. >And, please, don't accuse me of marketing. This is meant to be engineering information ! > >Peter Alfke, Xilinx Applications > > > Graeme ###### From: gautam_awasthi@yahoo.co.in (Gautam) Newsgroups: comp.arch.fpga Subject: Re: PLLs & DLLs Date: 16 Oct 2001 06:07:28 -0700 Organization: http://groups.google.com/ Lines: 41 Message-ID: References: <3BCB161F.6E691E11@xilinx.com> NNTP-Posting-Host: 164.129.1.38 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1003237648 4514 127.0.0.1 (16 Oct 2001 13:07:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 16 Oct 2001 13:07:28 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-xit-02!supernews.com!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10726 Dear Peter Your Explanations on DLL & PLL clarified most of my doubts barring a few: 1. Are the Features(mentioned by You) Unique to DLL(or Xilinx)? 'coz Recently I read somewhere that ALTERA also provides Fine Phase Shifting capabilities in its APEX II Family......PLEASE COMMENT.... 2. What is the Usage of the 50% Duty-Cycle Correction Capability offered by Virtex II DCM? Regards Gautam Peter Alfke wrote in message news:<3BCB161F.6E691E11@xilinx.com>... > Falk wrote: > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. > > Let me correct some misconceptions here. > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > > As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > > I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > > So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, > •correct the clock duty cycle to 50-50, > •provide four clock phases ( 0, 90, 180, 270 degrees ) > •provide two double-frequency outputs with opposite phase > •keep all these independent outputs phase-aligned > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) > •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > > Sorry for the long posting, but I find this really exciting. It's more than just a DLL. > And, please, don't accuse me of marketing. This is meant to be engineering information ! > > Peter Alfke, Xilinx Applications ###### From: "Peter Ormsby" Newsgroups: comp.arch.fpga References: <3BCB161F.6E691E11@xilinx.com> Subject: Re: PLLs & DLLs Lines: 97 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Message-ID: Date: Wed, 17 Oct 2001 01:35:10 GMT NNTP-Posting-Host: 66.41.8.108 X-Complaints-To: abuse@mediaone.net X-Trace: typhoon.mn.mediaone.net 1003282510 66.41.8.108 (Tue, 16 Oct 2001 20:35:10 CDT) NNTP-Posting-Date: Tue, 16 Oct 2001 20:35:10 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!dca6-feed1.news.digex.net!intermedia!cyclone2.usenetserver.com!usenetserver.com!news-east.rr.com!cyclone.rdc-detw.rr.com!news.mw.mediaone.net!cyclone3.rdc-detw.rr.com!news3.mw.mediaone.net!typhoon.mn.mediaone.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10732 I'm a different Peter, but I'll give this a shot anyway... Here's the feature list from the PLLs in Altera's PLLs: Output frequency as a function of input frequency is m/(n * k) where m and k are integer values between 1 and 160 and n is an integer between 1 and 16. Or in Mr. Alfke's words "(almost) any arbitrary conversion factor". There's also two special conversions (256/193 and 193/256) for E1-T1 and T1-E1 conversions. There is both corse (90, 180, 270 degree) and fine (0.5ns to 1.0ns resolution depending on input frequency) phase shift on the PLL outputs. Input frequency ranges are 1.5 to 420MHz. Ouput frequency ranges are 1.5 to 335 MHz and 12.5 to 335 MHz on the two outputs that each PLL feeds back into the internal logic and up to 420MHz on the outputs that feed an external pin. -Pete- Gautam wrote in message news:d10cf32c.0110160507.42e50998@posting.google.com... > Dear Peter > Your Explanations on DLL & PLL clarified most of my doubts barring a > few: > 1. Are the Features(mentioned by You) Unique to DLL(or Xilinx)? 'coz > Recently I read somewhere that ALTERA also provides Fine Phase > Shifting capabilities in its APEX II Family......PLEASE COMMENT.... > 2. What is the Usage of the 50% Duty-Cycle Correction Capability > offered by Virtex II DCM? > > Regards > > Gautam > > Peter Alfke wrote in message news:<3BCB161F.6E691E11@xilinx.com>... > > Falk wrote: > > > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. > > > > Let me correct some misconceptions here. > > > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > > > > As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > > > > I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > > > > So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > > > •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, > > •correct the clock duty cycle to 50-50, > > •provide four clock phases ( 0, 90, 180, 270 degrees ) > > •provide two double-frequency outputs with opposite phase > > •keep all these independent outputs phase-aligned > > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > > •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) > > •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > > > > Sorry for the long posting, but I find this really exciting. It's more than just a DLL. > > And, please, don't accuse me of marketing. This is meant to be engineering information ! > > > > Peter Alfke, Xilinx Applications ###### Message-ID: <3BCCE8B1.2D615002@earthlink.net> From: Peter Alfke Reply-To: palfke@earthlink.net X-Mailer: Mozilla 4.61 (Macintosh; I; PPC) X-Accept-Language: en,pdf MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: PLLs & DLLs References: <3BCB161F.6E691E11@xilinx.com> Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Lines: 106 Date: Wed, 17 Oct 2001 02:11:05 GMT NNTP-Posting-Host: 216.244.43.77 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 1003284665 216.244.43.77 (Tue, 16 Oct 2001 19:11:05 PDT) NNTP-Posting-Date: Tue, 16 Oct 2001 19:11:05 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Tue, 16 Oct 2001 19:07:25 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!news.stealth.net!gestalt.direcpc.com!newsfeed.direct.ca!look.ca!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10700 Peter, with a nice name like this, you should be more careful when quoting. It was Falk ( not "Mr. Alfke" ) who wrote " (almost) any arbitrary conversion actor", and he was referring to Altera PLLs, not to Xilinx DLLs. "A girl has to watch her reputation..." Greetings Peter Alfke =============================== Peter Ormsby wrote: > I'm a different Peter, but I'll give this a shot anyway... > > Here's the feature list from the PLLs in Altera's PLLs: > > Output frequency as a function of input frequency is m/(n * k) where m and k > are integer values between 1 and 160 and n is an integer between 1 and 16. > Or in Mr. Alfke's words "(almost) any arbitrary conversion factor". There's > also two special conversions (256/193 and 193/256) for E1-T1 and T1-E1 > conversions. > > There is both corse (90, 180, 270 degree) and fine (0.5ns to 1.0ns > resolution depending on input frequency) phase shift on the PLL outputs. > > Input frequency ranges are 1.5 to 420MHz. > > Ouput frequency ranges are 1.5 to 335 MHz and 12.5 to 335 MHz on the two > outputs that each PLL feeds back into the internal logic and up to 420MHz on > the outputs that feed an external pin. > > -Pete- > > Gautam wrote in message > news:d10cf32c.0110160507.42e50998@posting.google.com... > > Dear Peter > > Your Explanations on DLL & PLL clarified most of my doubts barring a > > few: > > 1. Are the Features(mentioned by You) Unique to DLL(or Xilinx)? 'coz > > Recently I read somewhere that ALTERA also provides Fine Phase > > Shifting capabilities in its APEX II Family......PLEASE COMMENT.... > > 2. What is the Usage of the 50% Duty-Cycle Correction Capability > > offered by Virtex II DCM? > > > > Regards > > > > Gautam > > > > Peter Alfke wrote in message > news:<3BCB161F.6E691E11@xilinx.com>... > > > Falk wrote: > > > > > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO > to generate the output signal. A PLL can do clock rate conversion with > (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop > in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the > input frequency. > > > > > > Let me correct some misconceptions here. > > > > > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = > completely eliminate ) the clock distribution delay. Without PLL/DLLs, the > larger chips would have unpredictable input set-up/hold times, and > abominably long clock-to-output delays. But that is all fixed now; big chips > can be as fast as small ones, since the clock distribution delay can be > eliminated. > > > > > > As to the difference between PLL and DLL, it is undisputed that a > well-designed PLL in a low-noise environment ( the caveats show my Xilinx > background here ) can reduce input jitter, while a DLL inherently passes the > jitter on. It is also undisputed that a DLL is inherently more robust, less > sensitive to ground and Vcc noise, and does not require its private supply > connections. > > > > > > I just finished writing an article for our techXclusives and we just > updated the Virtex-II Handbook ( data sheet and user guide. See it on the > web next week ). > > > > > > So, here is what the Virtex-II Digital Clock Manager can do ( and there > are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > > > > > •eliminate the clock distribution delay and, with clock mirroring, > perhaps even the board delay, > > > •correct the clock duty cycle to 50-50, > > > •provide four clock phases ( 0, 90, 180, 270 degrees ) > > > •provide two double-frequency outputs with opposite phase > > > •keep all these independent outputs phase-aligned > > > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, > 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > > > •on another output multiply and divide the input frequency > simultaneously by any integer multiplier and divisor from 2 to 32. ( for > example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz > output ) > > > •and - best of all- create a programmable phase shift, described > as a multiple of the clock period divided by 256, that affects all outputs > simultaneously. And this phase shift can even be incremented and decremented > during operation. Interesting possibilities to adjust input or output > clocks either by configuration, or adaptively, to optimize I/O performance. > > > > > > Sorry for the long posting, but I find this really exciting. It's more > than just a DLL. > > > And, please, don't accuse me of marketing. This is meant to be > engineering information ! > > > > > > Peter Alfke, Xilinx Applications ###### From: "Peter Ormsby" Newsgroups: comp.arch.fpga References: <3BCB161F.6E691E11@xilinx.com> <3BCCE8B1.2D615002@earthlink.net> Subject: Re: PLLs & DLLs Lines: 142 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Message-ID: Date: Wed, 17 Oct 2001 02:19:03 GMT NNTP-Posting-Host: 66.41.8.108 X-Complaints-To: abuse@mediaone.net X-Trace: typhoon.mn.mediaone.net 1003285143 66.41.8.108 (Tue, 16 Oct 2001 21:19:03 CDT) NNTP-Posting-Date: Tue, 16 Oct 2001 21:19:03 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.mailgate.org!out.nntp.be!propagator-SanJose!in.nntp.be!newsfeed.frii.net!64.152.100.70.MISMATCH!sjcppf01.usenetserver.com!usenetserver.com!news-west.rr.com!cyclone.rdc-detw.rr.com!news.mw.mediaone.net!cyclone3.rdc-detw.rr.com!news3.mw.mediaone.net!typhoon.mn.mediaone.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:10731 I stand corrected. Sorry Peter. BTW, I did realize that Mr. Falk was speaking of Altera PLLs. In my discussion, I was trying to acknowledge that Mr. Falk's description was accurate despite my slightly more rigorous explanation. -Pete- Peter Alfke wrote in message news:3BCCE8B1.2D615002@earthlink.net... > Peter, > with a nice name like this, you should be more careful when quoting. > It was Falk ( not "Mr. Alfke" ) who wrote " (almost) any arbitrary conversion > actor", and he was referring to Altera PLLs, not to Xilinx DLLs. > > "A girl has to watch her reputation..." > > Greetings > Peter Alfke > =============================== > Peter Ormsby wrote: > > > I'm a different Peter, but I'll give this a shot anyway... > > > > Here's the feature list from the PLLs in Altera's PLLs: > > > > Output frequency as a function of input frequency is m/(n * k) where m and k > > are integer values between 1 and 160 and n is an integer between 1 and 16. > > Or in Mr. Alfke's words "(almost) any arbitrary conversion factor". There's > > also two special conversions (256/193 and 193/256) for E1-T1 and T1-E1 > > conversions. > > > > There is both corse (90, 180, 270 degree) and fine (0.5ns to 1.0ns > > resolution depending on input frequency) phase shift on the PLL outputs. > > > > Input frequency ranges are 1.5 to 420MHz. > > > > Ouput frequency ranges are 1.5 to 335 MHz and 12.5 to 335 MHz on the two > > outputs that each PLL feeds back into the internal logic and up to 420MHz on > > the outputs that feed an external pin. > > > > -Pete- > > > > Gautam wrote in message > > news:d10cf32c.0110160507.42e50998@posting.google.com... > > > Dear Peter > > > Your Explanations on DLL & PLL clarified most of my doubts barring a > > > few: > > > 1. Are the Features(mentioned by You) Unique to DLL(or Xilinx)? 'coz > > > Recently I read somewhere that ALTERA also provides Fine Phase > > > Shifting capabilities in its APEX II Family......PLEASE COMMENT.... > > > 2. What is the Usage of the 50% Duty-Cycle Correction Capability > > > offered by Virtex II DCM? > > > > > > Regards > > > > > > Gautam > > > > > > Peter Alfke wrote in message > > news:<3BCB161F.6E691E11@xilinx.com>... > > > > Falk wrote: > > > > > > > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO > > to generate the output signal. A PLL can do clock rate conversion with > > (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop > > in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the > > input frequency. > > > > > > > > Let me correct some misconceptions here. > > > > > > > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = > > completely eliminate ) the clock distribution delay. Without PLL/DLLs, the > > larger chips would have unpredictable input set-up/hold times, and > > abominably long clock-to-output delays. But that is all fixed now; big chips > > can be as fast as small ones, since the clock distribution delay can be > > eliminated. > > > > > > > > As to the difference between PLL and DLL, it is undisputed that a > > well-designed PLL in a low-noise environment ( the caveats show my Xilinx > > background here ) can reduce input jitter, while a DLL inherently passes the > > jitter on. It is also undisputed that a DLL is inherently more robust, less > > sensitive to ground and Vcc noise, and does not require its private supply > > connections. > > > > > > > > I just finished writing an article for our techXclusives and we just > > updated the Virtex-II Handbook ( data sheet and user guide. See it on the > > web next week ). > > > > > > > > So, here is what the Virtex-II Digital Clock Manager can do ( and there > > are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > > > > > > > •eliminate the clock distribution delay and, with clock mirroring, > > perhaps even the board delay, > > > > •correct the clock duty cycle to 50-50, > > > > •provide four clock phases ( 0, 90, 180, 270 degrees ) > > > > •provide two double-frequency outputs with opposite phase > > > > •keep all these independent outputs phase-aligned > > > > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, > > 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > > > > •on another output multiply and divide the input frequency > > simultaneously by any integer multiplier and divisor from 2 to 32. ( for > > example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz > > output ) > > > > •and - best of all- create a programmable phase shift, described > > as a multiple of the clock period divided by 256, that affects all outputs > > simultaneously. And this phase shift can even be incremented and decremented > > during operation. Interesting possibilities to adjust input or output > > clocks either by configuration, or adaptively, to optimize I/O performance. > > > > > > > > Sorry for the long posting, but I find this really exciting. It's more > > than just a DLL. > > > > And, please, don't accuse me of marketing. This is meant to be > > engineering information ! > > > > > > > > Peter Alfke, Xilinx Applications >