From: "Abraham Henry Vlok" <wagter@tuks.co.za>
Newsgroups: comp.arch.fpga
Subject: Clockin on rising AND falling edge
Date: Thu, 20 Sep 2001 10:46:38 +0200
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Hi all,

Can anybody tell me how I can clock 'a process on the rising AND falling
edge of  a clock signal ?

I want to do something like :
<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
but it doesn't work.

Please help
Abraham

######

From: Andy Green <not-given@invalid.com>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
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Can't be done on Xilinx, anyhow; the hardware in the FPGA can only 
operate on one edge or the other.

Instead you should double your clock speed.

|Hi all,
|
|Can anybody tell me how I can clock 'a process on the rising AND 
falling
|edge of  a clock signal ?
|
|I want to do something like :
|<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
|but it doesn't work.
|
|Please help
|Abraham
--
Posted using Nographer - News in your Browser
http://www.nographer.com - free, open source, and smart

######

From: "Panu H" <panuh[@]cs.tut.fi>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
Date: Thu, 20 Sep 2001 14:03:50 +0300
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> |I want to do something like :
> |<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> |but it doesn't work.

It is not possible that clk is 1 and 0 at the same time.

Maybe like this:
if (clk'event and clk = '1') or (clk'event and clk = '0') then ...
or:
if clk'event then ...

-- Panu

######

From: "Abraham Henry Vlok" <wagter@tuks.co.za>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
Date: Thu, 20 Sep 2001 15:02:31 +0200
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Tried that aswell. It doesn't work.
thankx anyway.
Panu H <panuh[@]cs.tut.fi> wrote in message
news:9ociem$s7d$1@news.cc.tut.fi...
> > |I want to do something like :
> > |<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> > |but it doesn't work.
>
> It is not possible that clk is 1 and 0 at the same time.
>
> Maybe like this:
> if (clk'event and clk = '1') or (clk'event and clk = '0') then ...
> or:
> if clk'event then ...
>
> -- Panu
>
>
>

######

From: "Andrew Brown" <andrewbr@nortelnetworks.com>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
Date: Thu, 20 Sep 2001 16:24:12 +0100
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Abraham Henry Vlok <wagter@tuks.co.za> wrote in message
news:1000990968.542535@nntp.up.ac.za...
> Tried that aswell. It doesn't work.

Doesn't work in simulation or synthesis?

######

From: Peter Alfke <peter.alfke@xilinx.com>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
Date: Thu, 20 Sep 2001 10:25:20 -0700
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You first have to generate a double-frequency clock.
It's easy and uses only one ff, one inverter,and one XOR:
Feed the input frequency into the XOR, feed the other input of the XOR together
with the D input of the flip-flop from the inverted Q output of that flip-flop.
Then use the XOR output to clock the flip-flop, and also use the XOR as the
double-frequency output.
Now you have a double-frequency clock and can do anything you want.

Virtex circuits give you the clock doubling for free in their Digital Clock
Manager circuit.

Peter Alfke, Xilinx Applications.
===========================
Abraham Henry Vlok wrote:

> Hi all,
>
> Can anybody tell me how I can clock 'a process on the rising AND falling
> edge of  a clock signal ?
>
> I want to do something like :
> <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
> but it doesn't work.
>
> Please help
> Abraham

######

From: Philip Freidin <philip@fliptronics.com>
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
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On Thu, 20 Sep 2001 10:46:38 +0200, "Abraham Henry Vlok" <wagter@tuks.co.za>
wrote:
>Hi all,
>
>Can anybody tell me how I can clock 'a process on the rising AND falling
>edge of  a clock signal ?

I bet you mean  OR

>I want to do something like :
><<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
>but it doesn't work.

Probably just this:

    if (clock_in'event) then


but although this might be acceptable to simulation, this won't be
synthesizable.

>Please help
>Abraham
>

Philip


Philip Freidin
Fliptronics

######

From: hamish@cloud.net.au
Subject: Re: Clockin on rising AND falling edge
Newsgroups: comp.arch.fpga
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lennart <lennartheijnen@hotmail.com> wrote:
> You can never use a rising and a falling edge of a signal in a process. 

You can, you just can't synthesise it.

It's quite useful in simulation (only) to register some DDR signals using

reg_ddr: process (ddr_clk)
begin
  if ddr_clk'event then
    ddr_q <= ddr_d;
  end if;
end process;

I contacted Synplicity support a while ago and asked if Synplify could
infer the DDR outputs available in the Virtex-II; they told me it
was illegal in VHDL :-( I'm not sure what that means.



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

######

Sender: przemek@przemek
Newsgroups: comp.arch.fpga
Subject: Re: Clockin on rising AND falling edge
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Peter Alfke <peter.alfke@xilinx.com> writes:

> You first have to generate a double-frequency clock.
> It's easy and uses only one ff, one inverter,and one XOR:
> Feed the input frequency into the XOR, feed the other input of the XOR together
> with the D input of the flip-flop from the inverted Q output of that flip-flop.
> Then use the XOR output to clock the flip-flop, and also use the XOR as the
> double-frequency output.

This circuit seems to make short ones of a single FF delay length.
How is it better than a simple XOR gate fed with the input clock and a
negated input clock (or an odd number of inverters, in a row)? 

-- 
przemek Klosowski (przemek@nist.gov) tel 301/975-6249

######

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I think it is safer, since it includes the toggling of a flip-flop. So the pulse
will never be so short that it does not toggle a flip-flop.
And also, it is no more expensive than the basic circuit you describe. Flip-flops
are cheap  :-)

Peter Alfke, Xilinx Applications
==================================
przemek wrote:

> Peter Alfke <peter.alfke@xilinx.com> writes:
>
> > You first have to generate a double-frequency clock.
> > It's easy and uses only one ff, one inverter,and one XOR:
> > Feed the input frequency into the XOR, feed the other input of the XOR together
> > with the D input of the flip-flop from the inverted Q output of that flip-flop.
> > Then use the XOR output to clock the flip-flop, and also use the XOR as the
> > double-frequency output.
>
> This circuit seems to make short ones of a single FF delay length.
> How is it better than a simple XOR gate fed with the input clock and a
> negated input clock (or an odd number of inverters, in a row)?
>
> --
> przemek Klosowski (przemek@nist.gov) tel 301/975-6249

######

Message-ID: <3BAEF482.3C95@designtools.co.nz>
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Peter Alfke wrote:
> 
> I think it is safer, since it includes the toggling of a flip-flop. So the pulse
> will never be so short that it does not toggle a flip-flop.
> And also, it is no more expensive than the basic circuit you describe. Flip-flops
> are cheap  :-)
> 
> Peter Alfke, Xilinx Applications
> ==================================
> przemek wrote:
> 
> > Peter Alfke <peter.alfke@xilinx.com> writes:
> >
> > > You first have to generate a double-frequency clock.
> > > It's easy and uses only one ff, one inverter,and one XOR:
> > > Feed the input frequency into the XOR, feed the other input of the XOR together
> > > with the D input of the flip-flop from the inverted Q output of that flip-flop.
> > > Then use the XOR output to clock the flip-flop, and also use the XOR as the
> > > double-frequency output.
> >
> > This circuit seems to make short ones of a single FF delay length.
> > How is it better than a simple XOR gate fed with the input clock and a
> > negated input clock (or an odd number of inverters, in a row)?

 Also, some tools will optimise out the redundant inverters, unless 
watched carefully :-)
 
 You can, of course, add a 'delay line' in the Q->XOR path, and so
widen the pulse, if desired. 

-jg