Message-ID: <3B92E32A.5C5ABF92@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Virtex Architecture: Interconnect References: Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Lines: 58 Date: Mon, 03 Sep 2001 01:53:11 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 999481991 24.13.238.93 (Sun, 02 Sep 2001 18:53:11 PDT) NNTP-Posting-Date: Sun, 02 Sep 2001 18:53:11 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9689 There isn't a nice picture like there is for the 4K, but you can still glean most of the info from the databooks. The best place to go though, if you have the tools, is into the FPGA editor. It was that that finally made the interconnect all clear. Here is a summary of the routing: Local CLB routing intra-CLB routing (first level switchbox) 2 direct paths to horizontally adjacent CLBs General purpose routing: Each CLB is associated with General Routing Matrix (a switchbox) which connects to: 24 single length wires to adjacent GRMs in each of 4 directions 96 buffered hex wires to GRMs 6 blocks away in 4 directions staggered pattern driven only at end points accessible at endpoints and midpoint 1/3 are bidirectional, 1/3 unidirectionalleft/up and 1/3 unidirectional right/down vertical bidirectional hexes can connect to CLK, CE, SR and the tristate enables at every CLB 12 Long lines buffered bidirectional wires, 2 connected at each GRM connections to GRMs at multiples of 6 rows/columns, staggered. vertical and horizontal lines span device Global Routing 4 dedicated primary global nets driven by dedicated global buffers 24 Horizontal backbones with connections to vertical long lines I/O routing ‘Versa-Ring’ routing around chip periphery Extra routing resource to make pin placement less critical Dedicated Routing 4 Horizontal pseudo tri-state busses per CLB row Partitionable for multiple busses in a row Mux architecture mimics tri-state Buffered so it is faster than tri-state Dedicated vertical fast carry connections Dereck wrote: > Hi > Guys do you have information about The Interconnect Routing in The Virtex Parts. > I am interested in knowing how many, > Long, single , double etc lines are present in a single tile in a Virtex part like XCV800. > > 2. I have seen how the routing looks in XC4000 Programmable Interconnect (Figure 27 Page 6-30).XC 4000 datasheet. > Such a picture is not available for XCV 800. > If you guys can help, Please write to me I will explain in more details. > > Dereck > dereckaf@yahoo.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com