Lines: 34 X-Admin: news@aol.com From: diverseg@aol.com (DIVERSEG) Newsgroups: comp.arch.fpga Date: 31 Aug 2001 05:49:00 GMT Organization: AOL http://www.aol.com Subject: ISA(PC/104) BUS DECODE ASYNC or SYNC? Message-ID: <20010831014900.26248.00004289@mb-fy.aol.com> Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!portc03.blue.aol.com!audrey05.news.aol.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9617 I have always tried to stick to sync designs. However lately I have ran into a problem. While designing some isa cards I read somewhere that I did not need to use BALE to latch my address lines. Is this acceptable? Also I am decoding using a state machine in a FPGA with Sysclk as the clock for transitions in my state machine. Last week I changed CPU and the new CPU card does not drive Sysclk. Now my boards do not work. I called the board designer and de says that sysclk now a days is not sync with the I/O signals anyway? Who do i believe? Is async acceptable? Are the address lines stable so BALE is not nescessary? Any comments suggestions? Xilinx foundation users is it possible to take the VHDL created by the state diagram editor and make the state machine async and dependant on the input signal transitions to go from one state to another? Steven Collins Macha International, Inc. 713-723-5040x13 scollins@macha.com ###### From: "Tim" Newsgroups: comp.arch.fpga,comp.arch.embedded Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? Date: Fri, 31 Aug 2001 11:21:11 +0100 Message-ID: <999268551.4832.0.nnrp-14.9e9832fa@news.demon.co.uk> References: <20010831014900.26248.00004289@mb-fy.aol.com> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 999268551 nnrp-14:4832 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Lines: 43 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!grolier!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9643 comp.arch.embedded is probably the best place for this question. AFAIK. "DIVERSEG" wrote in message news:20010831014900.26248.00004289@mb-fy.aol.com... > > I have always tried to stick to sync designs. > However lately I have ran into a problem. > While designing some isa cards I read somewhere that I did not need to use BALE > to latch my address lines. > > Is this acceptable? > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > transitions in my state machine. > > Last week I changed CPU and the new CPU card does not drive Sysclk. > Now my boards do not work. I called the board designer and de says that sysclk > now a days is not sync with the I/O signals anyway? > > Who do i believe? > > Is async acceptable? > > Are the address lines stable so BALE is not nescessary? > > Any comments suggestions? > > > Xilinx foundation users is it possible to take the VHDL created by the state > diagram editor and make the state machine async and dependant on the input > signal transitions to go from one state to another? > > > Steven Collins > Macha International, Inc. > 713-723-5040x13 > scollins@macha.com > ###### Message-ID: <3B8F9DA9.D877E386@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? References: <20010831014900.26248.00004289@mb-fy.aol.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 48 Date: Fri, 31 Aug 2001 14:19:55 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 999267595 24.13.238.93 (Fri, 31 Aug 2001 07:19:55 PDT) NNTP-Posting-Date: Fri, 31 Aug 2001 07:19:55 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!102801!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9602 You can't really depend on the ISA bus signals being synchronous with sysclk. You don't need BALE. You should use IOW to clock in the data and address, then transfer that latched address and data to your local clock domain using sound async transfer techniques. For reads, sync up IOR to advance your local counter on the end of a read access. IOW should go into the FPGA via a global clock pin if possible. DIVERSEG wrote: > I have always tried to stick to sync designs. > However lately I have ran into a problem. > While designing some isa cards I read somewhere that I did not need to use BALE > to latch my address lines. > > Is this acceptable? > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > transitions in my state machine. > > Last week I changed CPU and the new CPU card does not drive Sysclk. > Now my boards do not work. I called the board designer and de says that sysclk > now a days is not sync with the I/O signals anyway? > > Who do i believe? > > Is async acceptable? > > Are the address lines stable so BALE is not nescessary? > > Any comments suggestions? > > Xilinx foundation users is it possible to take the VHDL created by the state > diagram editor and make the state machine async and dependant on the input > signal transitions to go from one state to another? > > Steven Collins > Macha International, Inc. > 713-723-5040x13 > scollins@macha.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com ###### From: "Andy Peters com"> X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? References: <20010831014900.26248.00004289@mb-fy.aol.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 Message-ID: Date: Fri, 31 Aug 2001 17:06:33 GMT NNTP-Posting-Host: 24.221.131.16 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 999277593 24.221.131.16 (Fri, 31 Aug 2001 10:06:33 PDT) NNTP-Posting-Date: Fri, 31 Aug 2001 10:06:33 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Fri, 31 Aug 2001 10:03:46 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!191454!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9612 Perhaps you should use a local clock of some reasonable speed to synchronize the ISA signals and run your state machine? --a DIVERSEG wrote: > > I have always tried to stick to sync designs. > However lately I have ran into a problem. > While designing some isa cards I read somewhere that I did not need to use BALE > to latch my address lines. > > Is this acceptable? > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > transitions in my state machine. > > Last week I changed CPU and the new CPU card does not drive Sysclk. > Now my boards do not work. I called the board designer and de says that sysclk > now a days is not sync with the I/O signals anyway? > > Who do i believe? > > Is async acceptable? > > Are the address lines stable so BALE is not nescessary? > > Any comments suggestions? > > Xilinx foundation users is it possible to take the VHDL created by the state > diagram editor and make the state machine async and dependant on the input > signal transitions to go from one state to another? > > Steven Collins > Macha International, Inc. > 713-723-5040x13 > scollins@macha.com ###### Message-ID: <3B8FE3D3.EB31EFBE@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? References: <20010831014900.26248.00004289@mb-fy.aol.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 57 Date: Fri, 31 Aug 2001 19:19:17 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 999285557 24.13.238.93 (Fri, 31 Aug 2001 12:19:17 PDT) NNTP-Posting-Date: Fri, 31 Aug 2001 12:19:17 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-lei1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9657 I had assumed he had some local clock. If none, he can use the sysclk (if it is there at all), however, he cannot depend on the IOW or other signals being synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there is a question as to whether that clock even exists, or if you need a higher clock rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago now), one could still depend on having a sysclock, even though it was not often used. With the latest boards with barely feigned ISA support, this may no longer be true. "Andy Peters > Perhaps you should use a local clock of some reasonable speed to > synchronize the ISA signals and run your state machine? > > --a > > DIVERSEG wrote: > > > > I have always tried to stick to sync designs. > > However lately I have ran into a problem. > > While designing some isa cards I read somewhere that I did not need to use BALE > > to latch my address lines. > > > > Is this acceptable? > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > transitions in my state machine. > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > Now my boards do not work. I called the board designer and de says that sysclk > > now a days is not sync with the I/O signals anyway? > > > > Who do i believe? > > > > Is async acceptable? > > > > Are the address lines stable so BALE is not nescessary? > > > > Any comments suggestions? > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > diagram editor and make the state machine async and dependant on the input > > signal transitions to go from one state to another? > > > > Steven Collins > > Macha International, Inc. > > 713-723-5040x13 > > scollins@macha.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com ###### Lines: 14 X-Admin: news@aol.com From: diverseg@aol.com (DIVERSEG) Newsgroups: comp.arch.fpga Date: 01 Sep 2001 05:36:44 GMT References: <3B8FE3D3.EB31EFBE@andraka.com> Organization: AOL http://www.aol.com Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? Message-ID: <20010901013644.18769.00005913@mb-mo.aol.com> Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!59701!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!howland.erols.net!portc.blue.aol.com.MISMATCH!portc01.blue.aol.com!audrey05.news.aol.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9660 Funny, Today before I read the response I used a local clock of sufficient speed to run my state machine. I thru out the BALE(I have read this is not usefull anymore, I am not sure why!). I used ADDRESS and AEN='0' and (iow='0' or ior='0') Beauitful !! Worked like a champ. I even tried other cpu boards works on all i tried so far! ###### Message-ID: <3B951B9B.3E104F8F@exponentmedia.deletethis.com> From: Andy Peters X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? References: <20010831014900.26248.00004289@mb-fy.aol.com> <3B8FE3D3.EB31EFBE@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 65 Date: Tue, 04 Sep 2001 18:21:48 GMT NNTP-Posting-Host: 24.221.131.16 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 999627708 24.221.131.16 (Tue, 04 Sep 2001 11:21:48 PDT) NNTP-Posting-Date: Tue, 04 Sep 2001 11:21:48 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Tue, 04 Sep 2001 11:18:12 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!small.news.tele.dk!4.1.16.34!cpk-news-hub1.bbnplanet.com!lsanca1-snf1!news.gtei.net!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9725 Ray, If I was designing the ISA board (been there, done that...), I'd put a local clock on it. There are probably other things on the board that you'd like to be synchronous to it... ---a Ray Andraka wrote: > > I had assumed he had some local clock. If none, he can use the sysclk (if it is > there at all), however, he cannot depend on the IOW or other signals being > synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there > is a question as to whether that clock even exists, or if you need a higher clock > rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago > now), one could still depend on having a sysclock, even though it was not often > used. With the latest boards with barely feigned ISA support, this may no longer be > true. > > "Andy Peters > > > Perhaps you should use a local clock of some reasonable speed to > > synchronize the ISA signals and run your state machine? > > > > --a > > > > DIVERSEG wrote: > > > > > > I have always tried to stick to sync designs. > > > However lately I have ran into a problem. > > > While designing some isa cards I read somewhere that I did not need to use BALE > > > to latch my address lines. > > > > > > Is this acceptable? > > > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > > transitions in my state machine. > > > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > > Now my boards do not work. I called the board designer and de says that sysclk > > > now a days is not sync with the I/O signals anyway? > > > > > > Who do i believe? > > > > > > Is async acceptable? > > > > > > Are the address lines stable so BALE is not nescessary? > > > > > > Any comments suggestions? > > > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > > diagram editor and make the state machine async and dependant on the input > > > signal transitions to go from one state to another? > > > > > > Steven Collins > > > Macha International, Inc. > > > 713-723-5040x13 > > > scollins@macha.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com ###### Message-ID: <3B956B54.8FA5C5B@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC? References: <20010831014900.26248.00004289@mb-fy.aol.com> <3B8FE3D3.EB31EFBE@andraka.com> <3B951B9B.3E104F8F@exponentmedia.deletethis.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 78 Date: Tue, 04 Sep 2001 23:58:35 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 999647915 24.13.238.93 (Tue, 04 Sep 2001 16:58:35 PDT) NNTP-Posting-Date: Tue, 04 Sep 2001 16:58:35 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!feed2.onemain.com!feed1.onemain.com!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9730 Me too, and you can bet that it would be quite a bit faster than 14.3 MHz :-) Andy Peters wrote: > Ray, > > If I was designing the ISA board (been there, done that...), I'd put a > local clock on it. There are probably other things on the board that > you'd like to be synchronous to it... > > ---a > > Ray Andraka wrote: > > > > I had assumed he had some local clock. If none, he can use the sysclk (if it is > > there at all), however, he cannot depend on the IOW or other signals being > > synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there > > is a question as to whether that clock even exists, or if you need a higher clock > > rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago > > now), one could still depend on having a sysclock, even though it was not often > > used. With the latest boards with barely feigned ISA support, this may no longer be > > true. > > > > "Andy Peters > > > > > Perhaps you should use a local clock of some reasonable speed to > > > synchronize the ISA signals and run your state machine? > > > > > > --a > > > > > > DIVERSEG wrote: > > > > > > > > I have always tried to stick to sync designs. > > > > However lately I have ran into a problem. > > > > While designing some isa cards I read somewhere that I did not need to use BALE > > > > to latch my address lines. > > > > > > > > Is this acceptable? > > > > > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > > > transitions in my state machine. > > > > > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > > > Now my boards do not work. I called the board designer and de says that sysclk > > > > now a days is not sync with the I/O signals anyway? > > > > > > > > Who do i believe? > > > > > > > > Is async acceptable? > > > > > > > > Are the address lines stable so BALE is not nescessary? > > > > > > > > Any comments suggestions? > > > > > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > > > diagram editor and make the state machine async and dependant on the input > > > > signal transitions to go from one state to another? > > > > > > > > Steven Collins > > > > Macha International, Inc. > > > > 713-723-5040x13 > > > > scollins@macha.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com