From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: XCV800 : Jbits Date: Thu, 30 Aug 2001 23:38:16 +0100 Message-ID: <999216222.17167.0.nnrp-14.9e9832fa@news.demon.co.uk> References: NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 999216222 nnrp-14:17167 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Lines: 31 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news.tele.dk!small.news.tele.dk!212.74.64.35!colt.net!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9644 "Dereck" wrote in message news:ee722b3.-1@WebX.sUN8CHnE... > Hi, > I am Dereck Fernandes, I am a grad student in the University of > Massachuetts, Amherst. I working on a Interconnect Test tool for Xilinx > Virtex FPGAs. > > I have a question regarding JBits. > > 1. Does the routing in the Tile for XC4000 and XCV800 widely differ. I > saw a Jbits code for XC4000 which allows you to set the routing: > jbits.set(row,col,Y.HORIZ_SINGLE1,Y.ON) > Is this the same in XCV 800. Virtex is much simpler and much more powerful. > 2. I am basically trying to understand how the routing looks in XCV800, In > the databook for XC4000 you have a figure that gives detail of the > Programmable Interconnect (Figure 27 Page 6-30). > Do you have a similiar page for XCV 800 or is it the same. Write to jbits@xilinx.com > 3. I need to know how many single,double,long lines are present in each > tile. The basics are in the data sheet and visible in FPGA_editor. More info comes with JBits. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: XCV800 : Jbits Date: 01 Sep 2001 00:17:28 +0200 Organization: My own Private Self Lines: 52 Message-ID: <6uu1ynswlj.fsf@chonsp.franklin.ch> References: <999216222.17167.0.nnrp-14.9e9832fa@news.demon.co.uk> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 999296250 590 10.0.3.2 (31 Aug 2001 22:17:30 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 31 Aug 2001 22:17:30 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:9655 Original post did not arrive, so answering to followup. "Tim" writes: > "Dereck" wrote in message news:ee722b3.-1@WebX.sUN8CHnE... > > 1. Does the routing in the Tile for XC4000 and XCV800 widely differ. I Totally. 2 entirely different designs. Even the amount of LUT/FFs per tile are different (XC4000 2, XCV 4). > > saw a Jbits code for XC4000 which allows you to set the routing: > > jbits.set(row,col,Y.HORIZ_SINGLE1,Y.ON) > > Is this the same in XCV 800. Same syntax, but totally different constants. Also JBits has the JRoute router to automatically connect without looking at individual PIPs. > Virtex is much simpler and much more powerful. That also. The more I work with Virtex, the more I like this chip. > > 2. I am basically trying to understand how the routing looks in XCV800, In > > the databook for XC4000 you have a figure that gives detail of the > > Programmable Interconnect (Figure 27 Page 6-30). > > Do you have a similiar page for XCV 800 or is it the same. I once sketched out part (hex and long line smissing) of the Virtex/XCV routing based on the JBits documentation: http://neil.franklin.ch/Projects/PDP-10/Virtex-CLB-PIPs > > 3. I need to know how many single,double,long lines are present in each > > tile. > > The basics are in the data sheet and visible in FPGA_editor. More > info comes with JBits. Single: 24 Double: none Hex: I can't remember, possibly 18 long lines: 6 IIRC -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery