Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: hardware damage to a Virtex or Spartan-II? Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 16 Aug 2001 21:53:17 -0700 Message-ID: Lines: 24 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 16 Aug 2001 22:02:32 -0700, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:9311 On the MPGA page it is stated: Please be warned that YOU CAN BLOW UP YOUR EXPENSIVE HARDWARE if you aren't careful with the MPGA as it is now. It's all too easy to download a design with (unintended) combinatorial loops in it, there is no DRC, no warning. http://ce.et.tudelft.nl/~reinoud/mpga/README.html Can a combinatorial loop cause hardware damage to a Virtex or Spartan-II? I thought the only internal condition that was potentially damaging was an internal driver conflict. I thought logic like: --------------+----------- | | | | | |\ | -----| >O----- |/ would probably not work too well, but can it actually cause damage? Eric ###### Message-ID: <3B7CE735.5B3FF6D2@wanabe.nl> Date: Fri, 17 Aug 2001 11:43:17 +0200 From: Reinoud Organization: remains troubled X-Mailer: Mozilla 4.7 [en] (X11; I; Linux 2.2.17 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 43 NNTP-Posting-Host: 8dyn83.delft.casema.net X-Trace: reader3 998041304 8120 195.96.123.83 X-Complaints-To: http://www.casema.net/abuse X-Abuse-Info: Please be sure to include a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly X-Server-Date: 17 Aug 2001 09:41:44 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!cleanfeed.casema.net!leda.casema.net!post.casema.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9279 Eric Smith wrote: > > On the MPGA page it is stated: > > Please be warned that YOU CAN BLOW UP YOUR EXPENSIVE HARDWARE if you > aren't careful with the MPGA as it is now. It's all too easy to > download a design with (unintended) combinatorial loops in it, there > is no DRC, no warning. > > http://ce.et.tudelft.nl/~reinoud/mpga/README.html > > Can a combinatorial loop cause hardware damage to a Virtex or Spartan-II? > I thought the only internal condition that was potentially damaging was > an internal driver conflict. I thought logic like: > > --------------+----------- > | | > | | > | |\ | > -----| >O----- > |/ > > would probably not work too well, but can it actually cause damage? > > Eric Eric, The same paragraph on that page explains: Resulting oscillations may cause widespread high frequency switching and this may draw more power than your hardware was designed to handle. A circuit like you have drawn above will oscillate at a fairly high frequency. If there are many loops, or if a lot of logic is driven at high frequency by such loops, this may draw a lot of power. Many boards out there with large FPGAs were not designed to handle such power. This is not a flaw of Virtex (actually, Xilinx documents power issues quite clearly), it's more a board/system design issue with current generation (high power density) chips. - Reinoud ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? References: <3B7CE735.5B3FF6D2@wanabe.nl> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 17 Aug 2001 18:36:26 -0700 Message-ID: Lines: 13 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 17 Aug 2001 18:45:52 -0700, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-koe1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:9312 Reinoud writes: > A circuit like you have drawn above will oscillate at a fairly high > frequency. If there are many loops, or if a lot of logic is driven > at high frequency by such loops, this may draw a lot of power. Many > boards out there with large FPGAs were not designed to handle such > power. This is not a flaw of Virtex (actually, Xilinx documents > power issues quite clearly), it's more a board/system design issue > with current generation (high power density) chips. I appreciate the insight. However, I'm still curious as to whether such things are likely to damage the chip. I suppose the answer may depend on how many such circuits one manages to configure. ###### Message-ID: <3B7EED41.9C0238A@wanabe.nl> Date: Sun, 19 Aug 2001 00:33:37 +0200 From: Reinoud Organization: remains troubled X-Mailer: Mozilla 4.7 [en] (X11; I; Linux 2.2.17 i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? References: <3B7CE735.5B3FF6D2@wanabe.nl> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 NNTP-Posting-Host: 8dyn114.delft.casema.net X-Trace: reader5 998173922 27108 195.96.123.114 X-Complaints-To: http://www.casema.net/abuse X-Abuse-Info: Please be sure to include a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly X-Server-Date: 18 Aug 2001 22:32:02 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!cleanfeed.casema.net!leda.casema.net!post.casema.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9364 Eric Smith wrote: > > Reinoud writes: > > A circuit like you have drawn above will oscillate at a fairly high > > frequency. If there are many loops, or if a lot of logic is driven > > at high frequency by such loops, this may draw a lot of power. Many > > boards out there with large FPGAs were not designed to handle such > > power. This is not a flaw of Virtex (actually, Xilinx documents > > power issues quite clearly), it's more a board/system design issue > > with current generation (high power density) chips. > > I appreciate the insight. However, I'm still curious as to whether > such things are likely to damage the chip. I suppose the answer > may depend on how many such circuits one manages to configure. It depends on how hot the chip can get when downloading such problematic designs. This depends on FPGA technology, die size, packaging and cooling - and the capacity of the power supply. The combination of a huge modern FPGA, strong power supply, and no heatsink has high potential for smoke emissions. With a tiny FPGA or weak power supply, no sweat. Otherwise, cooling or power/temperature monitoring can keep things within safe limits. You can get an idea of these power issues by playing with the power estimator on the Xilinx website, and calculating die temperatures with the package thermal data. - Reinoud (Spam goes to wanabe, mail to wanadoo.) ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Mon, 20 Aug 2001 07:42:43 -0700 Organization: Xilinx Lines: 48 Message-ID: <3B8121E2.1ACAFFDC@xilinx.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B7EED41.9C0238A@wanabe.nl> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!nycmny1-snh1.gtei.net!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9339 Right, It isn't a question of damaging the metal interconnect (not enough current), or of damaging the transistors (again, not enough current); it is a question of creating many millions of uA loads, that together cause the chip to overheat. I have often wondered what all the fuss is about: use a power controller to sense the temperature from the temp diode in Virtex (or Virtex E, or Virtex II), or use a series current sensor in the Vccint line. If in the process of programming, either the temperature starts to rise, or the current is over the limit, you try the next configuration. Austin Reinoud wrote: > Eric Smith wrote: > > > > Reinoud writes: > > > A circuit like you have drawn above will oscillate at a fairly high > > > frequency. If there are many loops, or if a lot of logic is driven > > > at high frequency by such loops, this may draw a lot of power. Many > > > boards out there with large FPGAs were not designed to handle such > > > power. This is not a flaw of Virtex (actually, Xilinx documents > > > power issues quite clearly), it's more a board/system design issue > > > with current generation (high power density) chips. > > > > I appreciate the insight. However, I'm still curious as to whether > > such things are likely to damage the chip. I suppose the answer > > may depend on how many such circuits one manages to configure. > > It depends on how hot the chip can get when downloading such > problematic designs. This depends on FPGA technology, die size, > packaging and cooling - and the capacity of the power supply. The > combination of a huge modern FPGA, strong power supply, and no > heatsink has high potential for smoke emissions. With a tiny FPGA or > weak power supply, no sweat. Otherwise, cooling or power/temperature > monitoring can keep things within safe limits. > > You can get an idea of these power issues by playing with the power > estimator on the Xilinx website, and calculating die temperatures > with the package thermal data. > > - Reinoud > > (Spam goes to wanabe, mail to wanadoo.) ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Mon, 20 Aug 2001 10:15:44 -0700 Organization: Xilinx Lines: 20 Message-ID: <3B8145C0.3D5547D3@xilinx.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en To: Eric Smith Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!nycmny1-snh1.gtei.net!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9335 Eric Smith wrote: > > I appreciate the insight. However, I'm still curious as to whether > such things are likely to damage the chip. I suppose the answer > may depend on how many such circuits one manages to configure. If you ( accidentally ) create a lot of internal oscillators or glitch generators, these circuits will consume Icc, and thus heat up the chip. But, by its nature, the local current is small, in the mA range. If total heat is a problem, the current will be widely distributed, and thus benign. You only have to worryabout chip temperature, not metal migration. Put your fingertip on the package: If you can keep it there, the package surface is below 65 degrees C, if it sizzles, it is above 100 degrees C. Ouch! Peter Alfke, Xilinx Applications ###### From: "Bryan" Newsgroups: comp.arch.fpga References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> Subject: Re: hardware damage to a Virtex or Spartan-II? Lines: 34 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Message-ID: Date: Mon, 20 Aug 2001 12:05:29 -0600 NNTP-Posting-Host: 38.227.95.10 X-Trace: client 998331427 38.227.95.10 (Mon, 20 Aug 2001 14:17:07 EDT) NNTP-Posting-Date: Mon, 20 Aug 2001 14:17:07 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newsfeed1.cidera.com!Cidera!portc03.blue.aol.com!peerfeed.news.psi.net!filter.news.psi.net!reader.dist.news.psi.net!client!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9358 Just for fun I created a full loaded virtex-II 1000 part which toggled all of the luts in the chip as fast as the routing would support. It draws about 10A of 1.5V for the core. Kind of fun test, just don't leave it plugged in very long. This was in the 256 pin package. Bryan "Peter Alfke" wrote in message news:3B8145C0.3D5547D3@xilinx.com... > > > Eric Smith wrote: > > > > > I appreciate the insight. However, I'm still curious as to whether > > such things are likely to damage the chip. I suppose the answer > > may depend on how many such circuits one manages to configure. > > If you ( accidentally ) create a lot of internal oscillators or glitch > generators, these circuits will consume Icc, and thus heat up the chip. > But, by its nature, the local current is small, in the mA range. If total heat > is a problem, the current will be widely distributed, and thus benign. > You only have to worryabout chip temperature, not metal migration. > Put your fingertip on the package: If you can keep it there, the package surface > is below 65 degrees C, if it sizzles, it is above 100 degrees C. Ouch! > > Peter Alfke, Xilinx Applications > > ###### Message-ID: <3B815292.36EA31DE@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 35 Date: Mon, 20 Aug 2001 19:10:26 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 998331030 62.254.210.251 (Mon, 20 Aug 2001 19:10:30 BST) NNTP-Posting-Date: Mon, 20 Aug 2001 19:10:30 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!37506!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!dispose.news.demon.net!demon!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9338 Peter Alfke wrote: > Eric Smith wrote: > > > > > I appreciate the insight. However, I'm still curious as to whether > > such things are likely to damage the chip. I suppose the answer > > may depend on how many such circuits one manages to configure. > > If you ( accidentally ) create a lot of internal oscillators or glitch > generators, these circuits will consume Icc, and thus heat up the chip. > But, by its nature, the local current is small, in the mA range. If total heat > is a problem, the current will be widely distributed, and thus benign. > You only have to worryabout chip temperature, not metal migration. > Put your fingertip on the package: If you can keep it there, the package surface > is below 65 degrees C, if it sizzles, it is above 100 degrees C. Ouch! > > Peter Alfke, Xilinx Applications Peter, On top of all the other useful stuff you contribute to CAF you have just answered a long-standing (or burning ?) question of mine regarding the calibration of heat sensing fingertips. To go further and get another data point: Last summer I was wondering why our new board wasn't doing anything from power-on. I, very briefly, put my finger on it & came away with a large & painful blister that was still very sore 2 days later. Cause = BGA chip pinout mirrored (not by me I hasten to add). What temp do you think the package would have reached ? ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: 20 Aug 2001 22:20:57 GMT Organization: California Institute of Technology, Pasadena Lines: 35 Message-ID: <9ls2g9$dc4@gap.cco.caltech.edu> References: <3B7CE735.5B3FF6D2@wanabe.nl> NNTP-Posting-Host: hork.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!113559!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!128.135.12.170.MISMATCH!news.uchicago.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:9382 In a discussion something like: >> Can a combinatorial loop cause hardware damage to a Virtex or Spartan-II? >> I thought the only internal condition that was potentially damaging was >> an internal driver conflict. I thought logic like: >> >> --------------+----------- >> | | >> | | >> | |\ | >> -----| >O----- >> |/ >> >> would probably not work too well, but can it actually cause damage? >The same paragraph on that page explains: > Resulting oscillations may cause widespread high frequency > switching and this may draw more power than your hardware was > designed to handle. It would seem that the oscillations wouldn't be much faster than the highest frequency that the device can run at. I was once working on a design in which a large fraction of the gates/ff would change state each clock cycle. Well, random would say 50% and it might have done that. I asked in this group, wondering if there would be any Icc/heat related problems. As far as I understood at the time (XC4000 series days), and assuming ordinary free-air cooling, it would be fine. If it was 100% of the gates changing at twice the clock rate, that would be four times the power, and it might get a little warmer. The path through CLBs and routing to make an oscillator like that shown should be long enough to keep the frequency relatively low, compared to discrete logic. -- glen ###### From: bryan@srccomp.com (Bryan) Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: 21 Aug 2001 09:19:27 -0700 Organization: http://groups.google.com/ Lines: 18 Message-ID: References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> NNTP-Posting-Host: 38.227.95.10 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 998410767 15528 127.0.0.1 (21 Aug 2001 16:19:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 21 Aug 2001 16:19:27 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9398 > > The path through CLBs and routing to make an oscillator like that > shown should be long enough to keep the frequency relatively low, > compared to discrete logic. > > -- glen The LUT oscillator that I created had 25% of the chip running at .45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at .45ns + .9ns or ~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by the book delays, which we have found actual routes to be 80% of the delay in the book(at nominal temp/voltage). Anyway, just FYI. I can't believe anyone would accidentally create this scenario, but I suppose that is what people thought as they were going down on the Titanic. Bryan ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: 21 Aug 2001 20:43:17 GMT Organization: California Institute of Technology, Pasadena Lines: 20 Message-ID: <9luh55$jak@gap.cco.caltech.edu> References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> NNTP-Posting-Host: hork.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsswitch.lcs.mit.edu!news.uchicago.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:9383 bryan@srccomp.com (Bryan) writes: >> The path through CLBs and routing to make an oscillator like that >> shown should be long enough to keep the frequency relatively low, >> compared to discrete logic. >> >> -- glen >The LUT oscillator that I created had 25% of the chip running at >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at >.45ns + .9ns or >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by >the book delays, which we have found actual routes to be 80% of the >delay What is the maximum clock speed for Virtex-II, FF, through one LUT, to another FF? Can Virtex-II run a design where most of the logic runs at that clock speed? -- glen ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Tue, 21 Aug 2001 16:23:24 -0700 Organization: Xilinx Lines: 32 Message-ID: <3B82ED6B.34E9A0CD@xilinx.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en To: glen herrmannsfeldt Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!68449!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!newshub.sdsu.edu!newspeer.cts.com!130.94.89.10.MISMATCH!news-out.spamkiller.net!propagator-la!news-in.superfeed.net!egsner!dfw-feed.news.verio.net!news.verio.net!nntp1.hal-pc.org!12.120.16.16.MISMATCH!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9370 At >300 MHz you are talkingabout tiny chunks of logic generating their own local clock. I built a frequency counter in XC4002XL three years ago, that resolved 420 MHz ( in the one flip-flop that matters). I am going for 1 GHz now, but not in a CLB flip-flop. Just for bragging rights. So it all depends... Peter Alfke, Xilinx Applications -------------------------------------------------------- glen herrmannsfeldt wrote: > bryan@srccomp.com (Bryan) writes: > > >> The path through CLBs and routing to make an oscillator like that > >> shown should be long enough to keep the frequency relatively low, > >> compared to discrete logic. > >> > >> -- glen > > >The LUT oscillator that I created had 25% of the chip running at > >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at > >.45ns + .9ns or > >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by > >the book delays, which we have found actual routes to be 80% of the > >delay > > What is the maximum clock speed for Virtex-II, FF, through one LUT, > to another FF? Can Virtex-II run a design where most of the logic > runs at that clock speed? > > -- glen ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Tue, 21 Aug 2001 16:50:23 -0700 Organization: Posted via Supernews, http://www.supernews.com Message-ID: References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> <3B815292.36EA31DE@algor.co.uk> X-Newsreader: Forte Agent 1.6/32.525 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: newsabuse@supernews.com Lines: 38 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!sn-xit-01!sn-post-02!sn-post-01!supernews.com!corp.supernews.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9388 On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz wrote: >Peter, > >On top of all the other useful stuff you contribute to CAF you have just answered a >long-standing (or burning ?) question of mine regarding the calibration of heat >sensing fingertips. Peter, my right forefinger is calibrated as follows: 50C - ok for infinite duration contact 52C - 10 seconds to pullaway 60C - 1 second to pullaway Interpolate linearly between points. Your digits may vary. We just got a cheap ($79) infrared temp sensor, which is cool (no pun, really) for scanning FPGAs on a board. John > >To go further and get another data point: Last summer I was wondering why our new >board wasn't doing anything from power-on. I, very briefly, put my finger on it & >came away with a large & painful blister that was still very sore 2 days later. > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > >What temp do you think the package would have reached ? ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 Date: Tue, 21 Aug 2001 17:21:30 -0700 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 998439704 216.103.85.188 (Tue, 21 Aug 2001 17:21:44 PDT) NNTP-Posting-Date: Tue, 21 Aug 2001 17:21:44 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!news-fra1.dfn.de!news0.de.colt.net!colt.net!dispose.news.demon.net!demon!howland.erols.net!netnews.com!newsfeed.nyc.globix.net!newsfeed.sjc.globix.net!cyclone-sf.pbi.net!206.13.28.144!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9408 On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: >What is the maximum clock speed for Virtex-II, FF, through one LUT, >to another FF? In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, about 666MHz . > Can Virtex-II run a design where most of the logic >runs at that clock speed? NO >-- glen --philip Philip Freidin Fliptronics ###### From: "Tim" Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Wed, 22 Aug 2001 11:21:42 +0100 Message-ID: <998476832.2468.0.nnrp-13.9e9832fa@news.demon.co.uk> References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 998476832 nnrp-13:2468 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Lines: 15 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!blackbush.xlink.net!blackbush.de.kpnqwest.net!newsfeed.freenet.de!newspeer.clara.net!news.clara.net!dispose.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9402 "Philip Freidin" wrote in message news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com... > On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: > >What is the maximum clock speed for Virtex-II, FF, through one LUT, > >to another FF? > > In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, > about 666MHz . > The mark of the beast. See alt.conspiracy.fpga ###### From: bryan@srccomp.com (Bryan) Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: 22 Aug 2001 07:44:24 -0700 Organization: http://groups.google.com/ Lines: 28 Message-ID: References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> NNTP-Posting-Host: 38.227.95.10 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 998491464 28126 127.0.0.1 (22 Aug 2001 14:44:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 22 Aug 2001 14:44:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9397 gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote in message news:<9luh55$jak@gap.cco.caltech.edu>... > bryan@srccomp.com (Bryan) writes: > > >> The path through CLBs and routing to make an oscillator like that > >> shown should be long enough to keep the frequency relatively low, > >> compared to discrete logic. > >> > >> -- glen > > >The LUT oscillator that I created had 25% of the chip running at > >.45ns(lut) + .5ns(route) or ~ 512Mhz and 75% of the chip running at > >.45ns + .9ns or > >~ 740Mhz. That is a Virtex-II 1000 speed 4. This of course is by > >the book delays, which we have found actual routes to be 80% of the > >delay > > What is the maximum clock speed for Virtex-II, FF, through one LUT, > to another FF? Can Virtex-II run a design where most of the logic > runs at that clock speed? > > -- glen I didn't say anything about using FFs. This is a design using nothing but LUTs. This design is not clocking latches. It is simpling toggling LUTs as fast as they will toggle. Bryan ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Wed, 22 Aug 2001 08:09:38 -0700 Organization: Xilinx Lines: 46 Message-ID: <3B83CB32.159FF093@xilinx.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> <3B815292.36EA31DE@algor.co.uk> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!12547!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!cambridge1-snf1.gtei.net!news.gtei.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9369 John, Make, model number, and where to buy the IR temp sensor? I get sooo many questions, and it would be worth its weight in gold to publicize this info! Austin John Larkin wrote: > On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz > wrote: > > >Peter, > > > >On top of all the other useful stuff you contribute to CAF you have just answered a > >long-standing (or burning ?) question of mine regarding the calibration of heat > >sensing fingertips. > > Peter, > > my right forefinger is calibrated as follows: > > 50C - ok for infinite duration contact > > 52C - 10 seconds to pullaway > > 60C - 1 second to pullaway > > Interpolate linearly between points. Your digits may vary. > > We just got a cheap ($79) infrared temp sensor, which is cool (no pun, > really) for scanning FPGAs on a board. > > John > > > > >To go further and get another data point: Last summer I was wondering why our new > >board wasn't doing anything from power-on. I, very briefly, put my finger on it & > >came away with a large & painful blister that was still very sore 2 days later. > > > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > > > >What temp do you think the package would have reached ? ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: 22 Aug 2001 18:42:59 GMT Organization: California Institute of Technology, Pasadena Lines: 17 Message-ID: <9m0ufj$ne6@gap.cco.caltech.edu> References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> <998476832.2468.0.nnrp-13.9e9832fa@news.demon.co.uk> NNTP-Posting-Host: hork.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!howland.erols.net!vixen.cso.uiuc.edu!news.uchicago.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:9422 "Philip Freidin" wrote in message news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com... > On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu wrote: > >What is the maximum clock speed for Virtex-II, FF, through one LUT, > >to another FF? > > In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, > about 666MHz . > So, again with careful design, one could have a design with about half the gates and FF changing state at 666MHz, or about 333MHz each. (That is, assuming random data bits.) About a factor of two from what was claimed for the oscillation modes. -- glen ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: <91c8otkustn3nvan3gibsv3p02o1hsh48f@4ax.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <9ls2g9$dc4@gap.cco.caltech.edu> <9luh55$jak@gap.cco.caltech.edu> <998476832.2468.0.nnrp-13.9e9832fa@news.demon.co.uk> <9m0ufj$ne6@gap.cco.caltech.edu> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 Date: Wed, 22 Aug 2001 15:32:03 -0700 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@pacbell.net X-Trace: nnrp5-w.sbc.net 998519538 216.103.85.188 (Wed, 22 Aug 2001 15:32:18 PDT) NNTP-Posting-Date: Wed, 22 Aug 2001 15:32:18 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!newsfeed.hanau.net!fr.clara.net!heighliner.fr.clara.net!feed2.onemain.com!feed1.onemain.com!cyclone-sf.pbi.net!206.13.28.183!nnrp5-w.sbc.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9438 On 22 Aug 2001 18:42:59 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: >"Philip Freidin" wrote in message >news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com... >> On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu wrote: >> >What is the maximum clock speed for Virtex-II, FF, through one LUT, >> >to another FF? >> >> In a V-II , -5 speed grade, M3.3.08i speed files, with careful placement, >> about 666MHz . >> > >So, again with careful design, one could have a design with about half >the gates and FF changing state at 666MHz, or about 333MHz each. >(That is, assuming random data bits.) About a factor of two from what >was claimed for the oscillation modes. >-- glen Not really. The average user that has abdicated responsibility for their design details to a synthesis tool and use typical design styles would be lucky to get a reasonable sized design (anything over 1000 gates) to run at more than 200MHz. So random data leads to a data toggle rate below 100MHz. In my previous post I wrote "careful placement". You wrote "careful design" I should have written "extremely detailed placement (multiple weeks for a few hundred gates)" All numbers above pulled out of thin air. Philip Freidin Philip Freidin Fliptronics ###### From: Dave Vanden Bout Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Thu, 23 Aug 2001 23:49:22 -0400 Organization: XESS Corp. Lines: 65 Message-ID: <3B85CEC2.5FF3BF53@xess.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> <3B815292.36EA31DE@algor.co.uk> <3B83CB32.159FF093@xilinx.com> NNTP-Posting-Host: a5.f7.8b.e9 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 24 Aug 2001 03:51:25 GMT X-Mailer: Mozilla 4.75 [en] (Win98; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!9421!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9491 Austin Lesea wrote: > John, > > Make, model number, and where to buy the IR temp sensor? > > I get sooo many questions, and it would be worth its weight in gold to publicize this > info! You can buy an Extech infrared thermometer from Techni-tool for $99.00. Measures 0 - 600 degrees F with a 6:1 field view. > > > Austin > > John Larkin wrote: > > > On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz > > wrote: > > > > >Peter, > > > > > >On top of all the other useful stuff you contribute to CAF you have just answered a > > >long-standing (or burning ?) question of mine regarding the calibration of heat > > >sensing fingertips. > > > > Peter, > > > > my right forefinger is calibrated as follows: > > > > 50C - ok for infinite duration contact > > > > 52C - 10 seconds to pullaway > > > > 60C - 1 second to pullaway > > > > Interpolate linearly between points. Your digits may vary. > > > > We just got a cheap ($79) infrared temp sensor, which is cool (no pun, > > really) for scanning FPGAs on a board. > > > > John > > > > > > > >To go further and get another data point: Last summer I was wondering why our new > > >board wasn't doing anything from power-on. I, very briefly, put my finger on it & > > >came away with a large & painful blister that was still very sore 2 days later. > > > > > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > > > > > >What temp do you think the package would have reached ? -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || ###### From: Austin Lesea Newsgroups: comp.arch.fpga Subject: Re: hardware damage to a Virtex or Spartan-II? Date: Fri, 24 Aug 2001 08:43:13 -0700 Organization: Xilinx Lines: 66 Message-ID: <3B867611.949165E6@xilinx.com> References: <3B7CE735.5B3FF6D2@wanabe.nl> <3B8145C0.3D5547D3@xilinx.com> <3B815292.36EA31DE@algor.co.uk> <3B83CB32.159FF093@xilinx.com> <3B85CEC2.5FF3BF53@xess.com> NNTP-Posting-Host: 149.199.9.10 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en,pdf Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.media.kyoto-u.ac.jp!sjc-peer.news.verio.net!dfw-feed.news.verio.net!news.verio.net!nntp1.hal-pc.org!12.120.16.16.MISMATCH!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9444 Dave, Thanks! Austin Dave Vanden Bout wrote: > Austin Lesea wrote: > > > John, > > > > Make, model number, and where to buy the IR temp sensor? > > > > I get sooo many questions, and it would be worth its weight in gold to publicize this > > info! > > You can buy an Extech infrared thermometer from Techni-tool for $99.00. Measures 0 - 600 > degrees F with a 6:1 field view. > > > > > > > Austin > > > > John Larkin wrote: > > > > > On Mon, 20 Aug 2001 19:10:26 +0100, Rick Filipkiewicz > > > wrote: > > > > > > >Peter, > > > > > > > >On top of all the other useful stuff you contribute to CAF you have just answered a > > > >long-standing (or burning ?) question of mine regarding the calibration of heat > > > >sensing fingertips. > > > > > > Peter, > > > > > > my right forefinger is calibrated as follows: > > > > > > 50C - ok for infinite duration contact > > > > > > 52C - 10 seconds to pullaway > > > > > > 60C - 1 second to pullaway > > > > > > Interpolate linearly between points. Your digits may vary. > > > > > > We just got a cheap ($79) infrared temp sensor, which is cool (no pun, > > > really) for scanning FPGAs on a board. > > > > > > John > > > > > > > > > > >To go further and get another data point: Last summer I was wondering why our new > > > >board wasn't doing anything from power-on. I, very briefly, put my finger on it & > > > >came away with a large & painful blister that was still very sore 2 days later. > > > > > > > >Cause = BGA chip pinout mirrored (not by me I hasten to add). > > > > > > > >What temp do you think the package would have reached ? > > -- > || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || > || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || > || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||