From: Eric Inazaki Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Building a clock out of a PLD Date: Tue, 14 Aug 2001 16:43:07 -0500 Organization: Washington Univ Lines: 10 Message-ID: <140820011643075782%penfold@deadbeat.edu> NNTP-Posting-Host: as0-isdn-72.wustl.edu Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: newsreader.wustl.edu 997825682 6755 128.252.41.72 (14 Aug 2001 21:48:02 GMT) X-Complaints-To: usenet@newsreader.wustl.edu NNTP-Posting-Date: Tue, 14 Aug 2001 21:48:02 +0000 (UTC) Mail-Copies-To: nobody User-Agent: YA-NewsWatcher/3.1.8 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!news.cc.ukans.edu!stl-feed.news.verio.net!newsreader.wustl.edu!penfold Xref: chonsp.franklin.ch comp.arch.fpga:9186 I have a PLD circuit which requires a clock signal. I'm thinking it'd be really nice if I could use some of the otherwise unused gates (along with a cap and a couple of resistors) to generate the clock. Is this a bad idea, doomed to failure or is this sort of thing done all the time? With respect to timing circuits in general, can PLDs be used in place of discreet logic gates? In this particular case I'm using a Lattice ispLSI1016E. thanks, eric ###### Message-ID: <3B79C344.682A@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD References: <140820011643075782%penfold@deadbeat.edu> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 54 Date: Wed, 15 Aug 2001 12:33:08 +1200 NNTP-Posting-Host: 203.79.102.82 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 997836791 203.79.102.82 (Wed, 15 Aug 2001 12:53:11 NZST) NNTP-Posting-Date: Wed, 15 Aug 2001 12:53:11 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!skynet.be!skynet.be!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9179 Eric Inazaki wrote: > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > be really nice if I could use some of the otherwise unused gates (along > with a cap and a couple of resistors) to generate the clock. > Is this a bad idea, doomed to failure or is this sort of thing done all the > time? Somewhere in-between :-) Low Frequency RC oscillators, of 2/3 terminal design, are impractical in CPLD due to lack of pin hysteresis. For low Freq sources, we use HEF4541, available in SO14. For medium Freq, a TinyLogic single gate makes a good osc source. You can quite safely build a 3 terminal OSC, (for higher precision), using an external TinyLogic gate and a PLD 'gate'. These solutions also keep the Icc down. At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal osc, with care. You need to do your own margin testing. Better may be to removce the R's and C's entirely: We have designed completely buried oscillators in the ATMEL ATF150X family of cpld, using a chain of foldbacks. I am not used to Lattice, but the Atmel devices have an option for a single inverter in the 'corner of a macrocell', that can be used for simple tasks, without loosing the whole macrocell. The foldback delay is 2.8nS/5.5nS for low/High power MC switch, so the lowest Freq from a single block OSC of 15 foldbacks in series, is 6MHz and 12MHz. This will of course vary with Vcc, Temperature and Process changes, but many designs do not care too much about the clock freq. You can also chain these Foldback's as delay lines. > With respect to timing circuits in general, can PLDs be used in > place of discreet logic gates? If you mean RC timing, like 4528, 4093, 40106, HC14, then no. If you mean counter chains, like 4060/4040 then yes. > In this particular case I'm using a > Lattice ispLSI1016E. > > thanks, > eric ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nz ###### From: Eric Inazaki Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: Tue, 14 Aug 2001 20:44:29 -0500 Organization: Washington Univ Lines: 78 Message-ID: <140820012044292591%penfold@deadbeat.edu> References: <140820011643075782%penfold@deadbeat.edu> <3B79C344.682A@designtools.co.nz> NNTP-Posting-Host: as0-isdn-13.wustl.edu Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: newsreader.wustl.edu 997840164 11045 128.252.41.13 (15 Aug 2001 01:49:24 GMT) X-Complaints-To: usenet@newsreader.wustl.edu NNTP-Posting-Date: Wed, 15 Aug 2001 01:49:24 +0000 (UTC) Mail-Copies-To: nobody User-Agent: YA-NewsWatcher/3.1.8 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!headwall.stanford.edu!unlnews.unl.edu!newsreader.wustl.edu!penfold Xref: chonsp.franklin.ch comp.arch.fpga:9185 In article <3B79C344.682A@designtools.co.nz>, Jim Granville wrote: > Eric Inazaki wrote: > > > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > be really nice if I could use some of the otherwise unused gates (along > > with a cap and a couple of resistors) to generate the clock. > > Is this a bad idea, doomed to failure or is this sort of thing done all the > > time? > > Somewhere in-between :-) I'm looking to do something in the few to few-tens of kHz. Would you consider that to be at the low end of the scale? The circuit I have in mind has an inverter whose output is the clk signal. This output also feeds a resistor (R1). The other end of R1 is connected to a cap (C) and another resistor (R2). The other end of R2 goes to the input of a buffer. The buffer's output, the inverter's input and the other leg of C are all tied together. (I know, pictures would be a big help.) BTW, is this what you mean by 3 terminal design? > > Low Frequency RC oscillators, of 2/3 terminal design, are impractical > in > CPLD due to lack of pin hysteresis. Ouch, that could be a problem. I should go look through my data sheets. I don't suppose there are any PLDs that have Schmitt trigger inputs (either configurable, or hard wired)? > For low Freq sources, we use HEF4541, available in SO14. > For medium Freq, a TinyLogic single gate makes a good osc source. > You can quite safely build a 3 terminal OSC, (for higher precision), > using an external TinyLogic gate and a PLD 'gate'. > > These solutions also keep the Icc down. > For my purposes, if I can't do the PLD thing I'll probably just break out a 555. I only need 2kHz or so and accuracy and stability are pretty much non-issues (or so I hope). > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > osc, with care. You need to do your own margin testing. > > Better may be to removce the R's and C's entirely: > > We have designed completely buried oscillators in the ATMEL > ATF150X family of cpld, using a chain of foldbacks. > Any chance you could point me towards an app note, text reference or sample circuits? > > > With respect to timing circuits in general, can PLDs be used in > > place of discreet logic gates? > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > If you mean counter chains, like 4060/4040 then yes. > > I'm thinking either a delayed monostable or a straight delay. The delay and pulse width would be on the order of few to tens of microseconds. > ======= 80x51 Tools & PLD IP Specialists ========= > = http://www.DesignTools.co.nz Thanks for all the input, you've given me quite a bit to chew on. I've actually just started doing things w/ PLDs. PLDs rock, especially these isp types. eric ###### From: "Maki" Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: Wed, 15 Aug 2001 11:02:56 +0200 Organization: Public news server of EUnet Yugoslavia Lines: 98 Message-ID: <9lddqt$4f7$1@news.eunet.yu> References: <140820011643075782%penfold@deadbeat.edu> <3B79C344.682A@designtools.co.nz> <140820012044292591%penfold@deadbeat.edu> NNTP-Posting-Host: p-5.210.eunet.yu X-Trace: news.eunet.yu 997866142 4583 213.240.5.210 (15 Aug 2001 09:02:22 GMT) X-Complaints-To: abuse@EUnet.yu NNTP-Posting-Date: Wed, 15 Aug 2001 09:02:22 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2314.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2314.1300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!npeer.kpnqwest.net!EUnet.yu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9175 For that small frequency I would recommend 40106 ST hex inverter. You only need resistor between in and out an cap between input and gnd. Rest of the buffers You can tie in parallel so you can have more power on the output. This config works fine to approx. 1Mhz with 5V Vcc. And less number of components comparing with 555 design. Regards M. -- Veselic Mladen Laboratorija Sigma ECO Izenjering Eric Inazaki wrote in message news:140820012044292591%penfold@deadbeat.edu... > In article <3B79C344.682A@designtools.co.nz>, Jim Granville > wrote: > > > Eric Inazaki wrote: > > > > > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > > be really nice if I could use some of the otherwise unused gates (along > > > with a cap and a couple of resistors) to generate the clock. > > > Is this a bad idea, doomed to failure or is this sort of thing done all the > > > time? > > > > Somewhere in-between :-) > > I'm looking to do something in the few to few-tens of kHz. Would you > consider that to be at the low end of the scale? > > The circuit I have in mind has an inverter whose output is the clk > signal. This output also feeds a resistor (R1). The other end of > R1 is connected to a cap (C) and another resistor (R2). The other > end of R2 goes to the input of a buffer. The buffer's output, the > inverter's input and the other leg of C are all tied together. (I > know, pictures would be a big help.) BTW, is this what you mean by > 3 terminal design? > > > > > Low Frequency RC oscillators, of 2/3 terminal design, are impractical > > in > > CPLD due to lack of pin hysteresis. > > Ouch, that could be a problem. I should go look through my data sheets. > I don't suppose there are any PLDs that have Schmitt trigger inputs > (either configurable, or hard wired)? > > > For low Freq sources, we use HEF4541, available in SO14. > > For medium Freq, a TinyLogic single gate makes a good osc source. > > You can quite safely build a 3 terminal OSC, (for higher precision), > > using an external TinyLogic gate and a PLD 'gate'. > > > > These solutions also keep the Icc down. > > > > For my purposes, if I can't do the PLD thing I'll probably just break > out a 555. I only need 2kHz or so and accuracy and stability are pretty > much non-issues (or so I hope). > > > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > > osc, with care. You need to do your own margin testing. > > > > Better may be to removce the R's and C's entirely: > > > > We have designed completely buried oscillators in the ATMEL > > ATF150X family of cpld, using a chain of foldbacks. > > > > Any chance you could point me towards an app note, text reference > or sample circuits? > > > > > > With respect to timing circuits in general, can PLDs be used in > > > place of discreet logic gates? > > > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > > If you mean counter chains, like 4060/4040 then yes. > > > > > > I'm thinking either a delayed monostable or a straight delay. > The delay and pulse width would be on the order of few to tens > of microseconds. > > > ======= 80x51 Tools & PLD IP Specialists ========= > > = http://www.DesignTools.co.nz > > Thanks for all the input, you've given me quite a bit to chew on. > I've actually just started doing things w/ PLDs. PLDs rock, especially > these isp types. > > eric ###### Message-ID: <3B7A49C5.91A@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD References: <140820011643075782%penfold@deadbeat.edu> <3B79C344.682A@designtools.co.nz> <140820012044292591%penfold@deadbeat.edu> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 80 Date: Wed, 15 Aug 2001 22:07:01 +1200 NNTP-Posting-Host: 203.79.102.214 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 997871222 203.79.102.214 (Wed, 15 Aug 2001 22:27:02 NZST) NNTP-Posting-Date: Wed, 15 Aug 2001 22:27:02 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!skynet.be!skynet.be!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9177 Eric Inazaki wrote: > > In article <3B79C344.682A@designtools.co.nz>, Jim Granville > wrote: > > I'm looking to do something in the few to few-tens of kHz. Would you > consider that to be at the low end of the scale? > > The circuit I have in mind has an inverter whose output is the clk > signal. This output also feeds a resistor (R1). The other end of > R1 is connected to a cap (C) and another resistor (R2). The other > end of R2 goes to the input of a buffer. The buffer's output, the > inverter's input and the other leg of C are all tied together. (I > know, pictures would be a big help.) BTW, is this what you mean by > 3 terminal design? Yes. When building this from non Hyst elements, the NonInverter (CAP) stage should go first, then the inverter (Resistor) stage. That way, regenerative feedback comes first, then the slower RC -ve feedback can come later. > > For low Freq sources, we use HEF4541, available in SO14. > > For medium Freq, a TinyLogic single gate makes a good osc source. > > You can quite safely build a 3 terminal OSC, (for higher precision), > > using an external TinyLogic gate and a PLD 'gate'. > > > > These solutions also keep the Icc down. > > > > For my purposes, if I can't do the PLD thing I'll probably just break > out a 555. I only need 2kHz or so and accuracy and stability are pretty > much non-issues (or so I hope). CMOS 555's are also a good solution - higher Icc than a 4541/40106, but fewer pins.. > > > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal > > osc, with care. You need to do your own margin testing. > > > > Better may be to removce the R's and C's entirely: > > > > We have designed completely buried oscillators in the ATMEL > > ATF150X family of cpld, using a chain of foldbacks. > > > > Any chance you could point me towards an app note, text reference > or sample circuits? I've put an example on our web: http://www.designtools.co.nz/lcd32ser.zip This is a LCD serial interface driver, and has a chain of foldbacks as a delay line, used for a Latch+XOR to drive a LCD backplane, using a ATF1502ASL. > > > > > > With respect to timing circuits in general, can PLDs be used in > > > place of discreet logic gates? > > > > If you mean RC timing, like 4528, 4093, 40106, HC14, then no. > > If you mean counter chains, like 4060/4040 then yes. > > > > > > I'm thinking either a delayed monostable or a straight delay. > The delay and pulse width would be on the order of few to tens > of microseconds. For this scale, consider a monostable-counter, using the buried Foldback OSC, and a triggered saturating counter - you'll get zero external components, and a time resolution of ~166nS - jg ###### From: "luigi funes" Newsgroups: comp.arch.fpga,sci.electronics.design References: <140820011643075782%penfold@deadbeat.edu> Subject: Re: Building a clock out of a PLD Lines: 25 X-Newsreader: Microsoft Outlook Express 4.72.3110.5 X-MimeOLE: Produced By Microsoft MimeOLE V4.72.3110.3 Message-ID: Date: Wed, 15 Aug 2001 16:07:57 GMT NNTP-Posting-Host: 151.33.134.115 X-Complaints-To: abuse@iol.it X-Trace: news.infostrada.it 997891677 151.33.134.115 (Wed, 15 Aug 2001 18:07:57 MET DST) NNTP-Posting-Date: Wed, 15 Aug 2001 18:07:57 MET DST Organization: [Infostrada] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.tele.dk!small.news.tele.dk!212.141.84.59!newsserver.inwind.it!inwind.it!nntp.infostrada.it!news.infostrada.it!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9196 Eric Inazaki ha scritto nel messaggio <140820011643075782%penfold@deadbeat.edu>... >With respect to timing circuits in general, can PLDs be used in >place of discreet logic gates? In this particular case I'm using a >Lattice ispLSI1016E. In my esperience, yes. I did oscillators just with Lattice 1K and 2K CPLD series. You have to configure a macrocell as a simple inverter and connect the input and the output to two adjacent pins. Internally you connect the macrocell output to the clock lines. Externally, you connect input and output with a resistor and the input with a capacitor to ground. This works in a very wide frequency range, also shorting input and output directly and without any capacitor to obtain easily 100-200 MHz! Unfortunately this kind of oscillator is unreliable as it is unstable and sensitive to noise, so you have to use it with caution. Luigi ###### From: Ken Smith Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: 15 Aug 2001 18:25:12 GMT Organization: a2i network Lines: 25 Message-ID: <9leeq8$s5t$1@samba.rahul.net> References: <140820011643075782%penfold@deadbeat.edu> NNTP-Posting-Host: waltz.rahul.net NNTP-Posting-User: kensmith Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!jfk3-feed1.news.digex.net!sfo2-feed1.news.digex.net!intermedia!feedwest.news.agis.net!us.telia.net!news.mainstreet.net!bug.rahul.net!samba.rahul.net!rahul.net!a2i!kensmith.a2i!kensmith Xref: chonsp.franklin.ch comp.arch.fpga:9178 I've done this with other types of PLDs. You need to make 2 inverters in the PAL. The non-inverted output connects to the input via a capacitor, or a resistor and capacitor in series. The inverting output connects via a resistor to the input. It is the same circuit you make from a CMOS logic gate. You take the clock from the second inverter's output. In article <140820011643075782%penfold@deadbeat.edu>, Eric Inazaki wrote: >I have a PLD circuit which requires a clock signal. I'm thinking it'd >be really nice if I could use some of the otherwise unused gates (along >with a cap and a couple of resistors) to generate the clock. Is this >a bad idea, doomed to failure or is this sort of thing done all the >time? With respect to timing circuits in general, can PLDs be used in >place of discreet logic gates? In this particular case I'm using a >Lattice ispLSI1016E. > >thanks, >eric -- -- kensmith@rahul.net forging knowledge ###### From: Eric Inazaki Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: Wed, 15 Aug 2001 16:38:42 -0500 Organization: Washington University in St. Louis Lines: 32 Message-ID: References: <140820011643075782%penfold@deadbeat.edu> <9leeq8$s5t$1@samba.rahul.net> Reply-To: einazaki@mac.com NNTP-Posting-Host: deadbeat.wustl.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: newsreader.wustl.edu 997911651 14361 128.252.125.52 (15 Aug 2001 21:40:51 GMT) X-Complaints-To: usenet@newsreader.wustl.edu NNTP-Posting-Date: Wed, 15 Aug 2001 21:40:51 +0000 (UTC) X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newscore.univie.ac.at!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!headwall.stanford.edu!unlnews.unl.edu!newsreader.wustl.edu!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9271 Do you recall what kind of PLD you used? Also, what frequency were you running? Thanks, eric On 15 Aug 2001 18:25:12 GMT, Ken Smith wrote: > >I've done this with other types of PLDs. You need to make 2 inverters in >the PAL. The non-inverted output connects to the input via a capacitor, >or a resistor and capacitor in series. The inverting output connects via >a resistor to the input. It is the same circuit you make from a CMOS >logic gate. You take the clock from the second inverter's output. > >In article <140820011643075782%penfold@deadbeat.edu>, >Eric Inazaki wrote: >>I have a PLD circuit which requires a clock signal. I'm thinking it'd >>be really nice if I could use some of the otherwise unused gates (along >>with a cap and a couple of resistors) to generate the clock. Is this >>a bad idea, doomed to failure or is this sort of thing done all the >>time? With respect to timing circuits in general, can PLDs be used in >>place of discreet logic gates? In this particular case I'm using a >>Lattice ispLSI1016E. >> >>thanks, >>eric > > >-- ###### From: jmrice@ntlworld.com (Martin Rice) Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: 15 Aug 2001 14:47:04 -0700 Organization: http://groups.google.com/ Lines: 36 Message-ID: References: <140820011643075782%penfold@deadbeat.edu> NNTP-Posting-Host: 62.253.64.5 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 997912025 11878 127.0.0.1 (15 Aug 2001 21:47:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: 15 Aug 2001 21:47:05 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9266 Eric Inazaki wrote in message news:<140820011643075782%penfold@deadbeat.edu>... > I have a PLD circuit which requires a clock signal. I'm thinking it'd > be really nice if I could use some of the otherwise unused gates (along > with a cap and a couple of resistors) to generate the clock. Is this > a bad idea, doomed to failure or is this sort of thing done all the > time? With respect to timing circuits in general, can PLDs be used in > place of discreet logic gates? In this particular case I'm using a > Lattice ispLSI1016E. > > thanks, > eric I've used a two-inverter circuit oscillator, using gates inside a Coolrunner (Xilinx) PLD. The circuit goes: inverter between nodes A and B inverter between nodes B and C 100nF between C and A 10k between A and B I got nice square waves at B and C; exponential decay at A, 1.7ms period. Unfortunately, the signal generated was useless as a clock for further circuits inside the CPLD! Not sure why... the square waves had nice clean edges. I guess the chip didn't like the slow edges at A. I think your inverter/buffer circuit would have the same problem since there is an exponential decay waveform at the input to the buffer. BTW, I think your circuit would work (in non-CPLD implementation) if you replace R2 with short. I ended up using 555. R from output to threshold/trigger; C from threshold/trigger to GND. Gives nice output. Rarely seen this simple circuit published. Only drawback I know is that output doesn't go rail to rail for bipolar version (but does for CMOS). Have fun. ###### Message-ID: <3B7AEDED.5DBBD09A@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.19 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD References: <140820011643075782%penfold@deadbeat.edu> <3B7B0BF7.7DA0@designtools.co.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 79 Date: Wed, 15 Aug 2001 15:47:25 -0600 NNTP-Posting-Host: 207.153.6.60 X-Trace: newsfeed.slurp.net 997921282 207.153.6.60 (Wed, 15 Aug 2001 19:21:22 CDT) NNTP-Posting-Date: Wed, 15 Aug 2001 19:21:22 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9224 Jim Granville wrote: > > Martin Rice wrote: > > > > Eric Inazaki wrote in message news:<140820011643075782%penfold@deadbeat.edu>... > > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > > be really nice if I could use some of the otherwise unused gates (along > > > with a cap and a couple of resistors) to generate the clock. Is this > > > a bad idea, doomed to failure or is this sort of thing done all the > > > time? With respect to timing circuits in general, can PLDs be used in > > > place of discreet logic gates? In this particular case I'm using a > > > Lattice ispLSI1016E. > > > > > > thanks, > > > eric > > > > I've used a two-inverter circuit oscillator, using gates inside a > > Coolrunner (Xilinx) PLD. The circuit goes: > > inverter between nodes A and B > > inverter between nodes B and C > > 100nF between C and A > > 10k between A and B > > > > I got nice square waves at B and C; exponential decay at A, 1.7ms > > period. > > > > Unfortunately, the signal generated was useless as a clock for further > > circuits inside the CPLD! Not sure why... the square waves had nice > > clean edges. I guess the chip didn't like the slow edges at A. I > > think your inverter/buffer circuit would have the same problem since > > there is an exponential decay waveform at the input to the buffer. > > What looks 'clean' to even a 100Mhz Scope may not be a clean-enough > clock signal, especially if it comes from a slow-slew oscillator! > > > BTW, I think your circuit would work (in non-CPLD implementation) if > > you replace R2 with short. > > The second R is not needed for timing, what it does is provide > overdrive > protection, and also improves stability. > Without it, you try and drive nominally 50% beyond the rails on the > RC node. > We have used 1R, and two equal C's to avoid both the overdrive, > and the very 'sensistive' node that an R.R.C oscillator gives. > But you take a hit in absolute tolerance, as C's are lower tolerance > than R's. > > A good challenge for students, is to get them to design a LR oscillator > ! > > > > I ended up using 555. R from output to threshold/trigger; > > C from threshold/trigger to GND. Gives nice output. Rarely seen this > > simple circuit published. > > Probably because of > a) The nasty loads often seen on 555 lash-ups :-) > b) The Bipolar 555's did not go rail-rail on the output > so Freq tolerance is not as good. > > You are right tho, a single RC two terminal config works, > ( same as HC14/40106 circuit) and well with a CMOS version > - which are just ~25c. > > Because C555's are 'everywhere', they are a better education/prototype > choice than TinyLogic, but I have seen designers swear they will never > ship anything with a 555 in it :-) > > > Only drawback I know is that output doesn't > > go rail to rail for bipolar version (but does for CMOS). > > -jg I would just use the good old fashioned Schmitt triggers. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics. ###### Message-ID: <3B7B0BF7.7DA0@designtools.co.nz> From: Jim Granville Reply-To: jim.granville@designtools.co.nz Organization: Mandeno Granville elect X-Mailer: Mozilla 3.0C-XTRA (Win95; I) MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD References: <140820011643075782%penfold@deadbeat.edu> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 71 Date: Thu, 16 Aug 2001 11:55:35 +1200 NNTP-Posting-Host: 203.79.102.25 X-Complaints-To: abuse@tsnz.net X-Trace: news02.tsnz.net 997919464 203.79.102.25 (Thu, 16 Aug 2001 11:51:04 NZST) NNTP-Posting-Date: Thu, 16 Aug 2001 11:51:04 NZST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newscore.gigabell.net!newsfeed00.sul.t-online.de!t-online.de!nntp-relay.ihug.net!ihug.co.nz!usenet.net.nz!203.96.216.22!news!newsfeed01.tsnz.net!news02.tsnz.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9235 Martin Rice wrote: > > Eric Inazaki wrote in message news:<140820011643075782%penfold@deadbeat.edu>... > > I have a PLD circuit which requires a clock signal. I'm thinking it'd > > be really nice if I could use some of the otherwise unused gates (along > > with a cap and a couple of resistors) to generate the clock. Is this > > a bad idea, doomed to failure or is this sort of thing done all the > > time? With respect to timing circuits in general, can PLDs be used in > > place of discreet logic gates? In this particular case I'm using a > > Lattice ispLSI1016E. > > > > thanks, > > eric > > I've used a two-inverter circuit oscillator, using gates inside a > Coolrunner (Xilinx) PLD. The circuit goes: > inverter between nodes A and B > inverter between nodes B and C > 100nF between C and A > 10k between A and B > > I got nice square waves at B and C; exponential decay at A, 1.7ms > period. > > Unfortunately, the signal generated was useless as a clock for further > circuits inside the CPLD! Not sure why... the square waves had nice > clean edges. I guess the chip didn't like the slow edges at A. I > think your inverter/buffer circuit would have the same problem since > there is an exponential decay waveform at the input to the buffer. What looks 'clean' to even a 100Mhz Scope may not be a clean-enough clock signal, especially if it comes from a slow-slew oscillator! > BTW, I think your circuit would work (in non-CPLD implementation) if > you replace R2 with short. The second R is not needed for timing, what it does is provide overdrive protection, and also improves stability. Without it, you try and drive nominally 50% beyond the rails on the RC node. We have used 1R, and two equal C's to avoid both the overdrive, and the very 'sensistive' node that an R.R.C oscillator gives. But you take a hit in absolute tolerance, as C's are lower tolerance than R's. A good challenge for students, is to get them to design a LR oscillator ! > I ended up using 555. R from output to threshold/trigger; > C from threshold/trigger to GND. Gives nice output. Rarely seen this > simple circuit published. Probably because of a) The nasty loads often seen on 555 lash-ups :-) b) The Bipolar 555's did not go rail-rail on the output so Freq tolerance is not as good. You are right tho, a single RC two terminal config works, ( same as HC14/40106 circuit) and well with a CMOS version - which are just ~25c. Because C555's are 'everywhere', they are a better education/prototype choice than TinyLogic, but I have seen designers swear they will never ship anything with a 555 in it :-) > Only drawback I know is that output doesn't > go rail to rail for bipolar version (but does for CMOS). -jg ###### From: Ken Smith Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: 16 Aug 2001 00:33:35 GMT Organization: a2i network Lines: 15 Message-ID: <9lf4cv$302$1@samba.rahul.net> References: <140820011643075782%penfold@deadbeat.edu> <9leeq8$s5t$1@samba.rahul.net> NNTP-Posting-Host: waltz.rahul.net NNTP-Posting-User: kensmith Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!informatik.tu-muenchen.de!news.csl-gmbh.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!fr.usenet-edu.net!usenet-edu.net!feed.ac-versailles.fr!news-out.spamkiller.net!propagator-la!news-in.superfeed.net!feedwest.news.agis.net!us.telia.net!news.mainstreet.net!bug.rahul.net!samba.rahul.net!rahul.net!a2i!kensmith.a2i!kensmith Xref: chonsp.franklin.ch comp.arch.fpga:9227 In article , Eric Inazaki wrote: >Do you recall what kind of PLD you used? Also, what frequency were >you running? In one case is was a T.I. TICPAL22V10Z running at about 5KHz. In another case it was an I.C.T. 7024 running at about 100KHz I've also made XTAL oscillators using PALs a the inverter. -- -- kensmith@rahul.net forging knowledge ###### From: Ken Smith Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD Date: 16 Aug 2001 00:41:22 GMT Organization: a2i network Lines: 26 Message-ID: <9lf4ri$330$1@samba.rahul.net> References: <140820011643075782%penfold@deadbeat.edu> NNTP-Posting-Host: waltz.rahul.net NNTP-Posting-User: kensmith Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!feedwest.news.agis.net!us.telia.net!news.mainstreet.net!bug.rahul.net!samba.rahul.net!rahul.net!a2i!kensmith.a2i!kensmith Xref: chonsp.franklin.ch comp.arch.fpga:9228 In article , Martin Rice wrote: [.. RC oscillator on Cool runner...] >Unfortunately, the signal generated was useless as a clock for further >circuits inside the CPLD! Not sure why... the square waves had nice >clean edges. I guess the chip didn't like the slow edges at A. There are some funnies in the Cool-Runner that I doubt have ever been documented. If you use it for a XTAL oscillator, it is best to use up another whole cell just to buffer the signal going to the clock pin. I think the transistors in the input circuits respond up to the GHz range to funnies on the edge. >I ended up using 555. R from output to threshold/trigger; >C from threshold/trigger to GND. Gives nice output. Rarely seen this >simple circuit published. Only drawback I know is that output doesn't >go rail to rail for bipolar version (but does for CMOS). The output of the LM555 can have cross over distortion on it. If you use Pin 7 (I think) the open collector transistor driving a resistor makes quite a nice logic signal. -- -- kensmith@rahul.net forging knowledge ###### From: "Andy Peters com"> X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: Building a clock out of a PLD References: <140820011643075782%penfold@deadbeat.edu> <3B7B0BF7.7DA0@designtools.co.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 12 Message-ID: Date: Thu, 16 Aug 2001 20:33:54 GMT NNTP-Posting-Host: 24.221.131.16 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 997994034 24.221.131.16 (Thu, 16 Aug 2001 13:33:54 PDT) NNTP-Posting-Date: Thu, 16 Aug 2001 13:33:54 PDT Organization: EarthLink Inc. -- http://www.EarthLink.net X-Received-Date: Thu, 16 Aug 2001 13:31:17 PDT (newsmaster1.prod.itd.earthlink.net) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!29165!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!newsfeed1.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:9221 Jim Granville wrote: > Because C555's are 'everywhere', they are a better education/prototype > choice than TinyLogic, but I have seen designers swear they will never > ship anything with a 555 in it :-) Jim, The main reason for not shipping something with a 555 in it is because you've got to trim each and every one. And once you trim it, how do you know that it stays trimmed in the field? --andy