From: Daniel =?iso-8859-1?Q?Ha=F1czewski?= Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Mon, 23 Jul 2001 13:03:36 +0200 Organization: tp.internet - http://www.tpi.pl Lines: 29 Message-ID: <3B5C0488.1024FB0E@wp.pl> References: <3B5BDDAD.9DBA32BA@IPricot.com> NNTP-Posting-Host: pe211.poznan.cvx.ppp.tpnet.pl Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: news.tpi.pl 995886012 14328 213.76.76.211 (23 Jul 2001 11:00:12 GMT) X-Complaints-To: usenet@tpi.pl NNTP-Posting-Date: 23 Jul 2001 11:00:12 GMT X-Accept-Language: en X-Mailer: Mozilla 4.6 [en] (WinNT; I) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed1.telenordia.se!algonet!news.man.lodz.pl!newsfeed.silweb.pl!news.tpi.pl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8455 Hi, I have also made this cable and the only problem I met was cable length. Xilinx advices wire connection between JTAG header and Parallel III electronics to be "as short as possible" and between electronics and LPT port no longer than 2m. I have placed electronics inside standard DSUB25 connector and according to Xilinx's schematic JTAG-electronics cable length musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to JTAG signal lines and now my cable has 2m and works without reservation. I haven't tried to make it longer... Regards Daniel Nicolas Matringe wrote: > Hi > I've built a Xilinx Parallel cable according to the schematics available > on Xilinx's site and it doesn't work. When I use the original cable > everything is fine so my board is OK. I looked at the signals with an > oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle > on the board), except that TDO stays high. Any idea? > > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/ ###### Message-ID: <3B5CB922.1090D05E@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem References: <3B5BDDAD.9DBA32BA@IPricot.com> <3B5C0488.1024FB0E@wp.pl> Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 28 Date: Tue, 24 Jul 2001 00:54:10 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 995932453 62.254.210.251 (Tue, 24 Jul 2001 00:54:13 BST) NNTP-Posting-Date: Tue, 24 Jul 2001 00:54:13 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!freenix!grolier!dispose.news.demon.net!demon!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8345 Daniel Hańczewski wrote: > Hi, > > I have also made this cable and the only problem I met was cable length. > Xilinx advices wire connection between JTAG header and Parallel III > electronics to be "as short as possible" and between electronics and LPT > port no longer than 2m. I have placed electronics inside standard DSUB25 > connector and according to Xilinx's schematic JTAG-electronics cable length > musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to > JTAG signal lines and now my cable has 2m and works without reservation. I > haven't tried to make it longer... > > Regards > Daniel > No real criticism Daniel but I've heard this sort of thing a lot but I reckon the length thing is basically voodoo. I've run 3x 3 meter Centronics extension cables + the Parallel-3 & configured CPLDs with not problem (back in the early days of the JTAG programmer when it didn't run on Win95 I had to do this to reach the NT box on the far side of the office). Now our boards have the Xilinx P-III h/w on them & it only takes 2 extension cables. ###### From: Daniel =?iso-8859-1?Q?Ha=F1czewski?= Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Tue, 24 Jul 2001 16:13:08 +0200 Organization: tp.internet - http://www.tpi.pl Lines: 45 Message-ID: <3B5D8273.A87AEDEC@wp.pl> References: <3B5BDDAD.9DBA32BA@IPricot.com> <3B5C0488.1024FB0E@wp.pl> <3B5CB922.1090D05E@algor.co.uk> NNTP-Posting-Host: pe73.poznan.cvx.ppp.tpnet.pl Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: news.tpi.pl 995983783 8649 213.76.76.73 (24 Jul 2001 14:09:43 GMT) X-Complaints-To: usenet@tpi.pl NNTP-Posting-Date: 24 Jul 2001 14:09:43 GMT X-Accept-Language: en X-Mailer: Mozilla 4.6 [en] (WinNT; I) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!news-fra1.dfn.de!news.man.poznan.pl!news.man.lodz.pl!newsfeed.silweb.pl!news.tpi.pl!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8460 Well, actually it seems that I put a jinx on my cable - just a few hour ago I noted first problem with it. Something went wrong during XC9572 CPLD programming and when I used my old 0,5m cable everything was ok. Sorry for trying to be wiser than Xilinx people. However the cable has 2m and I have used it around 50 times programming 3 different Xilinx devices (XC9500 family) and everything worked fine...until now. Maybe I had too much luck...? By the way. I'm working on new project where my CPLD is placed on PCI card. Can I somehow use PCI bus to program CPLD? This would be a gret help because I could change configuration without opening computer case. Where can I look for JTAG protocol and the proper software? Best regards Daniel Rick Filipkiewicz wrote: > Daniel Hańczewski wrote: > > > Hi, > > > > I have also made this cable and the only problem I met was cable length. > > Xilinx advices wire connection between JTAG header and Parallel III > > electronics to be "as short as possible" and between electronics and LPT > > port no longer than 2m. I have placed electronics inside standard DSUB25 > > connector and according to Xilinx's schematic JTAG-electronics cable length > > musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to > > JTAG signal lines and now my cable has 2m and works without reservation. I > > haven't tried to make it longer... > > > > Regards > > Daniel > > > > No real criticism Daniel but I've heard this sort of thing a lot but I reckon > the length thing is basically voodoo. I've run 3x 3 meter Centronics extension > cables + the Parallel-3 & configured CPLDs with not problem (back in the early > days of the JTAG programmer when it didn't run on Win95 I had to do this to > reach the NT box on the far side of the office). > > Now our boards have the Xilinx P-III h/w on them & it only takes 2 extension > cables. ###### From: Greg Neff Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Tue, 24 Jul 2001 13:07:56 -0400 Organization: Microsym Computers Inc. Lines: 28 Message-ID: <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> References: <3B5BDDAD.9DBA32BA@IPricot.com> NNTP-Posting-Host: hil-qbu-ptr-vty8.as.wcom.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: suaar1aa.prod.compuserve.com 995994409 23351 206.175.109.8 (24 Jul 2001 17:06:49 GMT) X-Complaints-To: newsmaster@compuserve.com NNTP-Posting-Date: 24 Jul 2001 17:06:49 GMT X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!isdnet!news.compuserve.com!news-master.compuserve.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8480 On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe wrote: We have incorporated this logic into a few of our test sets. The biggest problem that we found is that the 74HC125 input buffers are very sensitive to input noise, producing glitches on the outputs. Glitches on CLK are bad news. I guess those capacitors on the HC125 outputs are supposed to be a fix for this, but they would have been more effective on the inputs. We added pairs (series connected) of 74ACT14 Schmitt trigger inverters in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a 68pf cap to ground on the CLK input at the parallel cable connector. This circuit has worked flawlessly ever since, even with long cables. >Hi >I've built a Xilinx Parallel cable according to the schematics available >on Xilinx's site and it doesn't work. When I use the original cable >everything is fine so my board is OK. I looked at the signals with an >oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle >on the board), except that TDO stays high. Any idea? =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com ###### Message-ID: <3B5E1ACD.E5C90D93@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem References: <3B5BDDAD.9DBA32BA@IPricot.com> <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 29 Date: Wed, 25 Jul 2001 02:03:09 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 996022992 62.254.210.251 (Wed, 25 Jul 2001 02:03:12 BST) NNTP-Posting-Date: Wed, 25 Jul 2001 02:03:12 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.icl.net!dispose.news.demon.net!demon!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8354 Greg Neff wrote: > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > wrote: > > We have incorporated this logic into a few of our test sets. The > biggest problem that we found is that the 74HC125 input buffers are > very sensitive to input noise, producing glitches on the outputs. > Glitches on CLK are bad news. I guess those capacitors on the HC125 > outputs are supposed to be a fix for this, but they would have been > more effective on the inputs. > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > 68pf cap to ground on the CLK input at the parallel cable connector. > This circuit has worked flawlessly ever since, even with long cables. Interesting. Our - purely accidental - solution seems to be that we replaced the 'HC125s with LS125s. Or was it accidental ? I have a feeling that our ancient ca 1996/7 Parallel-III cable might not use the HC parts, these might have been added to program XL devices on pure 3V3 boards - I'll check. ###### From: Klaus Falser Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Wed, 25 Jul 2001 08:06:53 +0200 Organization: Durst Phototechnik AG Lines: 47 Message-ID: References: <3B5BDDAD.9DBA32BA@IPricot.com> <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> NNTP-Posting-Host: 213.192.36.18 X-Trace: serv1.iunet.it 996041183 4150 213.192.36.18 (25 Jul 2001 06:06:23 GMT) X-Complaints-To: newsmaster@iunet.it NNTP-Posting-Date: 25 Jul 2001 06:06:23 GMT X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fu-berlin.de!nntp.infostrada.it!i2unix!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8420 In article <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com>, gregeneff@yahoo.com says... > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > wrote: > > We have incorporated this logic into a few of our test sets. The > biggest problem that we found is that the 74HC125 input buffers are > very sensitive to input noise, producing glitches on the outputs. > Glitches on CLK are bad news. I guess those capacitors on the HC125 > outputs are supposed to be a fix for this, but they would have been > more effective on the inputs. > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > 68pf cap to ground on the CLK input at the parallel cable connector. > This circuit has worked flawlessly ever since, even with long cables. > > >Hi > >I've built a Xilinx Parallel cable according to the schematics available > >on Xilinx's site and it doesn't work. When I use the original cable > >everything is fine so my board is OK. I looked at the signals with an > >oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle > >on the board), except that TDO stays high. Any idea? > > > =================================== > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > Should it not be more correct to use HCT instead of HCs? Xilinx in their schematics (038057, from 10 july 1996) uses a HC125, but the signals levels on the printer plug are TTL. -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.it ###### From: Greg Neff Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Wed, 25 Jul 2001 08:49:19 -0400 Organization: Microsym Computers Inc. Lines: 21 Message-ID: References: <3B5BDDAD.9DBA32BA@IPricot.com> <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> <3B5E1ACD.E5C90D93@algor.co.uk> NNTP-Posting-Host: hil-qbu-ptr-vty8.as.wcom.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: suaar1aa.prod.compuserve.com 996065290 4776 206.175.109.8 (25 Jul 2001 12:48:10 GMT) X-Complaints-To: newsmaster@compuserve.com NNTP-Posting-Date: 25 Jul 2001 12:48:10 GMT X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news.cis.ohio-state.edu!news.compuserve.com!news-master.compuserve.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8502 On Wed, 25 Jul 2001 02:03:09 +0100, Rick Filipkiewicz wrote: (snip) > >Or was it accidental ? I have a feeling that our ancient ca 1996/7 >Parallel-III cable might not use the HC parts, these might have been added to >program XL devices on pure 3V3 boards - I'll check. > > > We always power the parallel cable (or equivalent logic) from 5V, even when programming XL devices. AFAIK, all Xilinx XL products have 5V tolerant I/O. =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com ###### Message-ID: <3B5F6E25.9BF49B6B@interlog.com> From: Iouri Besperstov Reply-To: iouri@interlog.com Organization: Eden Electronics X-Mailer: Mozilla 4.75 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem References: <3B5BDDAD.9DBA32BA@IPricot.com> <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> <3B5E1ACD.E5C90D93@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 32 Date: Wed, 25 Jul 2001 21:11:01 -0400 NNTP-Posting-Host: 154.20.70.33 X-Complaints-To: abuse@ca.inter.net X-Trace: news.total.net 996108982 154.20.70.33 (Wed, 25 Jul 2001 20:56:22 EDT) NNTP-Posting-Date: Wed, 25 Jul 2001 20:56:22 EDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-ulm.de!rz.uni-karlsruhe.de!schlund.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-peer1.tiac.net!news-feed2.tiac.net!news.total.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8514 Well everybody! Did you put jumpers on centronics connector if not do not expect you cable can work Iouri Rick Filipkiewicz wrote: > Greg Neff wrote: > > > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > > wrote: > > > > We have incorporated this logic into a few of our test sets. The > > biggest problem that we found is that the 74HC125 input buffers are > > very sensitive to input noise, producing glitches on the outputs. > > Glitches on CLK are bad news. I guess those capacitors on the HC125 > > outputs are supposed to be a fix for this, but they would have been > > more effective on the inputs. > > > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > > 68pf cap to ground on the CLK input at the parallel cable connector. > > This circuit has worked flawlessly ever since, even with long cables. > > Interesting. Our - purely accidental - solution seems to be that we replaced > the 'HC125s with LS125s. > > Or was it accidental ? I have a feeling that our ancient ca 1996/7 > Parallel-III cable might not use the HC parts, these might have been added to > program XL devices on pure 3V3 boards - I'll check. ###### From: Klaus Falser Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem Date: Thu, 26 Jul 2001 08:39:26 +0200 Organization: Durst Phototechnik AG Lines: 30 Message-ID: References: <3B5BDDAD.9DBA32BA@IPricot.com> <9n9rlto9b7opav9lvd7tqntcb0g8jg3o5n@4ax.com> <3B5E799B.4C09ED02@IPricot.com> NNTP-Posting-Host: 213.192.36.18 X-Trace: serv1.iunet.it 996129528 10261 213.192.36.18 (26 Jul 2001 06:38:48 GMT) X-Complaints-To: newsmaster@iunet.it NNTP-Posting-Date: 26 Jul 2001 06:38:48 GMT X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fu-berlin.de!nntp.infostrada.it!i2unix!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8529 In article <3B5E799B.4C09ED02@IPricot.com>, nicolas.matringe@IPricot.com says... > Klaus Falser a écrit : > > > > Should it not be more correct to use HCT instead of HCs? > > Xilinx in their schematics (038057, from 10 july 1996) > > uses a HC125, but the signals levels on the printer plug > > are TTL. > > HCT work with a power supply between 4.5 & 5.5V, HC work between 2.0 & > 6.0V (and it's recommended no to apply more than Vcc on the inputs) > This is true, but does not matter. If you have a TTL signal as coming out from the computer parallel port you need HCT since the switching levels are different. I'm using only XC9500 and XC9500XLs, so I do not know the specs of the other families very well, but IMO the only correct way is to power the cable from 5V even when programming XL devices (input are 5V tolerant) AND using HCTs. -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.it ###### From: "Speedy Zero Two" Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem + new question Date: Fri, 27 Jul 2001 21:00:28 +0100 Lines: 16 Message-ID: <9jsh08$kak$1@news6.svr.pol.co.uk> References: <3B5BDDAD.9DBA32BA@IPricot.com> <9jkeum$3ma$1@news8.svr.pol.co.uk> <3B5E797B.94BAF241@aon.at> NNTP-Posting-Host: modem-833.articuno.dialup.pol.co.uk X-Trace: news6.svr.pol.co.uk 996263752 20820 217.135.23.65 (27 Jul 2001 19:55:52 GMT) NNTP-Posting-Date: 27 Jul 2001 19:55:52 GMT X-Complaints-To: abuse@theplanet.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!t-online.de!diablo.theplanet.net!news.theplanet.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8561 "Bertram Geiger" wrote in message news:3B5E797B.94BAF241@aon.at... > It would be nice to have a little test program, to be able to check the > cable with a continous puls train without the need of having the CPLD > connected. > > greetings, bertram I would think this would be quite easy given that its just the "PC" parallel port. Dave ###### Message-ID: <3B6BBCAF.E5CDD074@sulimma.de> Date: Sat, 04 Aug 2001 11:13:19 +0200 From: Kolja Sulimma Reply-To: kolja@sulimma.de X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Homemade Xilinx parallel cable problem + new question References: <3B5BDDAD.9DBA32BA@IPricot.com> <9jkeum$3ma$1@news8.svr.pol.co.uk> <3B5E797B.94BAF241@aon.at> <9jsh08$kak$1@news6.svr.pol.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 213.23.52.215 X-Trace: 4 Aug 2001 11:13:00 +0200, 213.23.52.215 Lines: 26 X-Complaints-To: abuse@arcor-ip.de Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!151.189.0.75!newsfeed.germany.net!newsfeed.arcor-ip.de!news.arcor-ip.de!213.23.52.215 Xref: chonsp.franklin.ch comp.arch.fpga:8850 Many of the problems with the xilinx parallel download cable III are due to a bug in the Hardware Debugger software. At the end of the programming process all the signals are tristated, but are simultaneously set to a "0" value. This produces a race condition that can cause the PROG signal to go low again. Xilinx claims to have fixed this in answer record 6545. This is not true, as you can easily verify with a DSO. Whether this is a problem or not depends on the rise and fall times of your parralel port, the suply voltage on the 74HC125, the length of the cable, the capacitance on the 74HC125 outputs (see the capacitors in the schematic). We use both Xilinx original cables and home brew cables in a lab course where te students use their own computers. This way we have tested the cables at about 40 different computers and we can clearly state that both cables work on some computers and do not work with others. Adding schmitt triggers to the cable helps, but does not solve the problem. Eevntually Xilinx will have to fix the software bug.... Kolja Sulimma BTW: This is why XESS has no problems downloading their boards: They have their own download software.