From: "Noddy" Newsgroups: comp.arch.fpga Subject: Design entry Date: Thu, 12 Jul 2001 09:44:45 +0200 Organization: Rhodes University, Grahamstown, South Africa Lines: 14 Message-ID: <994923743.528258@turtle.ru.ac.za> NNTP-Posting-Host: turtle.ru.ac.za X-Trace: hippo.ru.ac.za 994923743 68727 146.231.128.8 (12 Jul 2001 07:42:23 GMT) X-Complaints-To: abuse@ru.ac.za NNTP-Posting-Date: Thu, 12 Jul 2001 07:42:23 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Cache-Post-Path: turtle.ru.ac.za!unknown@big-ears.phys.ru.ac.za X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.bme.hu!news.tele.dk!194.213.69.151!news.algonet.se!algonet!newsfeed.icl.net!netnews.com!newsfeed.nyc.globix.net!infeed.is.co.za!feeder.is.co.za!quagga.ru.ac.za!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8099 Hi, As you've guessed from recent posts, I'm very new to using FPGAs (couple of months). I've been spending my time implementing schematic design entries (using Foundation ISE). This brings me to my question? Should I rather be attempting to implement my designs in VHDL instead? My experience with VHDL is the Designer's Guide to VHDL! Any suggestions? Adrian ###### Lines: 22 X-Admin: news@aol.com From: vhdlcohen@aol.com (VhdlCohen) Newsgroups: comp.arch.fpga Date: 13 Jul 2001 18:56:37 GMT References: <994923743.528258@turtle.ru.ac.za> Organization: AOL http://www.aol.com Subject: Re: Design entry Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Message-ID: <20010713145637.19613.00003858@ng-fy1.aol.com> Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news.stealth.net!news-east.rr.com!news.rr.com!portc03.blue.aol.com!audrey04.news.aol.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8105 >As you've guessed from recent posts, I'm very new to using FPGAs (couple of >months). I've been spending my time implementing schematic design entries >(using Foundation ISE). This brings me to my question? Should I rather be >attempting to implement my designs in VHDL instead? My experience with VHDL >is the Designer's Guide to VHDL! > >Any suggestions? > Definitely use an HDL instead of schematic entry. You gain faster design entry, better documentation (provided you type it in), easier verification (one language or interface to a common lnaguage 9e.g., Specman)), and reuse. -------------------------------------------------------------------------- ----------------------------------------- Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830 http://www.vhdlcohen.com/                 vhdlcohen@aol.com   Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using   VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 -------------------------------------------------------------------------- ------------------------------------------ ###### Message-ID: <3B4F4DB0.927AA391@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 18 Date: Fri, 13 Jul 2001 13:36:16 -0600 NNTP-Posting-Host: 207.153.6.52 X-Trace: newsfeed.slurp.net 995067083 207.153.6.52 (Fri, 13 Jul 2001 18:31:23 CDT) NNTP-Posting-Date: Fri, 13 Jul 2001 18:31:23 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8098 John_H wrote: > > HDL, not schematics, yes! yes! > Verilog and VHDL are both appropriate to the task. > It's a little like the age old question (probably still valid in your corner of > this world: "Coke or Pepsi?" > If you have tools for and/or experienced designers that use one HDL, it's a > great way to go. I use schematics and drink "No-Name Cola". One advantage schematics may be ( with a good macro library ) for the large amount of small TTL projects that are around. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics. ###### Message-ID: <3B4F5DDB.A0671BB8@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 30 Date: Fri, 13 Jul 2001 20:45:15 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@tek.com X-Trace: news-west.eli.net 995057115 192.65.17.17 (Fri, 13 Jul 2001 14:45:15 MDT) NNTP-Posting-Date: Fri, 13 Jul 2001 14:45:15 MDT Organization: Tektronix NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!telocity-west!TELOCITY!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8112 HDL, not schematics, yes! yes! Verilog and VHDL are both appropriate to the task. It's a little like the age old question (probably still valid in your corner of this world: "Coke or Pepsi?" If you have tools for and/or experienced designers that use one HDL, it's a great way to go. You'll also find a new newsgroup to visit - comp.lang.verilog or comp.lang.vhdl. If you get in the habit of using HDL early on, you'll be in great shape for some interesting design challenges. - John Noddy wrote: > Hi, > > As you've guessed from recent posts, I'm very new to using FPGAs (couple of > months). I've been spending my time implementing schematic design entries > (using Foundation ISE). This brings me to my question? Should I rather be > attempting to implement my designs in VHDL instead? My experience with VHDL > is the Designer's Guide to VHDL! > > Any suggestions? > > Adrian ###### From: Magnus Homann Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: 13 Jul 2001 23:00:23 +0200 Organization: Chalmers univ. of Technology Lines: 14 Message-ID: References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> NNTP-Posting-Host: mis.dtek.chalmers.se X-Trace: nyheter.chalmers.se 995058023 29572 129.16.30.55 (13 Jul 2001 21:00:23 GMT) X-Complaints-To: abuse@chalmers.se NNTP-Posting-Date: 13 Jul 2001 21:00:23 GMT X-Newsreader: Gnus v5.7/Emacs 20.7 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!news.tele.dk!194.213.69.151!news.algonet.se!newsfeed1.telenordia.se!algonet!newsfeed.sunet.se!news01.sunet.se!news.chalmers.se!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8107 John_H writes: > Verilog and VHDL are both appropriate to the task. > It's a little like the age old question (probably still valid in > your corner of this world: "Coke or Pepsi?" Actually, it's more like "Coke or a beer?". One is common in the US, the other you can have more fun with... Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.se ###### Message-ID: <3B4F662B.DF9F18F7@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 Date: Fri, 13 Jul 2001 21:20:02 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 995059202 24.13.238.93 (Fri, 13 Jul 2001 14:20:02 PDT) NNTP-Posting-Date: Fri, 13 Jul 2001 14:20:02 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8097 My feeling on this is HDLs give you more flexibility when it comes to parameterizing your designs, and much better testbenches. Also, an HDL doesn't require a proprietary view to browse the design (although it may need a specific version of the synthesizer to generate exactly what you intended). Other than these points, I find that properly done schematics or HDL are appropriate. For either, proper use of hierarchy plays a much bigger role in reusability, readability, documentation, and troubleshooting than does the choice of a design entry tool. I actually like to discourage newbies to FPGAs and/or digital design using HDLs, as the abstraction tends to hide poor design practice, as well as the obvious architectural tailoring you can easily do in the design if you are close to the underlying chip architecture. HDLs make it too easy to design something that is very difficult/expensive in hardware and many times the designer doesn't even realize it. VHDL is a a powerful tool, but it does not make a lousy design magically good and since it tends to hide the details it may not be obvious the design is lousy. Magnus Homann wrote: > John_H ?johnhandwork@mail.com? writes: > > ? Verilog and VHDL are both appropriate to the task. > > ? It's a little like the age old question (probably still valid in > ? your corner of this world: "Coke or Pepsi?" > > Actually, it's more like "Coke or a beer?". One is common in the US, the other > you can have more fun with... > > Homann > -- > Magnus Homann, M.Sc. CS ? E > d0asta@dtek.chalmers.se -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com ###### Newsgroups: comp.arch.fpga From: arast@inficom.com (Alex Rast) Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> X-Newsreader: News Xpress 2.01 Lines: 120 Message-ID: Date: Fri, 13 Jul 2001 23:45:32 GMT NNTP-Posting-Host: 216.160.85.42 X-Trace: news.uswest.net 995068297 216.160.85.42 (Fri, 13 Jul 2001 18:51:37 CDT) NNTP-Posting-Date: Fri, 13 Jul 2001 18:51:37 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!feed.news.qwest.net!news.uswest.net.POSTED!alex Xref: chonsp.franklin.ch comp.arch.fpga:8106 In article <994923743.528258@turtle.ru.ac.za>, "Noddy" wrote: >Hi, > >As you've guessed from recent posts, I'm very new to using FPGAs (couple of >months). I've been spending my time implementing schematic design entries >(using Foundation ISE). This brings me to my question? Should I rather be >attempting to implement my designs in VHDL instead? My experience with VHDL >is the Designer's Guide to VHDL! > Most people, I'm sure, are going to tell you to use HDL's. I'm going to register a different opinion and say that to make a blanket statement, that such-and-such a tool is the way to go, limits your options and may not be the best way to go. I think it's a case of a different tool for a different type of job. It really depends what it is that you're trying to do that will determine what's the best tool. Since you're using Xilinx (as the Foundation software indicates), I'll go over the plusses and minuses of each. You have 4 basic options: HDL, state machine, schematic, or FPGA editor. These roughly correspond to decreasing levels of abstraction. HDL's excel in complex but well-defined designs, where you know exactly what it is that your logic must do, but what it needs to do is complex and involved. If you think in an "algorithmic" or software-like way, in other words, you view your logic as "code" that you need to execute, HDL's will be the tool you'll be most comfortable with. They let you describe your logic in a source-code-like manner, and they'll let you do some very involved stuff. The tools for HDL have extraordinary sophistication, with plenty of verification and simulation options, lots of different flavors of synthesis entry, and usually a great many options in the program itself. HDL's are also, oddly, very good for really quick, simple logic functions that you don't feel like taking the time to figure out how the hardware would have to be for them. The downside of HDL's is that the abstraction isolates you very much from the details of what's going on in the hardware. Typically you don't have ultimate control over how the software will actually implement your design on the chip. Furthermore, although the range of functions you can implement is amazing, abstracting the functionality still means that at a certain level you limit your design to the kinds of logic functions and blocks that the designers of the software envisioned. In other words, HDL's aren't your best bet if you're looking to tweak the last inch of performance, or utilization from your FPGA, or if you're doing something so bizarre that it falls outside the boundaries of what the software writers assumed you might be doing. Finally, there's the risk, with such a high degree of isolation, that you may try to implement something either too complex or at least very expensive to implement on the hardware. This could either hamper your design or be an outright barrier to success. So HDL's are things you should use with care, mostly to design relatively mature logic functions. State machine entry works well when your design is simple and has a linear flow. If you think in a sequential way, seeing your logic as a series of states that the system steps through, the FSM entry method will seem logical to you. You could perhaps get quite complex, depending on how big of a state machine you care to visualize. It's great for simple controllers, especially ones with feedback where a state-machine description is fitting and natural. Even relatively complex, closed-loop control systems are good with this kind of system. Nevertheless, it really comes into its own with semi-simple functions, ones that may be more clear with a visual representation, and where the source-code representation of an HDL might make it more opaque what's actually going on. The tools, OTOH, aren't very sophisticated or thought through. Third-party support is rare at best, and you'll probably end up using Xilinx' simulation and verification tools. Furthermore, at some point the design may become very difficult to follow, when you have hundreds of states, and since this method still isolates you from the underlying logic, there's no benefit to displaying a complex design in this way. In many respects, FSM design opens up the same weaknesses as HDLs, although admittedly it's pretty clear if you've got a state machine description that you're not doing anything bleeding-edge, so a great deal of the penalty of abstraction is a nonissue. Nonetheless, state machine synthesis is really for a narrow application range, where you're doing something simple, well-defined, and probably control-system oriented. Schematic entry gives you far more insight into what's happening at a gate-level. If you're a "hardware" person, this will be a natural way to design. You can actually see what the gate implementation is, and this will give you a better immediate feel for timing issues, data paths, and simply what's actually going on in your design. You can design very, very complex logic if you want, and it's easier to optimize the design for the specific device you have. It eliminates a lot of the associated abstraction problems of HDL's, simply because everything happens at a more primitive level. Also, you can instantly see how complex a function is *actually* going to turn out to be, so you can either eliminate or redesign the logic if it turns out to be too expensive. In a sense, you have more flexibility in what you can design, because the tool lets you create logic much more with a specific view to the hardware capabilities of the chip. It may help also to de-mystify what's happening at a hardware level. The big downside of schematic entry is that it's very difficult to modify the design, still harder to port it to a different device. It basically locks you into the device and design you envision at the present. You should also expect a lot of debugging because it doesn't isolate you from implementation-level errors, i.e. your logic may be right, but how you implemented it in the schematic may be faulty, something you can avoid with HDL's. Worse, the verification and simulation capabilities are more limited, and third-party support is essentially nonexistent. Xilinx' tool furthermore has a whole set of frustrating, nonsensical limitations. You should therefore be very confident with your schematic capture capabilities before tackling a design this way. It's best for the more bleeding edge, oddball designs where you aren't overly concerned with design cycle time, and where you don't expect to be changing devices any time soon. Finally, FPGA editor gives you ultimate control, giving you direct access to the physical layout and configuration of the device proper. Obviously, this means you can program any configuration the device is capable of implementing, no matter how bizarre or complex. You can see directly *exactly* what's going on, tweak your fitting down to the last detail, specify precisely what function blocks, connections, etc. implement which piece, etc. The negatives are equally clear-cut, namely, you have *NO*: simulation, verification, portability, error-checking, or third-party support. Experts only need apply, and you'd better know hardware inside and out. Debugging will take a long time, and unless you're really careful, you may smoke a component or 2. So this is a tool to use only if you're an expert and have some freakish, ultra-high-end design where you can't tolerate any sort of compromise whatsoever. Alex Rast arast@qwest.net arast@inficom.com ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: Design entry Message-ID: References: <994923743.528258@turtle.ru.ac.za> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 25 X-Complaints-To: abuse@usenetserver.com X-Abuse-Info: Please be sure to forward a copy of ALL headers X-Abuse-Info: Otherwise we will be unable to process your complaint properly. NNTP-Posting-Date: Fri, 13 Jul 2001 21:22:08 EDT Organization: WebUseNet Corp. - "ReInventing The UseNet" Date: Fri, 13 Jul 2001 18:26:09 -0700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.icl.net!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!in.nntp.be!easynews!e420r-sjo4.usenetserver.com!newsfeed.usenetserver.com!e420r-atl2.usenetserver.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8092 arast@inficom.com (Alex Rast) wrote: >... >HDL's excel in complex but well-defined designs, where you know exactly what >... >The downside of HDL's is that the abstraction isolates you very much from the >details of what's going on in the hardware. Typically you don't have ultimate >... >Schematic entry gives you far more insight into what's happening at a >gate-level. If you're a "hardware" person, this will be a natural way to I think this distinction is completely arbitrary. Actually the ONLY difference between HDL and schematic entry is how they are visually presented. You can get an HDL text file which is completely identical to a schematic and that is how you link schematic entry to P&R anyway. You get an EDIF file from your schematic entry tool. Viewlogic's Viewdraw can even generate Verilog from your schematics. You can instantiate gates in Verilog and put constraints etc. which is what the schematic does. IOW, if you want to do gate-level structural entry HDL lets you do it unlike schematic which forces you to only that type of entry. In HDL you have a lot more freedom. You can design complex state machines for control blocks easily and you can be as detailed and low level as you need for datapath blocks. Muzaffer ###### Message-ID: <3B5053B0.8E3FF4D2@ecubics.com> Date: Sat, 14 Jul 2001 08:14:08 -0600 From: emanuel stiebler X-Mailer: Mozilla 4.77 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 16 NNTP-Posting-Host: 63.90.186.226 X-Trace: reader0.news.uu.net 995119520 17910 63.90.186.226 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed1.cidera.com!news-reader.ntrnet.net!uunet!ash.uu.net!spool0.news.uu.net!reader0.news.uu.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8095 Noddy wrote: > > This brings me to my question? Should I rather be > attempting to implement my designs in VHDL instead? Mix it ! A top level schematic, the units below in VHDL, Verilog, etc.. It's amazing, already magic how easy it is to explain what you're doing to somebody else, when you can see all functional units, data flow on one sheet. And, sometimes you see your own design more clearly ;-) when you like to go to HDL only, just replace one sheet to a text page. just my .02 have fun ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: 14 Jul 2001 17:19:57 +0200 Organization: My own Private Self Lines: 58 Message-ID: <6ubsmnbkrm.fsf@chonsp.franklin.ch> References: <994923743.528258@turtle.ru.ac.za> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 995124000 395 10.0.3.2 (14 Jul 2001 15:20:00 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 14 Jul 2001 15:20:00 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:8113 arast@inficom.com (Alex Rast) writes: > In article <994923743.528258@turtle.ru.ac.za>, "Noddy" wrote: > >Hi, > > > >(using Foundation ISE). This brings me to my question? Should I rather be > >attempting to implement my designs in VHDL instead? My experience with VHDL > >is the Designer's Guide to VHDL! > > Most people, I'm sure, are going to tell you to use HDL's. > > You have 4 basic options: HDL, state machine, schematic, or FPGA editor. These > roughly correspond to decreasing levels of abstraction. May I add a 5th option: JBits. > HDL's > They let you describe your logic in > a source-code-like manner, > > The downside of HDL's is that the abstraction isolates you very much > > > Finally, FPGA editor gives you ultimate control > > The negatives are equally clear-cut, namely, you have *NO*: simulation, > verification, portability, error-checking, or third-party support. Experts > only need apply, and you'd better know hardware inside and out. Debugging will > take a long time, and unless you're really careful, you may smoke a component > or 2. So this is a tool to use only if you're an expert and have some > freakish, ultra-high-end design where you can't tolerate any sort of > compromise whatsoever. JBits also gives you FPGA Editor level control, but using an HDL like source code with all the advantages of replication structures (good for data paths). I managed to get it to work despite being a beginner (previously only 74xx stuff) by simply reading *thoroughly* the Virtex data sheet and the JBits docs, plus a few mails to Xilinx JBits group. The JRoute component allows routing without danger of accidently killing chips. Also runs on any machine with Java support. I develop on Linux, no NT or Solaris. Negatives are: simulation is limited to DeviceSimulator, essentially step the clock through your design, whatching what it does. No protability (only Virtex, and Spartan-II of sizes that also exist in Virtex). And code is fairly verbose (you set everything), and you need to do 100% hand placing (routing is automated). So it is fairly time intensive. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: Mike Treseler Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Sat, 14 Jul 2001 11:45:21 -0700 Organization: Fluke Networks Lines: 21 Message-ID: <3B509341.EC90F0AD@flukenetworks.com> References: <994923743.528258@turtle.ru.ac.za> NNTP-Posting-Host: slick.tc.fluke.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.16-SMP i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!jfk3-feed1.news.digex.net!sfo2-feed1.news.digex.net!intermedia!newsfeed2.sea.pnap.net!newsfeed1.sea.pnap.net!newsfeed.pnap.net!fluke!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8116 Noddy wrote: > > Hi, > > As you've guessed from recent posts, I'm very new to using FPGAs (couple of > months). I've been spending my time implementing schematic design entries > (using Foundation ISE). This brings me to my question? Should I rather be > attempting to implement my designs in VHDL instead? My experience with VHDL > is the Designer's Guide to VHDL! If you are getting the job done, don't worry about. My bias is now towards HDLs, but I also started with schematics, and that works fine too. The fact that you asked the question suggests that you have some interest in HDLs. If this is true, you might want to start by writing an HDL testbench for an existing schematic design. --Mike Treseler ###### Message-ID: <3B51E407.80E2FE21@mail.com> From: John_H X-Mailer: Mozilla 4.75 [en]C-CCK-MCD (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> <3B4F4DB0.927AA391@jetnet.ab.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 8 Date: Sun, 15 Jul 2001 18:42:16 GMT NNTP-Posting-Host: 192.65.17.17 X-Complaints-To: postmaster@tek.com X-Trace: news-west.eli.net 995222536 192.65.17.17 (Sun, 15 Jul 2001 12:42:16 MDT) NNTP-Posting-Date: Sun, 15 Jul 2001 12:42:16 MDT Organization: Tektronix NewsReader Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!telocity-west!TELOCITY!news-west.eli.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8140 Say, can we still buy TTL? DTL? RTL? Ben Franchuk wrote: > One advantage schematics may be ( with a good > macro library ) for the large amount of small TTL projects > that are around. ###### Message-ID: <3B51FB90.BFE36FA9@jetnet.ab.ca> From: Ben Franchuk X-Mailer: Mozilla 4.77 [en] (X11; U; Linux 2.2.18 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> <3B4F4DB0.927AA391@jetnet.ab.ca> <3B51E407.80E2FE21@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 Date: Sun, 15 Jul 2001 14:22:40 -0600 NNTP-Posting-Host: 207.153.6.42 X-Trace: newsfeed.slurp.net 995229186 207.153.6.42 (Sun, 15 Jul 2001 15:33:06 CDT) NNTP-Posting-Date: Sun, 15 Jul 2001 15:33:06 CDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.slurp.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8136 John_H wrote: > > Say, can we still buy TTL? DTL? RTL? > The DTL & RTL chips have gone the way of the Dodo. Real TTL chips can still be found mostly as surplus old stock. The TTL family of devices have moved to high speed cmos. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics. ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Sun, 15 Jul 2001 20:47:34 -0400 Organization: http://extra.newsguy.com Lines: 12 Message-ID: References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> <3B4F4DB0.927AA391@jetnet.ab.ca> <3B51E407.80E2FE21@mail.com> NNTP-Posting-Host: p-307.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.30 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!wn3feed!worldnet.att.net!209.155.233.17!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews4 Xref: chonsp.franklin.ch comp.arch.fpga:8189 In article <3B51E407.80E2FE21@mail.com>, johnhandwork@mail.com says... > Say, can we still buy TTL? DTL? RTL? Sure. Iv'e got some stuff with '72-'74 date codes on 'em... Wanna buy? ;-) ...other than that, it's the CMOS stuff and much of that is hard to come by. ---- Keith ###### Message-ID: <3B52EAF3.8A4D45DF@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Design entry References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> <3B4F4DB0.927AA391@jetnet.ab.ca> <3B51E407.80E2FE21@mail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 17 Date: Mon, 16 Jul 2001 14:24:03 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 995289845 62.254.210.251 (Mon, 16 Jul 2001 14:24:05 BST) NNTP-Posting-Date: Mon, 16 Jul 2001 14:24:05 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!newsfeed.germany.net!newsfeed.icl.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8154 "Keith R. Williams" wrote: > In article <3B51E407.80E2FE21@mail.com>, johnhandwork@mail.com > says... > > Say, can we still buy TTL? DTL? RTL? > > Sure. Iv'e got some stuff with '72-'74 date codes on 'em... > Wanna buy? ;-) > Maybe you should consider embedding them in perspex (plexiglass) and selling them as charms to new age h/w designers to ward off the evil metastability demon. I'd buy one to ward off s/w engineers who think a critical path is the route to the nearest pub (bar). ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Mon, 16 Jul 2001 11:53:08 -0400 Organization: http://extra.newsguy.com Lines: 26 Message-ID: References: <994923743.528258@turtle.ru.ac.za> <3B5053B0.8E3FF4D2@ecubics.com> NNTP-Posting-Host: p-095.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newscore.univie.ac.at!64.245.43.11.MISMATCH!dfw3-feed1.news.digex.net!jfk3-feed1.news.digex.net!intermedia!news.maxwell.syr.edu!newsfeed.stanford.edu!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews3 Xref: chonsp.franklin.ch comp.arch.fpga:8190 In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > Noddy wrote: > > > > This brings me to my question? Should I rather be > > attempting to implement my designs in VHDL instead? > > Mix it ! > A top level schematic, the units below in VHDL, Verilog, etc.. > It's amazing, already magic how easy it is to explain what you're doing > to somebody else, when you can see all functional units, data flow on > one sheet. > And, sometimes you see your own design more clearly ;-) That certainly would be an advantage. However, I understand that synthesis in a mixed environment doesn't work well. The redundancy isn't squished out beyond the black boxes. > when you like to go to HDL only, just replace one sheet to a text page. If I could do both schematics and (V)HDL with the same toolset with the flattening occurring before the "real" synthesis this would be nice. This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs wile remaining productive. Listening Synplicity? ;-) ---- Keith ###### From: Ken McElvain Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Mon, 16 Jul 2001 11:20:11 -0700 Organization: The ISP formerly known as Best Lines: 41 Message-ID: <3B53305B.68C195A5@synplicity.com> References: <994923743.528258@turtle.ru.ac.za> <3B5053B0.8E3FF4D2@ecubics.com> NNTP-Posting-Host: synvpn.synplicity.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: nntp1.ba.best.com 995307119 62769 209.157.48.1 (16 Jul 2001 18:11:59 GMT) X-Complaints-To: abuse@best.com NNTP-Posting-Date: Mon, 16 Jul 2001 18:11:59 +0000 (UTC) X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub.sdsu.edu!news1.best.com!nntp1.ba.best.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8163 There are several schematic entry systems that can write VHDL or Verilog netlists. Just include that generated HDL with the HDL for the subblocks and I think you have what you asked for. Look at Aldec for an example. In Europe, there is a tool called EASE from Translogic that generates VHDL. I think these tools also have state machine tools as well. "Keith R. Williams" wrote: > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > Noddy wrote: > > > > > > This brings me to my question? Should I rather be > > > attempting to implement my designs in VHDL instead? > > > > Mix it ! > > A top level schematic, the units below in VHDL, Verilog, etc.. > > It's amazing, already magic how easy it is to explain what you're doing > > to somebody else, when you can see all functional units, data flow on > > one sheet. > > And, sometimes you see your own design more clearly ;-) > > That certainly would be an advantage. However, I understand that > synthesis in a mixed environment doesn't work well. The redundancy > isn't squished out beyond the black boxes. > > > when you like to go to HDL only, just replace one sheet to a text page. > > If I could do both schematics and (V)HDL with the same toolset with the > flattening occurring before the "real" synthesis this would be nice. > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > wile remaining productive. Listening Synplicity? ;-) > > ---- > Keith -- Ken McElvain, CTO Synplicity Inc. (408)215-6060 ###### From: Keith R. Williams Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Mon, 16 Jul 2001 15:17:00 -0400 Organization: http://extra.newsguy.com Lines: 54 Message-ID: References: <994923743.528258@turtle.ru.ac.za> <3B5053B0.8E3FF4D2@ecubics.com> <3B53305B.68C195A5@synplicity.com> NNTP-Posting-Host: p-497.newsdawg.com X-Newsreader: MicroPlanet Gravity v2.50 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!t-online.de!news-lei1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!enews4 Xref: chonsp.franklin.ch comp.arch.fpga:8195 In article <3B53305B.68C195A5@synplicity.com>, ken@synplicity.com says... > There are several schematic entry systems that can write VHDL or > Verilog netlists. Just include that generated HDL with the > HDL for the subblocks and I think you have what you asked for. > > Look at Aldec for an example. In Europe, there is a tool called > EASE from Translogic that generates VHDL. I think these tools > also have state machine tools as well. I don't know if this is the same thing. Synplicity, for instance, does a lot of work optimizing the logic for the target architecture. It obviously can't see what it didn't generate so there may not be any optimizations across black boxes (even if two block boxes are adjacent in real life). In fact I don't think there are any optimizations attempted across black boxes. Anyway, I'm nervous adding more tools to the chain. If the tools did schematic in the hierarchy, fine. I agree that schematic is more "natural" for the high-level design and documentation. ---- Keith > "Keith R. Williams" wrote: > > > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > > Noddy wrote: > > > > > > > > This brings me to my question? Should I rather be > > > > attempting to implement my designs in VHDL instead? > > > > > > Mix it ! > > > A top level schematic, the units below in VHDL, Verilog, etc.. > > > It's amazing, already magic how easy it is to explain what you're doing > > > to somebody else, when you can see all functional units, data flow on > > > one sheet. > > > And, sometimes you see your own design more clearly ;-) > > > > That certainly would be an advantage. However, I understand that > > synthesis in a mixed environment doesn't work well. The redundancy > > isn't squished out beyond the black boxes. > > > > > when you like to go to HDL only, just replace one sheet to a text page. > > > > If I could do both schematics and (V)HDL with the same toolset with the > > flattening occurring before the "real" synthesis this would be nice. > > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > > wile remaining productive. Listening Synplicity? ;-) > > > > ---- > > Keith > > ###### From: husby_d@yahoo.com (Don Husby) Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: 16 Jul 2001 15:20:28 -0700 Organization: http://groups.google.com/ Lines: 16 Message-ID: <35802095.0107161420.3a5db07e@posting.google.com> References: <994923743.528258@turtle.ru.ac.za> <3B4F5DDB.A0671BB8@mail.com> NNTP-Posting-Host: 198.107.63.227 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 995322028 29250 127.0.0.1 (16 Jul 2001 22:20:28 GMT) X-Complaints-To: groups-support@google.com NNTP-Posting-Date: 16 Jul 2001 22:20:28 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!postnews1.google.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8186 John_H > HDL, not schematics, yes! yes! > Verilog and VHDL are both appropriate to the task. > It's a little like the age old question (probably still valid in > your corner of this world: "Coke or Pepsi?" At the risk of starting a long religious debate, my experience has been that VHDL is better suited for high speed FPGA design. To push an FPGA to the edge, you pretty much need attributes to control mapping and placement, and Verilog doesn't (yet) have a standard way to implement attributes. Also, VHDL's "generate" construct is almost necessary for attaching attributes when using wide busses. I'm not a big fan of VHDL either. I keep hoping that some day someone will invent a *good* HDL. ###### From: Ken McElvain Newsgroups: comp.arch.fpga Subject: Re: Design entry Date: Mon, 16 Jul 2001 18:24:36 -0700 Organization: The ISP formerly known as Best Lines: 63 Message-ID: <3B5393D4.4C2F542@synplicity.com> References: <994923743.528258@turtle.ru.ac.za> <3B5053B0.8E3FF4D2@ecubics.com> <3B53305B.68C195A5@synplicity.com> NNTP-Posting-Host: synvpn.synplicity.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: nntp1.ba.best.com 995332581 64100 209.157.48.1 (17 Jul 2001 01:16:21 GMT) X-Complaints-To: abuse@best.com NNTP-Posting-Date: Tue, 17 Jul 2001 01:16:21 +0000 (UTC) X-Mailer: Mozilla 4.51 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!feed.textport.net!news1.best.com!nntp1.ba.best.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:8162 "Keith R. Williams" wrote: > > In article <3B53305B.68C195A5@synplicity.com>, ken@synplicity.com > says... > > There are several schematic entry systems that can write VHDL or > > Verilog netlists. Just include that generated HDL with the > > HDL for the subblocks and I think you have what you asked for. > > > > Look at Aldec for an example. In Europe, there is a tool called > > EASE from Translogic that generates VHDL. I think these tools > > also have state machine tools as well. > > I don't know if this is the same thing. Synplicity, for instance, does > a lot of work optimizing the logic for the target architecture. It > obviously can't see what it didn't generate so there may not be any > optimizations across black boxes (even if two block boxes are adjacent > in real life). In fact I don't think there are any optimizations > attempted across black boxes. > > Anyway, I'm nervous adding more tools to the chain. If the tools did > schematic in the hierarchy, fine. I agree that schematic is more > "natural" for the high-level design and documentation. Synplify would see the generated(from the schematic) top level VHDL/verilog because you would include it in the Synplify project. The lower level VHDL/Verilog files would then be optimized together. You don't need to make the submodules black boxes. > > ---- > Keith > > > "Keith R. Williams" wrote: > > > > > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > > > Noddy wrote: > > > > > > > > > > This brings me to my question? Should I rather be > > > > > attempting to implement my designs in VHDL instead? > > > > > > > > Mix it ! > > > > A top level schematic, the units below in VHDL, Verilog, etc.. > > > > It's amazing, already magic how easy it is to explain what you're doing > > > > to somebody else, when you can see all functional units, data flow on > > > > one sheet. > > > > And, sometimes you see your own design more clearly ;-) > > > > > > That certainly would be an advantage. However, I understand that > > > synthesis in a mixed environment doesn't work well. The redundancy > > > isn't squished out beyond the black boxes. > > > > > > > when you like to go to HDL only, just replace one sheet to a text page. > > > > > > If I could do both schematics and (V)HDL with the same toolset with the > > > flattening occurring before the "real" synthesis this would be nice. > > > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > > > wile remaining productive. Listening Synplicity? ;-) > > > > > > ---- > > > Keith > > > >