Message-ID: <3B254B35.D80BFD4F@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Doing Ethernet in a Virtex ? Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 8 Date: Mon, 11 Jun 2001 23:50:29 +0100 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 992299831 62.254.210.251 (Mon, 11 Jun 2001 23:50:31 BST) NNTP-Posting-Date: Mon, 11 Jun 2001 23:50:31 BST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!newsfeed00.sul.t-online.de!t-online.de!colt.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7178 I'm trying to work out whether its possible to do Ethernet in an FPGA. Not just the MAC layer and then out on MII to an external PHY but connect directly to the TP transformer. Does anybody know if any of the Virtex2 differential IO standards would work either directly or with a minimal amount of level shifting ? ###### From: "Jeffrey Vallier" Newsgroups: comp.arch.fpga References: <3B254B35.D80BFD4F@algor.co.uk> Subject: Re: Doing Ethernet in a Virtex ? Lines: 32 Organization: Gibson Guitar Corp. X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MIMEOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Message-ID: <%8dV6.619$Hd1.134612@news.pacbell.net> Date: Mon, 11 Jun 2001 17:11:35 -0700 NNTP-Posting-Host: 63.202.30.226 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 992304827 63.202.30.226 (Mon, 11 Jun 2001 17:13:47 PDT) NNTP-Posting-Date: Mon, 11 Jun 2001 17:13:47 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!out.nntp.be!propagator-dallas!news-in-dallas.newsfeeds.com!cyclone-sf.pbi.net!206.13.28.144!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7197 "Rick Filipkiewicz" wrote in message news:3B254B35.D80BFD4F@algor.co.uk... > > I'm trying to work out whether its possible to do Ethernet in an FPGA. > Not just the MAC layer and then out on MII to an external PHY but > connect directly to the TP transformer. Does anybody know if any of the > Virtex2 differential IO standards would work either directly or with a > minimal amount of level shifting ? > Nope. We researched this pretty throughly and from our perspective there's too much mixed signal crap involved to make it worthwhile. Good idea though :) Don't despair, 'cause I have heard rumors of Phy-in-an-FPGA floating around. I think this is a solution that many designers wish for--we just have to wait for a "big" customer to want it enough to cough up the development costs and then have it filter down the product channels as a standard part for the rest of us. good luck, Jeff -- *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 *********************************************** ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: Doing Ethernet in a Virtex ? Organization: dspia inc. http://www.dspia.com Message-ID: References: <3B254B35.D80BFD4F@algor.co.uk> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 Date: Tue, 12 Jun 2001 15:48:48 GMT NNTP-Posting-Host: 24.11.138.186 X-Complaints-To: abuse@home.net X-Trace: news1.rdc1.sfba.home.com 992360928 24.11.138.186 (Tue, 12 Jun 2001 08:48:48 PDT) NNTP-Posting-Date: Tue, 12 Jun 2001 08:48:48 PDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.rdc1.sfba.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7223 On Mon, 11 Jun 2001 23:50:29 +0100, Rick Filipkiewicz wrote: > >I'm trying to work out whether its possible to do Ethernet in an FPGA. >Not just the MAC layer and then out on MII to an external PHY but >connect directly to the TP transformer. Does anybody know if any of the >Virtex2 differential IO standards would work either directly or with a >minimal amount of level shifting ? > do you mean 10bt, 100btx or 1000bt (or something else :-) ? 10bt is non-trivial but doable in an FPGA (have done it already). You need some external components to drive and a comparator to receive. It is difficult to be fully 802.3 compliant without a full AFE though. 100btx is very difficult even without the AFE issue (you need a 6 bit 250 (or 125) MHz ADC for a DSP implementation). It is possible with a large and fast virtex-2 if you can put the AFE together (ADC+VGA on the input. MLT3 driver on the output) Muzaffer FPGA DSP Consulting http://www.dspia.com ###### Message-ID: <3B263F1F.19E229E2@sulimma.de> Date: Tue, 12 Jun 2001 18:11:11 +0200 From: Kolja Sulimma Reply-To: kolja@sulimma.de X-Mailer: Mozilla 4.7 [en] (Win98; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Doing Ethernet in a Virtex ? References: <3B254B35.D80BFD4F@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 213.23.52.88 X-Trace: 12 Jun 2001 18:11:12 +0200, 213.23.52.88 Lines: 19 X-Complaints-To: abuse@arcor-ip.de Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!news-fra1.dfn.de!newsfeed.arcor-ip.de!news.arcor-ip.de!213.23.52.88 Xref: chonsp.franklin.ch comp.arch.fpga:7168 > 10bt is > non-trivial but doable in an FPGA (have done it already). You need > some external components to drive and a comparator to receive. Interesting. Do you have a schematic for a driver circuit? > It is > difficult to be fully 802.3 compliant without a full AFE though. What is AFE? > 100btx is very difficult even without the AFE issue (you need a 6 bit > 250 (or 125) MHz ADC for a DSP implementation). It is possible with a > large and fast virtex-2 if you can put the AFE together (ADC+VGA on > the input. MLT3 driver on the output) Kolja Sulimma