From: "Alfredo Benso" Newsgroups: comp.arch.fpga Subject: Xilinx Configuration Bitstream Date: Mon, 4 Jun 2001 17:59:49 +0200 Organization: Unknown Lines: 32 Message-ID: <9fgaom$opj$1@menelao.polito.it> NNTP-Posting-Host: galaxy.polito.it X-Trace: menelao.polito.it 991669846 25395 130.192.16.245 (4 Jun 2001 15:50:46 GMT) X-Complaints-To: usenet@news.polito.it NNTP-Posting-Date: 4 Jun 2001 15:50:46 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsmi-eu.news.garr.it!newsmi-us.news.garr.it!newsbo.news.garr.it!NewsITBone-GARR!newsfeed.cineca.it!menelao.polito.it!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6892 Hi everybody, I am a researcher at Politecnico di Torino in Italy. I am looking for information about the format of the Xilinx configuration bit stream. Is the format public? Is there some document or file available explaining how to generate a stream of configuration bits for a Xiling FPGA? Anybody can help? Thanks Alfredo ----ooo---ooo---ooo---ooo---- BENSO Alfredo, PhD Politecnico di Torino Dip. Automatica e Informatica C.so Duca degli Abruzzi 24 Torino - Italy Phone: +39-011-564.7080 Fax: +39-011-564.7099 email: alfredo.benso@polito.it ----------ooo---ooo------------- ###### From: Vladislav Vasilenko Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Tue, 05 Jun 2001 11:06:38 +0300 Organization: NTUU "KPI" Lines: 38 Message-ID: <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> References: <9fgaom$opj$1@menelao.polito.it> NNTP-Posting-Host: pm000-2.comsys.ntu-kpi.kiev.ua Mime-Version: 1.0 Content-Type: text/plain; charset=koi8-r Content-Transfer-Encoding: 7bit X-Trace: igloo.uran.net.ua 991728538 77414 10.18.48.13 (5 Jun 2001 08:08:57 GMT) X-Complaints-To: newsmaster@news.ntu-kpi.kiev.ua NNTP-Posting-Date: 5 Jun 2001 08:08:57 GMT X-Mailer: Mozilla 4.72 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!sjc-peer.news.verio.net!iad-feed.news.verio.net!news.verio.net!carrier.kiev.ua!news.uran.net.ua!news.ntu-kpi.kiev.ua!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6950 Hi Alfredo, "..Xilinx keeps the interpretation of the bitstream a closely guarded secret.." It's quotation from Xilinx "The Programmable Logic Data Book ". Best regards, Vlad. Alfredo Benso wrote: > > Hi everybody, > I am a researcher at Politecnico di Torino in Italy. > I am looking for information about the format of the Xilinx configuration > bit stream. Is the format public? Is there some document or file available > explaining how to generate a stream of configuration bits for a Xiling FPGA? > > Anybody can help? > > Thanks Alfredo > > ----ooo---ooo---ooo---ooo---- > BENSO Alfredo, PhD > > Politecnico di Torino > > Dip. Automatica e Informatica > > C.so Duca degli Abruzzi 24 > > Torino - Italy > > Phone: +39-011-564.7080 > > Fax: +39-011-564.7099 > > email: alfredo.benso@polito.it > > ----------ooo---ooo------------- ###### From: "luigi funes" Newsgroups: comp.arch.fpga References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> Subject: Re: Xilinx Configuration Bitstream Lines: 21 X-Newsreader: Microsoft Outlook Express 4.72.3110.5 X-MIMEOLE: Produced By Microsoft MimeOLE V4.72.3110.3 Message-ID: Date: Tue, 05 Jun 2001 09:12:52 GMT NNTP-Posting-Host: 151.33.129.80 X-Complaints-To: abuse@iol.it X-Trace: news.infostrada.it 991732372 151.33.129.80 (Tue, 05 Jun 2001 11:12:52 MET DST) NNTP-Posting-Date: Tue, 05 Jun 2001 11:12:52 MET DST Organization: [Infostrada] Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!nntp.infostrada.it!news.infostrada.it!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6943 Vladislav Vasilenko ha scritto nel messaggio <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua>... >Hi Alfredo, > >"..Xilinx keeps the interpretation of the bitstream a closely guarded >secret.." It's >quotation from Xilinx "The Programmable Logic Data Book ". > >Best regards, Vlad. Yes, I can trust in Xilinx. But I suppose the every manufacturer has to give the full informations about the bitstream and internal structure to the companies doing the development tools... Luigi ###### From: Michael Dales Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: 05 Jun 2001 13:11:34 +0100 Organization: University of Glasgow Lines: 7 Message-ID: References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <3b1cc768.0@d2o947.telia.com> NNTP-Posting-Host: kettle.dcs.gla.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: singer.cent.gla.ac.uk 991743094 3294 130.209.241.124 (5 Jun 2001 12:11:34 GMT) X-Complaints-To: newsmaster@gla.ac.uk NNTP-Posting-Date: 5 Jun 2001 12:11:34 GMT User-Agent: Gnus/5.0805 (Gnus v5.8.5) Emacs/20.5 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!grolier!dispose.news.demon.net!demon!nntp.news.xara.net!xara.net!gxn.net!server6.netnews.ja.net!news.gla.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6954 If it's Virtex info you're after then Xilinx App-note 151 may be of some use. -- Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQ ###### From: "Thomas Karlsson" Newsgroups: comp.arch.fpga References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> Subject: Re: Xilinx Configuration Bitstream Date: Tue, 5 Jun 2001 13:49:22 +0100 Lines: 16 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 NNTP-Posting-Host: 194.17.253.70 X-NNTP-Posting-Host: 194.17.253.70 Message-ID: <3b1cc768.0@d2o947.telia.com> X-Trace: 5 Jun 2001 13:50:00 -0200, 194.17.253.70 X-Complaints-To: abuse@internet.telia.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!feed.news.qwest.net!dfw-peer.news.verio.net!iad-feed.news.verio.net!news.verio.net!carrier.kiev.ua!news.alkar.net!ATNS!newsfeed5.telia.com!d2o947.telia.com!194.17.253.70 Xref: chonsp.franklin.ch comp.arch.fpga:6911 > > Yes, I can trust in Xilinx. > But I suppose the every manufacturer has to give the full informations > about the bitstream and internal structure to the companies doing the > development tools... Internal structure of the device, YES, for synthesis tool developers. Bitstream format, NO. The tools for generating the bitstream are, as far as I know, only made by.....Xilinx. /Thomas ###### From: Phil James-Roxby Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Tue, 05 Jun 2001 08:51:21 -0600 Organization: Xilinx, Inc. Lines: 24 Message-ID: <3B1CF1E9.FB8F4D09@xilinx.com> References: <9fgaom$opj$1@menelao.polito.it> NNTP-Posting-Host: 149.199.185.56 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!sunqbc.risq.qc.ca!news3.bellglobal.com!border1.nntp.aus1.giganews.com!nntp1.hal-pc.org!12.120.16.16.MISMATCH!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6916 Alfredo Benso wrote: > > Hi everybody, > I am a researcher at Politecnico di Torino in Italy. > I am looking for information about the format of the Xilinx configuration > bit stream. Is the format public? Is there some document or file available > explaining how to generate a stream of configuration bits for a Xiling FPGA? > > Anybody can help? Take a look at JBits, which is a Java API giving read and write access to a Virtex configuration stream. You can find details on the Xilinx web site. Or Xilinx App. Note XAPP151 gives some information too on the configuration format for Virtex. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder --------------------------------------------------------------------- ###### From: "Austin Franklin" Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Tue, 5 Jun 2001 17:15:37 -0400 Organization: MindSpring Enterprises Lines: 23 Message-ID: <9fji5s$b2a$1@slb1.atl.mindspring.net> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> NNTP-Posting-Host: a5.f7.06.6d X-Server-Date: 5 Jun 2001 21:15:40 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!skynet.be!newsfeed.icl.net!netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6945 > >"..Xilinx keeps the interpretation of the bitstream a closely guarded > >secret.." It's > >quotation from Xilinx "The Programmable Logic Data Book ". > > > >Best regards, Vlad. > > > Yes, I can trust in Xilinx. > But I suppose the every manufacturer has to give the full informations > about the bitstream and internal structure to the companies doing the > development tools... No. NeoCAD had to decode it on their own, and they are the only people I know who ever decoded the Xilinx bitstream... They were bought by Xilinx some time ago... The only people who need the bitstream are the people developing the back end tools, NOT the design entry tools. ###### From: "Miguel Silva" Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Wed, 6 Jun 2001 11:27:00 +0100 Organization: A poorly-installed InterNetNews site Lines: 50 Message-ID: <9fl0hm$trk$1@news.up.pt> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> NNTP-Posting-Host: electro-ip-23.fe.up.pt X-Trace: news.up.pt 991823222 30580 193.136.33.225 (6 Jun 2001 10:27:02 GMT) X-Complaints-To: news@news.up.pt NNTP-Posting-Date: 6 Jun 2001 10:27:02 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!nntp01.fccn.pt!nntp02.fccn.pt!zap!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6903 The format of the bitstream is a secret but you can use JBits API from xilinx to access the information contained in the bitstream and change it. Miguel "Vladislav Vasilenko" wrote in message news:3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua... > Hi Alfredo, > > "..Xilinx keeps the interpretation of the bitstream a closely guarded > secret.." It's > quotation from Xilinx "The Programmable Logic Data Book ". > > Best regards, Vlad. > > Alfredo Benso wrote: > > > > Hi everybody, > > I am a researcher at Politecnico di Torino in Italy. > > I am looking for information about the format of the Xilinx configuration > > bit stream. Is the format public? Is there some document or file available > > explaining how to generate a stream of configuration bits for a Xiling FPGA? > > > > Anybody can help? > > > > Thanks Alfredo > > > > ----ooo---ooo---ooo---ooo---- > > BENSO Alfredo, PhD > > > > Politecnico di Torino > > > > Dip. Automatica e Informatica > > > > C.so Duca degli Abruzzi 24 > > > > Torino - Italy > > > > Phone: +39-011-564.7080 > > > > Fax: +39-011-564.7099 > > > > email: alfredo.benso@polito.it > > > > ----------ooo---ooo------------- ###### From: "Juan-Luis Lopez" Newsgroups: comp.arch.fpga Subject: RE: Xilinx Configuration Bitstream Date: Wed, 6 Jun 2001 12:39:50 +0200 Organization: BT Tel. Netnews service (readers) Lines: 50 Message-ID: <9fl144$9ch$1@titan.bt.es> References: <9fgaom$opj$1@menelao.polito.it> NNTP-Posting-Host: 212.49.150.236 Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: titan.bt.es 991823812 9617 212.49.150.236 (6 Jun 2001 10:36:52 GMT) X-Complaints-To: abuse@bt.es NNTP-Posting-Date: 6 Jun 2001 10:36:52 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2615.200 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.qis.net!btnet-peer!btnet!newsfeed.bt.es!news.bt.es!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6897 Hi Alfredo, Time ago in this newsgroup it was a thread called "XC3000A Configuration data", that maybe could answer some of your questions. I described then the few bits of the bitstream that I know. You can see the article at: http://www.fpga-faq.com/archives/25350.html#25351 Hope this helps a bit Juan-Luis Lopez Spain Alfredo Benso escribió en el mensaje de noticias 9fgaom$opj$1@menelao.polito.it... > Hi everybody, > I am a researcher at Politecnico di Torino in Italy. > I am looking for information about the format of the Xilinx configuration > bit stream. Is the format public? Is there some document or file available > explaining how to generate a stream of configuration bits for a Xiling FPGA? > > Anybody can help? > > Thanks Alfredo > > ----ooo---ooo---ooo---ooo---- > BENSO Alfredo, PhD > > Politecnico di Torino > > Dip. Automatica e Informatica > > C.so Duca degli Abruzzi 24 > > Torino - Italy > > Phone: +39-011-564.7080 > > Fax: +39-011-564.7099 > > email: alfredo.benso@polito.it > > ----------ooo---ooo------------- ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: 6 Jun 2001 18:03:49 GMT Organization: California Institute of Technology, Pasadena Lines: 18 Message-ID: <9flra5$i0a@gap.cco.caltech.edu> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> NNTP-Posting-Host: seniti.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.stanford.edu!uchinews!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:6988 "Austin Franklin" writes: (snip) >The only people who need the bitstream are the people developing the back >end tools, NOT the design entry tools. I was once working on a project that would have needed to know some of the bits. Most of the design was static, but some constants had to be changed before the data was loaded. Xilinx will tell you where the LUT bits are, at least in the 4000 series. (So you know which bits to ignore when you read the data out again.) Mostly it was loading the values for ROM compiled into the design, in a systolic array where each chip had different values. There are probably other projects that need similar information. -- glen ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Wed, 06 Jun 2001 11:17:02 -0700 Organization: Xilinx Lines: 28 Message-ID: <3B1E739D.93C2CBFB@xilinx.com> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> <9flra5$i0a@gap.cco.caltech.edu> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!opentransit.net!newsfeed.direct.ca!look.ca!border1.nntp.aus1.giganews.com!nntp1.hal-pc.org!12.120.16.16.MISMATCH!attdl1!attdl2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:6984 In Virtex ( and its derivatives ) you can load any LUT "sideways" by using the shift-register function SRL16. So you can change any LUT content on-the-fly without reconfiguring, and without interfering with all its inputs. Peter Alfke ================================= glen herrmannsfeldt wrote: > "Austin Franklin" writes: > > (snip) > > >The only people who need the bitstream are the people developing the back > >end tools, NOT the design entry tools. > > I was once working on a project that would have needed to know > some of the bits. Most of the design was static, but some constants > had to be changed before the data was loaded. Xilinx will tell you > where the LUT bits are, at least in the 4000 series. (So you know > which bits to ignore when you read the data out again.) > > Mostly it was loading the values for ROM compiled into the design, > in a systolic array where each chip had different values. > There are probably other projects that need similar information. > > -- glen ###### From: Falk Brunner Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Wed, 06 Jun 2001 22:06:51 +0200 Lines: 15 Message-ID: <3B1E8D5B.F1BA06D9@gmx.de> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> <9flra5$i0a@gap.cco.caltech.edu> <3B1E739D.93C2CBFB@xilinx.com> NNTP-Posting-Host: pec-87-102.tnt5.b2.uunet.de (149.225.87.102) Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fu-berlin.de 991859312 4998542 149.225.87.102 (16 [84877]) X-Mailer: Mozilla 4.08 [de] (Win95; I) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!pec-87-102.tnt5.b2.uunet.DE!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7008 Peter Alfke schrieb: > > In Virtex ( and its derivatives ) you can load any LUT "sideways" by using the > shift-register function SRL16. So you can change any LUT content on-the-fly > without reconfiguring, and without interfering with all its inputs. Yes, but what can you do when you would like to add a series number in your FPGA bitstream? Compile every design with a new number?? No. -- MFG Falk ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: 07 Jun 2001 00:16:47 +0200 Organization: My own Private Self Lines: 15 Message-ID: <6uhext6ypc.fsf@chonsp.franklin.ch> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> <9flra5$i0a@gap.cco.caltech.edu> <3B1E739D.93C2CBFB@xilinx.com> <3B1E8D5B.F1BA06D9@gmx.de> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 991865807 1366 10.0.3.2 (6 Jun 2001 22:16:47 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 6 Jun 2001 22:16:47 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:7011 Falk Brunner writes: > Yes, but what can you do when you would like to add a series number in > your FPGA bitstream? > Compile every design with a new number?? No. Use JBits to make an serial number modification tool. That is an _very_easy_ thing to do. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual Robbery ###### From: "Austin Franklin" Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Thu, 7 Jun 2001 10:59:46 -0400 Organization: MindSpring Enterprises Lines: 18 Message-ID: <9fo4ul$m66$1@slb4.atl.mindspring.net> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> <9flra5$i0a@gap.cco.caltech.edu> NNTP-Posting-Host: a5.f7.07.2d X-Server-Date: 7 Jun 2001 15:00:37 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!pinatubo.switch.ch!news-ge.switch.ch!newsfeed00.sul.t-online.de!t-online.de!fr.usenet-edu.net!usenet-edu.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.skycache.com!Cidera!netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7066 > >The only people who need the bitstream are the people developing the back > >end tools, NOT the design entry tools. > > I was once working on a project that would have needed to know > some of the bits. Most of the design was static, but some constants > had to be changed before the data was loaded. Xilinx will tell you > where the LUT bits are, at least in the 4000 series. (So you know > which bits to ignore when you read the data out again.) > > Mostly it was loading the values for ROM compiled into the design, > in a systolic array where each chip had different values. > There are probably other projects that need similar information. Isn't that still back end tools though? Having the front end tools know the bitstream wouldn't help this as far as I can tell. ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: 7 Jun 2001 17:35:25 GMT Organization: California Institute of Technology, Pasadena Lines: 24 Message-ID: <9foe0t$pbc@gap.cco.caltech.edu> References: <9fgaom$opj$1@menelao.polito.it> <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua> <9fji5s$b2a$1@slb1.atl.mindspring.net> <9flra5$i0a@gap.cco.caltech.edu> <9fo4ul$m66$1@slb4.atl.mindspring.net> NNTP-Posting-Host: seniti.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!howland.erols.net!vixen.cso.uiuc.edu!uchinews!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:7055 "Austin Franklin" writes: >> >The only people who need the bitstream are the people developing the back >> >end tools, NOT the design entry tools. >> >> I was once working on a project that would have needed to know >> some of the bits. Most of the design was static, but some constants >> had to be changed before the data was loaded. Xilinx will tell you >> where the LUT bits are, at least in the 4000 series. (So you know >> which bits to ignore when you read the data out again.) >> >> Mostly it was loading the values for ROM compiled into the design, >> in a systolic array where each chip had different values. >> There are probably other projects that need similar information. >Isn't that still back end tools though? Having the front end tools know the >bitstream wouldn't help this as far as I can tell. I mean after the back end tools. At the time the stream is loaded into the FPGA array the ROM data is modified. About the equivalent of patching an .EXE file after compiling and linking. -- glen ###### From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <9fgaom$opj$1@menelao.polito.it> Subject: Re: Xilinx Configuration Bitstream Lines: 66 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: <0sPZ6.944$5m1.133917@news.pacbell.net> Date: Mon, 25 Jun 2001 16:01:34 -0700 NNTP-Posting-Host: 64.174.106.246 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 993510268 64.174.106.246 (Mon, 25 Jun 2001 16:04:28 PDT) NNTP-Posting-Date: Mon, 25 Jun 2001 16:04:28 PDT Organization: SBC Internet Services Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feeder.via.net!cyclone-sf.pbi.net!206.13.28.143!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7669 As far as I know Xilinx has published bitstream Information on the xc6200 line (now defunct) and some information on the Virtex family. The Virtex information is in XAPP 151 "Virtex Configuration Architecture Advanced Users Guide." We use that information to dynamically configure a target system through the select map. We designed a microcoded state machine / controller that consists of a single Block Ram and 20 CLBs in a Virtex or VirtexE. We read a placed and routed design (.ncd) into what we call a "FPGA Browser" where you can select a block ram. You can change that Ram while the Virtex is running live. If that Ram is a controller ram you can pop up the "C" code and edit that then download directly into the running Virtex system. It takes less than 1 second to compile your code and download the resulting partial configuration bitstream. The controller runs at 125 MHz. To use the controller you connect the state bits up to Flip-flop clock enables and mux controls and other control bits of your design (resets or what not). The program then outputs bitstream data when connected live to a system or INIT_xx style initialization data for the UCF file. What is great about this approach (IMHO) is that you can change the behavior of your design without changing the design itself (in that all routing and placement are held constant just the data content of the ram is changed). We just showed this at live at DAC where we were the only company doing partial reconfiguration. Steve Casselman, President Virtual Computer Corporation www.vcc.com ###### From: Michael Stevens Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Tue, 26 Jun 2001 09:20:29 -0400 Organization: Alcatel CID Lines: 42 Message-ID: <3B388C1D.42384E2C@alcatel.com> References: <9fgaom$opj$1@menelao.polito.it> <0sPZ6.944$5m1.133917@news.pacbell.net> NNTP-Posting-Host: pcmsteven.ca.newbridge.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------6DB7B79BFAFEB37229124B80" X-Trace: kannews.ca.alcatel.com 993561325 24202 138.120.46.56 (26 Jun 2001 13:15:25 GMT) X-Complaints-To: news@ca.alcatel.com NNTP-Posting-Date: 26 Jun 2001 13:15:25 GMT X-Mailer: Mozilla 4.61 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!news3.bellglobal.com!kannews.ca.alcatel.com!kannews.ca.alcatel.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7513 This is a multi-part message in MIME format. --------------6DB7B79BFAFEB37229124B80 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Do you know if they have published anything regarding the ancient xc2000 series? I recently picked up a bunch of recycled xc2018's figuring I'd learn some VHDL and get some home projects on the go. Finding S/W to do P&A and to generate the configuration bitstream seems to be difficult as the current batch of free tools do not support these discontinued devices. Cheers, Michael --------------6DB7B79BFAFEB37229124B80 Content-Type: text/x-vcard; charset=us-ascii; name="michael.stevens.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Michael Stevens Content-Disposition: attachment; filename="michael.stevens.vcf" begin:vcard n:Stevens;Michael tel;work:(613) 784-6145 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:michael.stevens@alcatel.com x-mozilla-cpt:;10896 fn:Michael Stevens end:vcard --------------6DB7B79BFAFEB37229124B80-- ###### From: hamish@cloud.net.au Subject: Re: Xilinx Configuration Bitstream Newsgroups: comp.arch.fpga References: <9fgaom$opj$1@menelao.polito.it> <0sPZ6.944$5m1.133917@news.pacbell.net> User-Agent: tin/1.5.8-20010221 ("Blue Water") (UNIX) (Linux/2.2.18 (i586)) Lines: 11 Message-ID: Date: Tue, 26 Jun 2001 14:00:39 GMT NNTP-Posting-Host: 203.164.64.6 X-Complaints-To: abuse@optushome.com.au X-Trace: news1.eburwd1.vic.optushome.com.au 993564039 203.164.64.6 (Wed, 27 Jun 2001 00:00:39 EST) NNTP-Posting-Date: Wed, 27 Jun 2001 00:00:39 EST Organization: @Home Network Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news.mel.connect.com.au!newshub1.rdc1.nsw.optushome.com.au!news1.eburwd1.vic.optushome.com.au.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7555 Steve Casselman wrote: > constant just the data content of the ram is changed). We just showed this > at live at DAC where we were the only company doing partial reconfiguration. Is that partial reconfiguration using the actual features in the tools/chips though? Or did you just change the block RAM contents the regular way? Hamish -- Hamish Moffatt VK3SB ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Xilinx Configuration Bitstream Date: Tue, 26 Jun 2001 09:15:20 -0700 Organization: Xilinx Lines: 30 Message-ID: <3B38B519.8F6CCA61@xilinx.com> References: <9fgaom$opj$1@menelao.polito.it> <0sPZ6.944$5m1.133917@news.pacbell.net> <3B388C1D.42384E2C@alcatel.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 (Macintosh; U; PPC) X-Accept-Language: en To: Michael Stevens Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.berkeley.edu!ucberkeley!feed.news.qwest.net!dfw-peer.news.verio.net!dfw-feed.news.verio.net!news.verio.net!nntp1.hal-pc.org!12.120.16.16.MISMATCH!attdl1!attdl2!attsl2!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7480 Michael, my advice, if you want to learn about FPGAs and VHDL, take those XC2000 parts and throw them in the garbage can. Just like you would do with an intel 286 processor of similar vintage No software, no support, ancient features, slow as molasses.... Yes they work, but for little money you can aget a Spartan or Spartan XLpart ( XC4000 generation ), or, better yet, get Spartan-II or Virtex-E, two families that are mature, but halfway modern. My analogy is that one year of FPGA evolution equals 20 years of human aging. And the XC2018 is 15 years old, that makes it a 300 year old very senior citizen. Definitely retirement age. Peter Alfke ======================== Michael Stevens wrote: > Do you know if they have published anything regarding the ancient xc2000 series? > > I recently picked up a bunch of recycled xc2018's figuring I'd learn some VHDL > and > get some home projects on the go. Finding S/W to do P&A and to generate the > configuration > bitstream seems to be difficult as the current batch of free tools do not > support these > discontinued devices. > > Cheers, > Michael ###### From: "Steve Casselman" Newsgroups: comp.arch.fpga References: <9fgaom$opj$1@menelao.polito.it> <0sPZ6.944$5m1.133917@news.pacbell.net> Subject: Re: Xilinx Configuration Bitstream Lines: 39 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Tue, 26 Jun 2001 11:18:54 -0700 NNTP-Posting-Host: 64.174.106.246 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 993579675 64.174.106.246 (Tue, 26 Jun 2001 11:21:15 PDT) NNTP-Posting-Date: Tue, 26 Jun 2001 11:21:15 PDT Organization: SBC Internet Services Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!cyclone.swbell.net!cyclone-sf.pbi.net!206.13.28.143!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:7647 Yes we use the select map port. We can change the both the Block Ram and any LUT. We can readback the state of all the flop too. This is done with a tool we developed. The FPGA Browser converts the .ncd file to a xdl (xilinx design language) file. There is a little known command (xdl or xdl.exe) that translates the .ncd binary format to a fully ASCII format. This command will also give you generic information about all the Xilinx devices. It shows you where all the tiles are on the device as well as all the interconnect (pips and switches) information. I'm pretty sure all the information to reverse the bit stream is extracted by the xdl command (it will produce files over 100 MBytes). This really makes it easy to write tools. So since we are power users we developed a tool for power users. We developed a download cable that uses active buffers and connects to the PCI bus. Steve Casselman, CEO Virtual Computer Corporation wrote in message news:bA0_6.256$A5.1081@news1.eburwd1.vic.optushome.com.au... > Steve Casselman wrote: > > constant just the data content of the ram is changed). We just showed this > > at live at DAC where we were the only company doing partial reconfiguration. > > Is that partial reconfiguration using the actual features in the tools/chips > though? Or did you just change the block RAM contents the regular way? > > > Hamish > -- > Hamish Moffatt VK3SB >