Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: More detailed Spartan II CLB drawings? X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 06 Mar 2001 15:44:27 -0800 Message-ID: Lines: 16 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 6 Mar 2001 15:45:33 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!blackbush.xlink.net!howland.erols.net!newsfeed.mathworks.com!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:5048 Is there any document that gives more detailed logic drawings of the Spartan II CLBs? The description and diagram in the data sheet are sort of, well, spartan. I'm trying to figure out whether I can do certain things like simultaneously route the carry out both to the carry-in of the CLB above *and* to the GRM or to the CLB on the right. Figure 3 in the data sheet shows a slice, but it has big unexplained blocks like "Carray and Control Logic". Also, the possible routing choices for signals are not obvious. The text talks about the F5 and F6 multipliexers, but they don't appear in the drawing at all. These details aren't considered proprietary trade secrets, are they? That would make it hard for me to figure out how to best design for this part. ###### From: Chris Dunlap Newsgroups: comp.arch.fpga Subject: Re: More detailed Spartan II CLB drawings? Date: Tue, 06 Mar 2001 17:24:48 -0700 Organization: Xilinx, Inc. Lines: 24 Message-ID: <3AA57FD0.FB09E2CE@xilinx.com> References: NNTP-Posting-Host: 149.199.190.169 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.74 [en]C-CCK-MCD (Win98; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!newsfeed.direct.ca!look.ca!nntp2.aus1.giganews.com!NetNews1!attws2!attsl2!attla2!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:5036 You can always look in FPGA editor. Nothing can be left out there. If its routed or routable, its there. Chris Eric Smith wrote: > Is there any document that gives more detailed logic drawings of > the Spartan II CLBs? The description and diagram in the data sheet > are sort of, well, spartan. > > I'm trying to figure out whether I can do certain things like > simultaneously route the carry out both to the carry-in of the CLB above > *and* to the GRM or to the CLB on the right. Figure 3 in the data sheet > shows a slice, but it has big unexplained blocks like "Carray and Control > Logic". Also, the possible routing choices for signals are not obvious. > > The text talks about the F5 and F6 multipliexers, but they don't appear > in the drawing at all. > > These details aren't considered proprietary trade secrets, are they? > That would make it hard for me to figure out how to best design for > this part. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: More detailed Spartan II CLB drawings? Date: 07 Mar 2001 22:08:22 +0100 Organization: My own Private Self Lines: 34 Message-ID: <6ur9094795.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 983999302 1448 10.0.3.2 (7 Mar 2001 21:08:22 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 7 Mar 2001 21:08:22 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:5056 Eric Smith writes: > Is there any document that gives more detailed logic drawings of > the Spartan II CLBs? Get the Virtex data sheet (Virtex are bitstream-identical with Spartan-II, for equivalent sizes, so the CLB is identical): http://www.xilinx.com/partinfo/ds003.pdf Page 7, Figure 5 is what you want to look at. > The description and diagram in the data sheet > are sort of, well, spartan. :-) > I'm trying to figure out whether I can do certain things like > simultaneously route the carry out both to the carry-in of the CLB above > *and* to the GRM or to the CLB on the right. Yes, both of these connections are fixed wired actually. > These details aren't considered proprietary trade secrets, are they? No. They are published. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic ###### Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch.fpga Subject: Re: More detailed Spartan II CLB drawings? References: <3AA57FD0.FB09E2CE@xilinx.com> X-Disclaimer: Everything I write is false. Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 07 Mar 2001 14:49:33 -0800 Message-ID: Lines: 9 User-Agent: Gnus/5.0807 (Gnus v5.8.7) Emacs/20.7 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ruckus.brouhaha.com X-Trace: 7 Mar 2001 14:50:49 -0800, ruckus.brouhaha.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!news.kjsl.com!news.spies.com!ruckus.brouhaha.com Xref: chonsp.franklin.ch comp.arch.fpga:5069 Chris Dunlap writes: > You can always look in FPGA editor. Nothing can be left out there. If its > routed or routable, its there. I don't seem to have an FPGA editor. Is it supposed to be available in WebPACK ISE, or is it only in the "real" software? Thanks! Eric ###### From: Kent Orthner Newsgroups: comp.arch.fpga Subject: Re: More detailed Spartan II CLB drawings? Date: 09 Mar 2001 10:13:32 +0900 Organization: ... Lines: 33 Sender: korthner@KENT Message-ID: References: NNTP-Posting-Host: dhcp238.inf.furukawa.co.jp X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Canyonlands" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.dplanet.ch!news-ge.switch.ch!blackbush.xlink.net!uni-erlangen.de!newsfeed1.telenordia.se!news.algonet.se!algonet!newsfeed.rt.ru!newsfeed.mesh.ad.jp!news.ksw.feedmania.org!nf1.xephion.ne.jp!fintnews!ifnews!inf-gw!postmaster Xref: chonsp.franklin.ch comp.arch.fpga:5090 Hey, Eric. Seeing as you don't have the FPGA Editor, I'd try emailing Xilinx, asking for the JBits package. There's a email address you have to send your reauest to, then they ask you a question or two, and then give you access to the package. Part of the JBits package includes an explanation of th Virtex/ Spartan-II architacture. It's not as detailed as FPGA editor, but it's much better than the databook. HTH, -Kent Eric Smith writes: > Is there any document that gives more detailed logic drawings of > the Spartan II CLBs? The description and diagram in the data sheet > are sort of, well, spartan. > > I'm trying to figure out whether I can do certain things like > simultaneously route the carry out both to the carry-in of the CLB above > *and* to the GRM or to the CLB on the right. Figure 3 in the data sheet > shows a slice, but it has big unexplained blocks like "Carray and Control > Logic". Also, the possible routing choices for signals are not obvious. > > The text talks about the F5 and F6 multipliexers, but they don't appear > in the drawing at all. > > These details aren't considered proprietary trade secrets, are they? > That would make it hard for me to figure out how to best design for > this part. ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: More detailed Spartan II CLB drawings? Date: 11 Mar 2001 23:09:55 +0100 Organization: My own Private Self Lines: 25 Message-ID: <6u8zmcez4c.fsf@chonsp.franklin.ch> References: NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 984348595 744 10.0.3.2 (11 Mar 2001 22:09:55 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 11 Mar 2001 22:09:55 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:5102 Kent Orthner writes: > Part of the JBits package includes an explanation of th Virtex/ > Spartan-II architacture. No need of getting JBits just for the "Slice" graphic in the Virtex Architecture Guide. It is nearly[1] identical to the graphic[2] in the Virtex data sheet, available to anyone direct from the Xilinx web site. [1] apart from the JBits specific "numbering" of the features for introducing the JBits constants used to configure the features. [2] http://www.xilinx.com/partinfo/ds003.pdf, Page 7, Figure 5 > but it's much better than the databook. Next to identical to the Virtex data sheet / databook. Most likely copied from there and then annotated. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic