Message-ID: <3A9C0C45.3A3D8431@ntlworld.com> From: Bard_64 Reply-To: Bard_64@ntlworld.com X-Mailer: Mozilla 4.7 [en]C-CCK-MCD NetscapeOnline.co.uk (Win95; I) X-Accept-Language: en-GB,en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Interfacing Xilinx 4003 to an IDE Hard Disk interface. Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 Date: Tue, 27 Feb 2001 20:21:25 +0000 NNTP-Posting-Host: 213.104.97.132 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 983305084 213.104.97.132 (Tue, 27 Feb 2001 20:18:04 GMT) NNTP-Posting-Date: Tue, 27 Feb 2001 20:18:04 GMT Organization: ntlworld News Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!dispose.news.demon.net!demon!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4894 Hello Everyone. I am currently doing backgroud reading on a project involving the interfacing of a Hard disk to a Palm Pilot. I was wondering could it be possible to access the IDE interface using an FPGA (specifically the X4003). Thanks Daniel ###### Message-ID: <3A9C5D9B.4E6F633D@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 38 Date: Wed, 28 Feb 2001 02:08:27 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 983326113 62.254.210.251 (Wed, 28 Feb 2001 02:08:33 GMT) NNTP-Posting-Date: Wed, 28 Feb 2001 02:08:33 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!news1.carrier1.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4904 Bard_64 wrote: > Hello Everyone. > > I am currently doing backgroud reading on a project > involving the > interfacing of a Hard disk to a Palm Pilot. > > I was wondering could it be possible to access the IDE > interface > using an FPGA (specifically the X4003). > > Thanks > > Daniel Question: What i/f has the PP got ? There are basically 3 ``levels'' of IDE: (1) PIO: Programmed I/O i.e. the disk is just treated as a dumb ISA peripheral & you read/write data via some polled/int driven s/w routine. [NB the data port is 16 bits wide but all the other registers are 8]. (2) DMA: Old fashioned 80?? DMA. Single transfer at a time. (2a) MultiDMA: As above but you can do bursts as long as the DMA req's active. (3) UDMA: A ``source synchronous'' abomination but it can get very high data rates, UDMA66 up to 133MBytes/sec. Hard to design & get right since the h/w protocol is both async wrt your system clock & tediously complicated. For something like a PP I would not have thought you'd need to go beyond 2a if that. ###### Message-ID: <3A9D3BBB.56ADF552@ntlworld.com> From: Bard_64 Reply-To: Bard_64@ntlworld.com X-Mailer: Mozilla 4.7 [en]C-CCK-MCD NetscapeOnline.co.uk (Win95; I) X-Accept-Language: en-GB,en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Wed, 28 Feb 2001 17:56:11 +0000 NNTP-Posting-Host: 213.104.100.85 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 983382763 213.104.100.85 (Wed, 28 Feb 2001 17:52:43 GMT) NNTP-Posting-Date: Wed, 28 Feb 2001 17:52:43 GMT Organization: ntlworld News Service Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!nntp.news.xara.net!xara.net!gxn.net!server6.netnews.ja.net!server4.netnews.ja.net!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4906 Rick Filipkiewicz wrote > > Question: What i/f has the PP got ? There are basically 3 ``levels'' of > IDE: > > (1) PIO: Programmed I/O i.e. the disk is just treated as a dumb ISA > peripheral & you read/write data via some polled/int driven s/w routine. > [NB the data port is 16 bits wide but all the other registers are 8]. > > (2) DMA: Old fashioned 80?? DMA. Single transfer at a time. > > (2a) MultiDMA: As above but you can do bursts as long as the DMA req's > active. > > (3) UDMA: A ``source synchronous'' abomination but it can get very high > data rates, UDMA66 up to 133MBytes/sec. Hard to design & get right since > the h/w protocol is both async wrt your system clock & tediously > complicated. > > For something like a PP I would not have thought you'd need to go beyond 2a > if that. Hello Rick Thanks for replying. In the specificfation data from the Hard disk is to be sent to the Palm Pilot via the Palm Pilot's RS-232 link. Therefore to reduce control overheads I am looking at developing some form of secondary processor to handle file input and retrieval from the hardrive, then sending the data up the RS 232, Daniel ###### Message-ID: <3A9DC5C5.FE68E5CE@banet.net> From: yuryws@banet.net Reply-To: yuryws@banet.net X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: uk,ru MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 Date: Thu, 01 Mar 2001 03:37:57 GMT NNTP-Posting-Host: 24.185.185.107 X-Trace: news02.optonline.net 983417877 24.185.185.107 (Wed, 28 Feb 2001 22:37:57 EST) NNTP-Posting-Date: Wed, 28 Feb 2001 22:37:57 EST Organization: Optimum Online Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.onemain.com!feed1.onemain.com!news-out.usenetserver.com!news-out-sjo.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4922 Side note: uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) not 133 MB/sec. -- Yury Rick Filipkiewicz wrote: > Bard_64 wrote: > > > Hello Everyone. > > > > I am currently doing backgroud reading on a project > > involving the > > interfacing of a Hard disk to a Palm Pilot. > > > > I was wondering could it be possible to access the IDE > > interface > > using an FPGA (specifically the X4003). > > > > Thanks > > > > Daniel > > Question: What i/f has the PP got ? There are basically 3 ``levels'' of > IDE: > > (1) PIO: Programmed I/O i.e. the disk is just treated as a dumb ISA > peripheral & you read/write data via some polled/int driven s/w routine. > [NB the data port is 16 bits wide but all the other registers are 8]. > > (2) DMA: Old fashioned 80?? DMA. Single transfer at a time. > > (2a) MultiDMA: As above but you can do bursts as long as the DMA req's > active. > > (3) UDMA: A ``source synchronous'' abomination but it can get very high > data rates, UDMA66 up to 133MBytes/sec. Hard to design & get right since > the h/w protocol is both async wrt your system clock & tediously > complicated. > > For something like a PP I would not have thought you'd need to go beyond 2a > if that. ###### Message-ID: <3A9DC64D.6182C915@banet.net> From: yuryws@banet.net Reply-To: yuryws@banet.net X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: uk,ru MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 25 Date: Thu, 01 Mar 2001 03:40:12 GMT NNTP-Posting-Host: 24.185.185.107 X-Trace: news02.optonline.net 983418012 24.185.185.107 (Wed, 28 Feb 2001 22:40:12 EST) NNTP-Posting-Date: Wed, 28 Feb 2001 22:40:12 EST Organization: Optimum Online Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!grolier!dispose.news.demon.net!demon!europa.netcrusader.net!64.152.100.70!news-out.usenetserver.com!news-out-sjo.usenetserver.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4959 Recently I completed a design interfacing Spartan XL (which is rather similar to 4000 family) to IDE interface implementing PIO-4 and uDMA66 protocols. Yes it is possible. -- Yury Bard_64 wrote: > Hello Everyone. > > I am currently doing backgroud reading on a project > involving the > interfacing of a Hard disk to a Palm Pilot. > > I was wondering could it be possible to access the IDE > interface > using an FPGA (specifically the X4003). > > Thanks > > Daniel ###### Message-ID: <3A9EEAF6.606D4388@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 15 Date: Fri, 02 Mar 2001 00:36:06 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 983493368 62.254.210.251 (Fri, 02 Mar 2001 00:36:08 GMT) NNTP-Posting-Date: Fri, 02 Mar 2001 00:36:08 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!btnet-peer1!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4934 yuryws@banet.net wrote: > Side note: > uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) > not 133 MB/sec. > > -- Yury > > R UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = 133MBytes/sec. ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. Organization: dspia inc. http://www.dspia.com Message-ID: References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 24 Date: Fri, 02 Mar 2001 06:11:35 GMT NNTP-Posting-Host: 24.16.43.54 X-Complaints-To: abuse@home.net X-Trace: news1.frmt1.sfba.home.com 983513495 24.16.43.54 (Thu, 01 Mar 2001 22:11:35 PST) NNTP-Posting-Date: Thu, 01 Mar 2001 22:11:35 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.frmt1.sfba.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4956 On Fri, 02 Mar 2001 00:36:06 +0000, Rick Filipkiewicz wrote: >yuryws@banet.net wrote: > >> Side note: >> uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) >> not 133 MB/sec. >> >> -- Yury >> >> R > >UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = >133MBytes/sec. I believe you're mistaken. UDMA66 (UDMA Mode 4) is 33 M transitions/s not 33 MHz; IOW, it has a 16.67 MHz clock and transmits data at both edges so it has a 66.67 MB/s transfer rate. Muzaffer FPGA DSP Consulting http://www.dspia.com ###### Message-ID: <3AA02D4A.40D4AD01@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 34 Date: Fri, 02 Mar 2001 23:31:23 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 983575885 62.254.210.251 (Fri, 02 Mar 2001 23:31:25 GMT) NNTP-Posting-Date: Fri, 02 Mar 2001 23:31:25 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!btnet-peer1!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4931 Muzaffer Kal wrote: > On Fri, 02 Mar 2001 00:36:06 +0000, Rick Filipkiewicz > wrote: > > >yuryws@banet.net wrote: > > > >> Side note: > >> uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) > >> not 133 MB/sec. > >> > >> -- Yury > >> > >> R > > > >UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = > >133MBytes/sec. > > I believe you're mistaken. UDMA66 (UDMA Mode 4) is 33 M transitions/s > not 33 MHz; IOW, it has a 16.67 MHz clock and transmits data at both > edges so it has a 66.67 MB/s transfer rate. > > Muzaffer > > FPGA DSP Consulting > http://www.dspia.com I've *built* a UDMA33 interface and that clock runs at 16.66 ergo the UDMA66 interface I'm about to build will have a 33.33MHz clock. Note that the clock frequency is really the read clock sent by the disk on IORDY. The write clock is under my own control. ###### From: muzaffer@dspia.com Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. Date: 03 Mar 2001 00:47:34 GMT Organization: Concentric Internet Services Lines: 45 Sender: Muzaffer Kal Message-ID: <18jv9tgubuh38ui9gba3hauq11l4mbff72@4ax.com> References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> <3AA02D4A.40D4AD01@algor.co.uk> Reply-To: muzaffer@dspia.com NNTP-Posting-Host: 209.31.228.232 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Newsreader: Forte Agent 1.8/32.548 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fu-berlin.de!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!sjc1.nntp.concentric.net!newsfeed.concentric.net!global-news-master Xref: chonsp.franklin.ch comp.arch.fpga:4954 Rick Filipkiewicz wrote: > > >Muzaffer Kal wrote: > >> On Fri, 02 Mar 2001 00:36:06 +0000, Rick Filipkiewicz >> wrote: >> >> >yuryws@banet.net wrote: >> > >> >> Side note: >> >> uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) >> >> not 133 MB/sec. >> >> >> >> -- Yury >> >> >> >> R >> > >> >UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = >> >133MBytes/sec. >> >> I believe you're mistaken. UDMA66 (UDMA Mode 4) is 33 M transitions/s >> not 33 MHz; IOW, it has a 16.67 MHz clock and transmits data at both >> edges so it has a 66.67 MB/s transfer rate. >> >> Muzaffer >> >> FPGA DSP Consulting >> http://www.dspia.com > >I've *built* a UDMA33 interface and that clock runs at 16.66 ergo the UDMA66 >interface I'm about to build will have a 33.33MHz clock. Note that the clock >frequency is really the read clock sent by the disk on IORDY. The write clock is >under my own control. I am looking at this document http://www.t13.org/project/d1410r1a.pdf specifically table 57, figure 50 and figure 55 (on pages 361, 365 and 370 respectively). I'd appreciate if you could tell me how one gets 133 MB/s with a design compliant to this document. Muzaffer FPGA DSP Consulting http://www.dspia.com ###### Message-ID: <3AA06B33.DB6737AA@banet.net> From: yuryws@banet.net Reply-To: yuryws@banet.net X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: uk,ru MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 18 Date: Sat, 03 Mar 2001 03:50:17 GMT NNTP-Posting-Host: 24.185.185.107 X-Trace: news02.optonline.net 983591417 24.185.185.107 (Fri, 02 Mar 2001 22:50:17 EST) NNTP-Posting-Date: Fri, 02 Mar 2001 22:50:17 EST Organization: Optimum Online Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.dplanet.ch!news-ge.switch.ch!news.bme.hu!news.tele.dk!209.50.235.254!europa.netcrusader.net!152.163.239.130!portc01.blue.aol.com!news.stealth.net!24.30.200.2.MISMATCH!news-east.rr.com!news.rr.com!news01.optonline.net!news02.optonline.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4921 2 bytes every 30 ns (approximately 27 ns/ 32 ns), not 4 bytes every 30 ns. This is where your error is. Rick Filipkiewicz wrote: > yuryws@banet.net wrote: > > > Side note: > > uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) > > not 133 MB/sec. > > > > -- Yury > > > > R > > UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = > 133MBytes/sec. ###### From: "Heinz Wolter" Newsgroups: comp.arch.fpga References: <3A9C0C45.3A3D8431@ntlworld.com> Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. Lines: 43 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Sun, 04 Mar 2001 03:47:38 GMT NNTP-Posting-Host: 64.230.140.189 X-Trace: news20.bellglobal.com 983677658 64.230.140.189 (Sat, 03 Mar 2001 22:47:38 EST) NNTP-Posting-Date: Sat, 03 Mar 2001 22:47:38 EST Organization: Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!nntp01.fccn.pt!news.uevora.pt!sagan!news-raspail.gip.net!news.gsl.net!gip.net!fr.clara.net!heighliner.fr.clara.net!grolier!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!howland.erols.net!sunqbc.risq.qc.ca!news3.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4973 If your're interfacing to a serial port on the Palm Pilot, then that's very obviously going to be your limiting factor. I don't think a Dragonball could sustain 115kbit/s of even if the built in uart supports that baud rate. PIO mode should do. Now if you were going to a Visor, you'd be better off with an FPGA- it has a Compact Flash slot - with parallel bus signals - so a simple decoding and latch arrangement would work- a PLD could even be enough Any simple microcontroller should be able to handle this- even bit bashing a software uart. Take a look at a system from MVS (<$100$US) -I think they're using a Scenix PIC clone. I know this isn't an FPGA solution, but there are many ways to skin a cat - some a lot easier and cheaper than others... unless you're just after the FPGA learning exercise. http://www.star.net/people/~mvs/SDRVSPEC.TXT Regards, Heinz Wolter "Bard_64" wrote in message news:3A9C0C45.3A3D8431@ntlworld.com... > > > > Hello Everyone. > > I am currently doing backgroud reading on a project > involving the > interfacing of a Hard disk to a Palm Pilot. > > I was wondering could it be possible to access the IDE > interface > using an FPGA (specifically the X4003). > > Thanks > > Daniel > ###### Message-ID: <3AA28EFA.F02BA500@sympatico.ca> From: Eric Montreal X-Mailer: Mozilla 4.6 [en] (Win98; U) X-Accept-Language: en,fr-CA,fr-FR MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> <3AA02D4A.40D4AD01@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 69 Date: Sun, 04 Mar 2001 18:51:21 GMT NNTP-Posting-Host: 64.229.198.205 X-Trace: news20.bellglobal.com 983731881 64.229.198.205 (Sun, 04 Mar 2001 13:51:21 EST) NNTP-Posting-Date: Sun, 04 Mar 2001 13:51:21 EST Organization: Sympatico Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!grolier!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!news3.bellglobal.com!nf2.bellglobal.com!news20.bellglobal.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4980 AFAIK, Muzaffer Kal is right. The latest T13 document he references clarify the data rates / throughput http://www.t13.org/project/d1410r1a.pdf Look page numbered 400 (414 in acrobat reader) third paragraph, and you'll find the exact transfert speed for all modes. If you made a UDMA interface that runs a 16.67 Mhz, thus transferring 16.67 * 2[transfers per clock] * 2[bytes per transfert], then it's UDMA mode 4 (AKA UDMA66) and not UDMA33. If you plan to build a UDMA controller with a 33 Mhz clock, you're ahead of times and already building a UDMA133 interface. IOW, you will simply overclock your drive, and, as usual, that's pretty sure to work in the lab / fail in the field. The fastest established standard, UDMA100, uses a 25 Mhz clock to attain 25*2*2=100 MBytes per second. Double check the timing in table 57 ( page numbered 361 (375 in acrobat reader)) "T2cyctyp" for UDMA mode 2 (AKA UDMA33) is 120 ns (8.33 Mhz) . "T2cyctyp" for UDMA mode 4 is 60 ns (16.67 Mhz) while Tcyc applies to either half clock period and is specified to allow for unequal High / Low clock times. Tcyc is *not* the clock cycle time. Hope this helps. Eric. ------------------------------------- Rick Filipkiewicz wrote: > Muzaffer Kal wrote: > > > On Fri, 02 Mar 2001 00:36:06 +0000, Rick Filipkiewicz > > wrote: > > > > >yuryws@banet.net wrote: > > > > > >> Side note: > > >> uDMA66 burst transfer rate is approximately 66 MB/sec (4 bytes every 57 ns) > > >> not 133 MB/sec. > > >> > > >> -- Yury > > >> > > >> R > > > > > >UDMA66 = 33MHz clock. 16 bits on each edge = 4 bytes every 30nsec = > > >133MBytes/sec. > > > > I believe you're mistaken. UDMA66 (UDMA Mode 4) is 33 M transitions/s > > not 33 MHz; IOW, it has a 16.67 MHz clock and transmits data at both > > edges so it has a 66.67 MB/s transfer rate. > > > > Muzaffer > > > > FPGA DSP Consulting > > http://www.dspia.com > > I've *built* a UDMA33 interface and that clock runs at 16.66 ergo the UDMA66 > interface I'm about to build will have a 33.33MHz clock. Note that the clock > frequency is really the read clock sent by the disk on IORDY. The write clock is > under my own control. ###### Message-ID: <3AA2E1D4.9DA95EE6@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface. References: <3A9C0C45.3A3D8431@ntlworld.com> <3A9C5D9B.4E6F633D@algor.co.uk> <3A9DC5C5.FE68E5CE@banet.net> <3A9EEAF6.606D4388@algor.co.uk> <3AA02D4A.40D4AD01@algor.co.uk> <3AA28EFA.F02BA500@sympatico.ca> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 49 Date: Mon, 05 Mar 2001 00:46:12 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news6-win.server.ntlworld.com 983753176 62.254.210.251 (Mon, 05 Mar 2001 00:46:16 GMT) NNTP-Posting-Date: Mon, 05 Mar 2001 00:46:16 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!grolier!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news6-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4994 Eric Montreal wrote: > AFAIK, Muzaffer Kal is right. > > The latest T13 document he references clarify the data rates / throughput > http://www.t13.org/project/d1410r1a.pdf > > Look page numbered 400 (414 in acrobat reader) third paragraph, > and you'll find the exact transfert speed for all modes. > > If you made a UDMA interface that runs a 16.67 Mhz, thus transferring > 16.67 * 2[transfers per clock] * 2[bytes per transfert], then it's UDMA > mode 4 (AKA UDMA66) and not UDMA33. > > If you plan to build a UDMA controller with a 33 Mhz clock, you're > ahead of times and already building a UDMA133 interface. > IOW, you will simply overclock your drive, and, as usual, that's pretty > sure to work in the lab / fail in the field. > > The fastest established standard, UDMA100, uses a 25 Mhz clock > to attain 25*2*2=100 MBytes per second. > > Double check the timing in table 57 ( page numbered 361 (375 in acrobat reader)) > > "T2cyctyp" for UDMA mode 2 (AKA UDMA33) is 120 ns (8.33 Mhz) . > > "T2cyctyp" for UDMA mode 4 is 60 ns (16.67 Mhz) while Tcyc applies to either > half clock period and is specified to allow for unequal High / Low clock times. > Tcyc is *not* the clock cycle time. > > Hope this helps. > > Eric. > > ------------------------------------- > > I stand corrected. I was designing for mode 2 i.e UDMA33. But its such a long time ago that I thought I'd designed the i/f around a 16.67 MHz clock & not an 8.33MHz one! In fact, dependent on the speed the logic's clocked at, it will already handle a 16.67MHz clock. This is great since I have to do practically no work to get the client's requested UDMA66, I don't see any great problem with UDMA100, and for once I can get ahead of the game and invent UDMA133 [mode 6 ?]. Once again apologies to all.