From: sulimma@my-deja.com Newsgroups: comp.arch.fpga Subject: Foundation FPGA Editor hard macros in VHDL Date: Tue, 23 Jan 2001 11:37:11 GMT Organization: Deja.com Lines: 13 Message-ID: <94jqd7$ilp$1@nnrp1.deja.com> NNTP-Posting-Host: 141.2.84.221 X-Article-Creation-Date: Tue Jan 23 11:37:11 2001 GMT X-Http-User-Agent: Mozilla/4.74 [en] (X11; U; Linux 2.3.99-pre1 i686) X-Http-Proxy: 1.0 x59.deja.com:80 (Squid/1.1.22) for client 141.2.84.221 X-MyDeja-Info: XMYDJUIDsulimma Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-ulm.de!rz.uni-karlsruhe.de!blackbush.xlink.net!netnews.web.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4073 Does anybody know, where I can find documentation about using hard macros created with the FPGA editor of Xilinx foundation software a) In a schematic b) In a VHDL design Thanx, Kolja Sent via Deja.com http://www.deja.com/ ###### From: mrandelzhofer@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Foundation FPGA Editor hard macros in VHDL Date: Fri, 26 Jan 2001 07:04:22 GMT Organization: Deja.com Lines: 66 Message-ID: <94r7hl$2pn$1@nnrp1.deja.com> References: <94jqd7$ilp$1@nnrp1.deja.com> NNTP-Posting-Host: 63.59.176.213 X-Article-Creation-Date: Fri Jan 26 07:04:22 2001 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 4.01; Windows 98) X-Http-Proxy: 1.1 x68.deja.com:80 (Squid/1.1.22) for client 63.59.176.213 X-MyDeja-Info: XMYDJUIDmrandelzhofer Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4181 this is quite an interesting issue, wonder why nobody else is familiar with hardmacros. maybe some simple tasks would become much more easier or faster. I loved the old xact 6.xx fpga editor, which was originally better than the neocad editor. our team has done lots of successful xc3000/xc4003 designs just at the chip level. of course this was done mainly because of the lack of fpga resources and the need for speed. now xilinx enhanced the fpga editor, and i'd like to experience some small virtex designs just in the lowest design level. (No doubt, the high level design strategy is the more efficient way for higher integrated devices). here are some of my assumptions on hardmacros: - I think the xilinx pci cores (and maybe others) uses hard-macros heavily. - all the device specific stuff can be used, or used easier as in any hdl. - you get the highest speed and area optimization out of the logic - they are only useful for the fpga family they are designed for, and only for one special size of fpga - good for ip-property protection - only used by the hardliners, a hardmacro can take lots of time and know how - its the only way to access the special virtex trdy/irdy logic ? interesting question is also if there can be prerouted nets. if not, the usage of rlocs, muxcy's, xorcy's and clbmaps etc. should do the same. but this isn't supportet by all the vhdl/verilog compilers isn't it ? Most of my new designs are foundation express vhdl, max clock is about 50MHz in spartan2, and i'm basically not really forced to use subsubleveldesign. but e.g. if you want access to all of the carry outputs of an alu in vhdl, you can spend hours or days to find a solution. this maybe could be done simpler at the lowest chip-level (with the xb and yb outputs of the virtexclb's). also for testing in the lab, its often helpful to know everything about the fpga-editor, so you don't need to recompile the design. an appnote about all these fpga pip, net, block, etc hackings would be great ! In article <94jqd7$ilp$1@nnrp1.deja.com>, sulimma@my-deja.com wrote: > Does anybody know, where I can find documentation about > using hard macros created with the FPGA editor of Xilinx > foundation software > > a) In a schematic > b) In a VHDL design > > Thanx, > Kolja > > Sent via Deja.com > http://www.deja.com/ > Sent via Deja.com http://www.deja.com/ ###### From: kolja@prowokulta.org Newsgroups: comp.arch.fpga Subject: Re: Foundation FPGA Editor hard macros in VHDL Date: Fri, 26 Jan 2001 10:08:36 GMT Organization: Deja.com Lines: 52 Message-ID: <94rib1$bdf$1@nnrp1.deja.com> References: <94jqd7$ilp$1@nnrp1.deja.com> <94r7hl$2pn$1@nnrp1.deja.com> NNTP-Posting-Host: 141.2.84.221 X-Article-Creation-Date: Fri Jan 26 10:08:36 2001 GMT X-Http-User-Agent: Mozilla/4.74 [en] (X11; U; Linux 2.3.99-pre1 i686) X-Http-Proxy: 1.0 x64.deja.com:80 (Squid/1.1.22) for client 141.2.84.221 X-MyDeja-Info: XMYDJUIDsulimma Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeeds.belnet.be!news.belnet.be!sunqbc.risq.qc.ca!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:4183 The FPGA editor documentation is OK, and I get along with the editor very well, but the documentation that I found only explains how to use the FPGAEditor macros in FPGAEditor design. In the old days you coudl just instanciate .NMC macros in XNF files. XNF is not supported any longer, but I guess something like this is still possible. However, I could not find documentation on - In which directory should the NMC file be placed to be used in a VHDL design? - Do I need to use any special library or can I just instanciate them? - Can I make my NMC macro show up in the library manager to create a symbol for it? I need to control the routing of a very small part of my design, and the FPGA Editor seems easier to use then JBits which would obviously solve the problem. Any help is appriciated. Kolja mrandelzhofer@my-deja.com wrote: > our team has done lots of successful xc3000/xc4003 designs just at the > chip level. > - all the device specific stuff can be used, or used easier as in any > hdl. > - you get the highest speed and area optimization out of the logic > - they are only useful for the fpga family they are designed for, and > only for one special size of fpga > - good for ip-property protection > - only used by the hardliners, a hardmacro can take lots of time and > know how > - its the only way to access the special virtex trdy/irdy logic ? > an appnote about all these fpga pip, net, block, etc hackings would be > great ! > > In article <94jqd7$ilp$1@nnrp1.deja.com>, > sulimma@my-deja.com wrote: > > Does anybody know, where I can find documentation about > > using hard macros created with the FPGA editor of Xilinx > > foundation software > > > > a) In a schematic > > b) In a VHDL design Sent via Deja.com http://www.deja.com/ ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Foundation FPGA Editor hard macros in VHDL Date: 26 Jan 2001 23:51:50 +0100 Organization: My own Private Self Lines: 73 Message-ID: <6uofwugc55.fsf@chonsp.franklin.ch> References: <94jqd7$ilp$1@nnrp1.deja.com> <94r7hl$2pn$1@nnrp1.deja.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 980549510 885 10.0.3.2 (26 Jan 2001 22:51:50 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 26 Jan 2001 22:51:50 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:4211 mrandelzhofer@my-deja.com writes: > I loved the old xact 6.xx fpga editor, which was originally better than > the neocad editor. > our team has done lots of successful xc3000/xc4003 designs just at the > chip level. Just like many people did successful programming at assembly language level. HLLs may be faster, but assembly level works. Same HDLs may be faster, but CLB level works. > now xilinx enhanced the fpga editor, and i'd like to experience some > small virtex designs just in the lowest design level. You look like a candidate for JBits, mail jbits@xilinx.com to order (free). Note that this is not an editor, but it is an Java library with an API to modify Virtex (and equivalent size Spartan-II) bitstreams CLB by CLB, feature by feature. That included bitstreams read direct from an powered up but not yet configured chips. So the default interface is Java code, but an graphical display and editor could be written. > (No doubt, the > high level design strategy is the more efficient way for higher > integrated devices). If you are prepared to take work time inefficiecy to experience low level control, you may contemplate taking JBits as base and buidling your ideal Virtex editor on top of it. This could even have an real-time on-line mode, where "open" reads out an chip and "save" writes the modification to an chip. JBits even allows run-time reloading of CLB columns. > - all the device specific stuff can be used, or used easier as in any > hdl. Only if the tool writer adds it. > but e.g. if you want access to all of the carry outputs of an alu in > vhdl, you can spend hours or days to find a solution. A.k.a. rope pushing. > also for testing in the lab, its often helpful to know everything about > the fpga-editor, so you don't need to recompile the design. Just load chip and modify. > an appnote about all these fpga pip, net, block, etc hackings would be > great ! It is in the JBits documentation. Actually just an intro and then an detailled list of all the parameters that can be inserted into the modifying functions. My JBits-docs-derived preliminary/partial CLB surrounding PIPs layout diagram sketch is at: http://neil.franklin.ch/Projects/PDP-10/Virtex-CLB-PIPs (You need an very wide browser window (or scroll horizontally), and an fixed width font for ASCII/plain text) -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic