Message-ID: <3A64DF5E.397E70B9@cs.waikato.ac.nz> From: Dean Armstrong X-Mailer: Mozilla 4.76 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: FPGA driving clock line Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: University of Waikato News Cache Cache-Post-Path: clint.waikato.ac.nz!unknown@trillian.cs.waikato.ac.nz X-Cache: nntpcache 2.3.2.1 (see http://www.nntpcache.org/) Lines: 11 Date: Wed, 17 Jan 2001 12:55:10 +1300 NNTP-Posting-Host: 130.217.64.30 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 979689254 130.217.64.30 (Wed, 17 Jan 2001 12:54:14 NZDT) NNTP-Posting-Date: Wed, 17 Jan 2001 12:54:14 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-ulm.de!rz.uni-karlsruhe.de!blackbush.xlink.net!renate.komtel.net!news.tele.dk!204.94.211.44!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3906 Hi All, Is it possible to drive a clock line for a Spartan II device and three Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. The application is one where I want logic within the main Spartan to select between two different input clocks. To be used for itself and the other devices. Thanks Dean Armstrong ###### Message-ID: <3A64DFBC.A895C809@cs.waikato.ac.nz> From: Dean Armstrong X-Mailer: Mozilla 4.76 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: University of Waikato News Cache Cache-Post-Path: clint.waikato.ac.nz!unknown@trillian.cs.waikato.ac.nz X-Cache: nntpcache 2.3.2.1 (see http://www.nntpcache.org/) Lines: 16 Date: Wed, 17 Jan 2001 12:56:44 +1300 NNTP-Posting-Host: 130.217.64.30 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 979689348 130.217.64.30 (Wed, 17 Jan 2001 12:55:48 NZDT) NNTP-Posting-Date: Wed, 17 Jan 2001 12:55:48 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news.tele.dk!204.94.211.44!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3908 Sorry, I also forgot to mention that this will only be operating at low frequencies (~2MHz). Dean Armstrong wrote: > Hi All, > > Is it possible to drive a clock line for a Spartan II device and three > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > The application is one where I want logic within the main Spartan to > select between two different input clocks. To be used for itself and the > other devices. > > Thanks > Dean Armstrong ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> Subject: Re: FPGA driving clock line Lines: 59 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Wed, 17 Jan 2001 00:14:17 GMT NNTP-Posting-Host: 24.95.236.177 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 979690457 24.95.236.177 (Tue, 16 Jan 2001 19:14:17 EST) NNTP-Posting-Date: Tue, 16 Jan 2001 19:14:17 EST Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news-lei1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!pln-w!extra.newsguy.com!lotsanews.com!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3924 "Dean Armstrong" wrote in message news:3A64DFBC.A895C809@cs.waikato.ac.nz... > Sorry, I also forgot to mention that this will only be operating at low > frequencies (~2MHz). > > Dean Armstrong wrote: > > > Hi All, > > > > Is it possible to drive a clock line for a Spartan II device and three > > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > > The application is one where I want logic within the main Spartan to > > select between two different input clocks. To be used for itself and the > > other devices. > > > > Thanks > > Dean Armstrong Dean, It' hard to determine exactly what you are talking about. Let me see if I have this right. You have two Spartan II devices and three CPLDs. You call one Spartan II device the "main" device, and you want logic on this device to select from two different input clocks for itself as well as the other Spartan II device and three CPLDs. This means that the main Spartan II will have two or more input clocks, and it is going to select the clock and drive itself as well as the other Spartan II and the three CPLDs. I thnk that the following are applicable: 1. You won't have a clock out of main Spartain II until after configuration. It could glitch, too. Can you handle this? 2. The logic selecting the clock is totally combinatorial and not dependent on any of the clocks. 3. You drive the selected clock to a IO pad and distribute the clock to both Spartan IIs and CPLDs. 4. The IO pad will be tristated and weakly pulled high. You might want to pull it high with an external pull up resistor. 5. The clock network will probably have no termination or a mild termination (pullup resistor?) due to the Spartan II 24ma limit. The clock may be 2 MHz, max, but you still have to contend with those edges. 6. You're not too worried about duty cycle. At 2 MHz, I think this would be true. Without having more information to work with, this is what I came up with. It would be nice to know how you are originally generating the clock, as the clock selection can be made there, too. With what you have, though, I would be tempted to select the clocks in the CPLDs, though, because they come right up after power on. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USA ###### Message-ID: <3A64E669.5A49690A@cs.waikato.ac.nz> From: Dean Armstrong X-Mailer: Mozilla 4.76 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: University of Waikato News Cache Cache-Post-Path: clint.waikato.ac.nz!unknown@trillian.cs.waikato.ac.nz X-Cache: nntpcache 2.3.2.1 (see http://www.nntpcache.org/) Lines: 78 Date: Wed, 17 Jan 2001 13:25:13 +1300 NNTP-Posting-Host: 130.217.64.30 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 979691058 130.217.64.30 (Wed, 17 Jan 2001 13:24:18 NZDT) NNTP-Posting-Date: Wed, 17 Jan 2001 13:24:18 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3904 Hi Simon, Thanks for your reply. You understood me correctly. The intention is that one clock source be a crystal oscillator at about 2MHz, the other will be a push button (which will be debounced in programmable logic somewhere). A third input (an on/off switch) will select between the two. This will allow the devices to run on the clock or be switched into a single-step mode. Basically, what I am designing is a computer system that can free-run, or be switched into a mode where the CPU and bus operations are single stepping. Some of these devices (eg UART, programmable timer) will still need the high speed clock to perform their operations correctly, but all bus transactions with them will be single stepped. Thanks, Dean "S. Ramirez" wrote: > "Dean Armstrong" wrote in message > news:3A64DFBC.A895C809@cs.waikato.ac.nz... > > Sorry, I also forgot to mention that this will only be operating at low > > frequencies (~2MHz). > > > > Dean Armstrong wrote: > > > > > Hi All, > > > > > > Is it possible to drive a clock line for a Spartan II device and three > > > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > > > The application is one where I want logic within the main Spartan to > > > select between two different input clocks. To be used for itself and the > > > other devices. > > > > > > Thanks > > > Dean Armstrong > > Dean, > It' hard to determine exactly what you are talking about. Let me see if I > have this right. You have two Spartan II devices and three CPLDs. You call > one Spartan II device the "main" device, and you want logic on this device > to select from two different input clocks for itself as well as the other > Spartan II device and three CPLDs. > > This means that the main Spartan II will have two or more input clocks, and > it is going to select the clock and drive itself as well as the other > Spartan II and the three CPLDs. I thnk that the following are applicable: > 1. You won't have a clock out of main Spartain II > until after configuration. It could glitch, too. > Can you handle this? > 2. The logic selecting the clock is totally combinatorial > and not dependent on any of the clocks. > 3. You drive the selected clock to a IO pad and distribute > the clock to both Spartan IIs and CPLDs. > 4. The IO pad will be tristated and weakly pulled high. > You might want to pull it high with an external pull up > resistor. > 5. The clock network will probably have no termination > or a mild termination (pullup resistor?) due to the > Spartan II 24ma limit. The clock may be 2 MHz, max, > but you still have to contend with those edges. > 6. You're not too worried about duty cycle. At 2 MHz, > I think this would be true. > > Without having more information to work with, this is what I came up with. > It would be nice to know how you are originally generating the clock, as the > clock selection can be made there, too. > > With what you have, though, I would be tempted to select the clocks in the > CPLDs, though, because they come right up after power on. > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line Date: Tue, 16 Jan 2001 17:34:24 -0800 Organization: Xilinx Lines: 139 Message-ID: <3A64F69F.99FAE9CC@xilinx.com> References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="------------68EC4BA62900476F802CF76A" X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: "S. Ramirez" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news-lei1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!cyclone.swbell.net!bos-service1.ext.raytheon.com!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3891 --------------68EC4BA62900476F802CF76A Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit There seem to be three issues here: 1 Does Spartan have enough drive to supply clocks to several chips? Answer: yes, no problem 2 What happens during configuration? Answer: Outputs are 3-stated, and internal logic is being held reset. Output will be glitch-free if the user keeps it 3-stated until the clock multiplexer is running properly. May take another internal flip-flop. But they are cheap. 3 How can I mux asynchronous clocks reliably, without glitches and runt output pulses? Answer: click on http://www.xilinx.com/xcell/xl24/xl24_20.pdf Peter Alfke, Xilinx Applications ======================= "S. Ramirez" wrote: > "Dean, > It' hard to determine exactly what you are talking about. Let me see if I > have this right. You have two Spartan II devices and three CPLDs. You call > one Spartan II device the "main" device, and you want logic on this device > to select from two different input clocks for itself as well as the other > Spartan II device and three CPLDs. > > This means that the main Spartan II will have two or more input clocks, and > it is going to select the clock and drive itself as well as the other > Spartan II and the three CPLDs. I thnk that the following are applicable: > 1. You won't have a clock out of main Spartain II > until after configuration. It could glitch, too. > Can you handle this? > 2. The logic selecting the clock is totally combinatorial > and not dependent on any of the clocks. > 3. You drive the selected clock to a IO pad and distribute > the clock to both Spartan IIs and CPLDs. > 4. The IO pad will be tristated and weakly pulled high. > You might want to pull it high with an external pull up > resistor. > 5. The clock network will probably have no termination > or a mild termination (pullup resistor?) due to the > Spartan II 24ma limit. The clock may be 2 MHz, max, > but you still have to contend with those edges. > 6. You're not too worried about duty cycle. At 2 MHz, > I think this would be true. > > Without having more information to work with, this is what I came up with. > It would be nice to know how you are originally generating the clock, as the > clock selection can be made there, too. > > With what you have, though, I would be tempted to select the clocks in the > CPLDs, though, because they come right up after power on. > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA --------------68EC4BA62900476F802CF76A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit There seem to be three issues here:
1
Does  Spartan have enough drive to supply clocks to several chips?
Answer: yes, no problem
2
What happens during configuration?
Answer: Outputs are 3-stated, and internal logic is being held reset. Output will be glitch-free if the user keeps it 3-stated until the clock multiplexer is running properly. May take another internal flip-flop. But they are cheap.
3
How can I mux asynchronous clocks reliably, without glitches and runt output pulses?
Answer: click on
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

Peter Alfke, Xilinx Applications
=======================
"S. Ramirez" wrote:

"Dean,
It' hard to determine exactly what you are talking about.  Let me see if I
have this right.  You have two Spartan II devices and three CPLDs.  You call
one Spartan II device the "main" device, and you want logic on this device
to select from two different input clocks for itself as well as the other
Spartan II device and three CPLDs.

This means that the main Spartan II will have two or more input clocks, and
it is going to select the clock and drive itself as well as the other
Spartan II and the three CPLDs.  I thnk that the following are applicable:
   1.  You won't have a clock out of main Spartain II
         until after configuration.  It could glitch, too.
         Can you handle this?
   2.  The logic selecting the clock is totally combinatorial
        and not dependent on any of the clocks.
  3.  You drive the selected clock to a IO pad and distribute
        the clock to both Spartan IIs and CPLDs.
  4.  The IO pad will be tristated and weakly pulled high.
       You might want to pull it high with an external pull up
        resistor.
  5.  The clock network will probably have no termination
       or a mild termination (pullup resistor?) due to the
       Spartan II 24ma limit.  The clock may be 2 MHz, max,
       but you still have to contend with those edges.
  6.  You're not too worried about duty cycle.  At 2 MHz,
        I think this would be true.

Without having more information to work with, this is what I came up with.
It would be nice to know how you are originally generating the clock, as the
clock selection can be made there, too.

With what you have, though, I would be tempted to select the clocks in the
CPLDs, though, because they come right up after power on.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA

--------------68EC4BA62900476F802CF76A-- ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line Date: Tue, 16 Jan 2001 17:48:22 -0800 Organization: Xilinx Lines: 91 Message-ID: <3A64F9E5.AA245718@xilinx.com> References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> <3A64E669.5A49690A@cs.waikato.ac.nz> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: Dean Armstrong Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news.augsburg.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!cyclone.swbell.net!bos-service1.ext.raytheon.com!attla1!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3882 Dean, now that you let us in on your real plans, let me give some advice: Do not source two different clocks, but rather build a simple internal switch differentiator and gate the clock for one period. Better yet, let the clock run freely, and use the FPGA to create a one-clock-period Enable signal when you want to single step. Driven by a simple state machine in less than one CLB, this is the solution that will give you the least trouble ( none at all) Peter Alfke =========================== Dean Armstrong wrote: > Hi Simon, > > Thanks for your reply. > > You understood me correctly. > > The intention is that one clock source be a crystal oscillator at about 2MHz, > the other will be a push button (which will be debounced in programmable logic > somewhere). A third input (an on/off switch) will select between the two. This > will allow the devices to run on the clock or be switched into a single-step > mode. > > Basically, what I am designing is a computer system that can free-run, or be > switched into a mode where the CPU and bus operations are single stepping. Some > of these devices (eg UART, programmable timer) will still need the high speed > clock to perform their operations correctly, but all bus transactions with them > will be single stepped. > > Thanks, > Dean > > "S. Ramirez" wrote: > > > "Dean Armstrong" wrote in message > > news:3A64DFBC.A895C809@cs.waikato.ac.nz... > > > Sorry, I also forgot to mention that this will only be operating at low > > > frequencies (~2MHz). > > > > > > Dean Armstrong wrote: > > > > > > > Hi All, > > > > > > > > Is it possible to drive a clock line for a Spartan II device and three > > > > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > > > > The application is one where I want logic within the main Spartan to > > > > select between two different input clocks. To be used for itself and the > > > > other devices. > > > > > > > > Thanks > > > > Dean Armstrong > > > > Dean, > > It' hard to determine exactly what you are talking about. Let me see if I > > have this right. You have two Spartan II devices and three CPLDs. You call > > one Spartan II device the "main" device, and you want logic on this device > > to select from two different input clocks for itself as well as the other > > Spartan II device and three CPLDs. > > > > This means that the main Spartan II will have two or more input clocks, and > > it is going to select the clock and drive itself as well as the other > > Spartan II and the three CPLDs. I thnk that the following are applicable: > > 1. You won't have a clock out of main Spartain II > > until after configuration. It could glitch, too. > > Can you handle this? > > 2. The logic selecting the clock is totally combinatorial > > and not dependent on any of the clocks. > > 3. You drive the selected clock to a IO pad and distribute > > the clock to both Spartan IIs and CPLDs. > > 4. The IO pad will be tristated and weakly pulled high. > > You might want to pull it high with an external pull up > > resistor. > > 5. The clock network will probably have no termination > > or a mild termination (pullup resistor?) due to the > > Spartan II 24ma limit. The clock may be 2 MHz, max, > > but you still have to contend with those edges. > > 6. You're not too worried about duty cycle. At 2 MHz, > > I think this would be true. > > > > Without having more information to work with, this is what I came up with. > > It would be nice to know how you are originally generating the clock, as the > > clock selection can be made there, too. > > > > With what you have, though, I would be tempted to select the clocks in the > > CPLDs, though, because they come right up after power on. > > Simon Ramirez, Consultant > > Synchronous Design, Inc. > > Oviedo, FL USA ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> <3A64E669.5A49690A@cs.waikato.ac.nz> Subject: Re: FPGA driving clock line Lines: 40 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Wed, 17 Jan 2001 02:16:49 GMT NNTP-Posting-Host: 24.95.236.177 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 979697809 24.95.236.177 (Tue, 16 Jan 2001 21:16:49 EST) NNTP-Posting-Date: Tue, 16 Jan 2001 21:16:49 EST Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-koe1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.primenet.com!nntp.gblx.net!pln-w!extra.newsguy.com!lotsanews.com!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3923 "Dean Armstrong" wrote in message news:3A64E669.5A49690A@cs.waikato.ac.nz... > Hi Simon, > > Thanks for your reply. > > You understood me correctly. > > The intention is that one clock source be a crystal oscillator at about 2MHz, > the other will be a push button (which will be debounced in programmable logic > somewhere). A third input (an on/off switch) will select between the two. This > will allow the devices to run on the clock or be switched into a single-step > mode. > > Basically, what I am designing is a computer system that can free-run, or be > switched into a mode where the CPU and bus operations are single stepping. Some > of these devices (eg UART, programmable timer) will still need the high speed > clock to perform their operations correctly, but all bus transactions with them > will be single stepped. > > Thanks, > Dean Good luck, Dean. What you are doing sounds relatively simple, yet you can be stepping on some mines here. I would make sure to use an excellent debounce circuit as well as verify that all components running on the slow push button frequency can go to 0 Hz. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USA ###### From: murray@pa.dec.com (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line Date: 17 Jan 2001 05:56:49 GMT Organization: Compaq Systems Research Center Lines: 30 Distribution: world Message-ID: <943c71$nd0@src-news.pa.dec.com> References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> NNTP-Posting-Host: quatre.pa.dec.com X-Newsreader: xrn 9.01 Originator: murray@quatre.pa.dec.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news.f.de.plusline.net!news.netcologne.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!paloalto-snf1.gtei.net!news.gtei.net!newsgate.tandem.com!mailint03.im.hou.compaq.com!pa.dec.com!src.dec.com!murray Xref: chonsp.franklin.ch comp.arch.fpga:3903 > Is it possible to drive a clock line for a Spartan II device and three > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > The application is one where I want logic within the main Spartan to > select between two different input clocks. To be used for itself and the > other devices. I think there are two issues here. The first is generating a clock from a Spartan. The second is making right logic inside a Spartan to cleanly switch between clocks. I don't know of any special problems with generating a clock on a Spartan - just the standard problems of rise time, reflections, and skew. If you have enough pins, I'd suggest one pin per clock and series terminate. Cleanly switching clocks seems as though it should be a standard problem. But I don't remember seening an example. My straw man would be a small FSM with 3 states - clock1, clock2, idle. When you want to switch, you go from clock1 to idle using logic clocked by clock1. Then you run the idle signal through a synchronizer and go to the clock2 state ising logic clocked by clock2. Another msg said the second clock was just to get single-stepping on some logic. In that case, you might leave the clock running all the time and just use a clock-enable for the logic that needs it. -- These are my opinions, not necessarily my employers. I hate spam. ###### Message-ID: <3A65EED1.CAF46946@cs.waikato.ac.nz> From: Dean Armstrong X-Mailer: Mozilla 4.76 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: University of Waikato News Cache Cache-Post-Path: clint.waikato.ac.nz!unknown@trillian.cs.waikato.ac.nz X-Cache: nntpcache 2.3.2.1 (see http://www.nntpcache.org/) Lines: 21 Date: Thu, 18 Jan 2001 08:13:21 +1300 NNTP-Posting-Host: 130.217.64.30 X-Complaints-To: newsadmin@xtra.co.nz X-Trace: news.xtra.co.nz 979758745 130.217.64.30 (Thu, 18 Jan 2001 08:12:25 NZDT) NNTP-Posting-Date: Thu, 18 Jan 2001 08:12:25 NZDT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news.tele.dk!204.94.211.44!enews.sgi.com!news.xtra.co.nz!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3907 Hi, Thanks for all the help guys. I think having a clock enable seems to be the best bet, so I'll try that. Regards, Dean Armstrong Dean Armstrong wrote: > Hi All, > > Is it possible to drive a clock line for a Spartan II device and three > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II. > The application is one where I want logic within the main Spartan to > select between two different input clocks. To be used for itself and the > other devices. > > Thanks > Dean Armstrong ###### From: murray@pa.dec.com (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: FPGA driving clock line Date: 19 Jan 2001 04:34:07 GMT Organization: Compaq Systems Research Center Lines: 23 Distribution: world Message-ID: <948g3v$792@src-news.pa.dec.com> References: <3A64DF5E.397E70B9@cs.waikato.ac.nz> <3A64DFBC.A895C809@cs.waikato.ac.nz> <3A64E669.5A49690A@cs.waikato.ac.nz> <3A64F9E5.AA245718@xilinx.com> NNTP-Posting-Host: quatre.pa.dec.com X-Newsreader: xrn 9.01 Originator: murray@quatre.pa.dec.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!paloalto-snf1.gtei.net!news.gtei.net!newsgate.tandem.com!mailint03.im.hou.compaq.com!pa.dec.com!src.dec.com!murray Xref: chonsp.franklin.ch comp.arch.fpga:3975 > Better yet, let the clock run freely, and use the FPGA to create a > one-clock-period Enable signal when you want to single step. Driven by a simple > state machine in less than one CLB, this is the solution that will give you the > least trouble ( none at all) The disadvantage that I see with a traditional Enable signal is that you have to route it all over the place and the enable logic is often very handy for other things. Here is a suggestion that might avoid that. Start with a 2x clock. Generate the working clock with a FF. Put the enable on that FF. You can do the same thing with a 1x clock and appropriate gates but that depends upon prop times so you will have to work a bit to get it right and convince yourself it is correct. -- These are my opinions, not necessarily my employers. I hate spam.