Newsgroups: comp.arch.fpga From: Lawrence Peregrim Subject: Virtex counter speed Sender: news@world.std.com (Mr Usenet Himself) Message-ID: <3A5F8CD5.7BAEAA6F@nospam.ksa1.com> Date: Fri, 12 Jan 2001 23:01:41 GMT Content-Transfer-Encoding: 7bit X-Accept-Language: en Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: ppp0b001.std.com Mime-Version: 1.0 X-Mailer: Mozilla 4.73 [en] (WinNT; U) Organization: Kalman Saffran Associates, Inc. Lines: 10 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.cwix.com!news.umass.edu!world!news Xref: chonsp.franklin.ch comp.arch.fpga:3799 What's the fastest binary up-counter speed that can be wrung from a speed grade 6 Virtex? I need to emulate a few ASIC counters (one 16 bit and one 32 bit) that are presently implemented with simple chained toggle flops. These counters have async. clear only, no load/preset. Before getting to the post P&R sims and after looking at Xilinx literature, it looks like I should expect around 100 MHz. I'm looking to use the secondary interconnect lines. TIA Lawrence ###### Message-ID: <3A5FAB55.3143FA74@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Virtex counter speed References: <3A5F8CD5.7BAEAA6F@nospam.ksa1.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 Date: Sat, 13 Jan 2001 01:08:49 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 979348129 24.13.238.93 (Fri, 12 Jan 2001 17:08:49 PST) NNTP-Posting-Date: Fri, 12 Jan 2001 17:08:49 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3794 Depends! (gotta love that answer) If you can live with a ripple counter, for example, the speeds can be more than 500MHz. But then you have to deal with non-synchronous outputs. For synchronous binary counters the carry chain limits non-pipelined performance. For 16 bits in a -6, you can get about 195 MHz, but you need to be careful about fan-in on any controls. For a free running counter, the automatic tool flow should get you pretty close to that. As soon as you add controls, you'll need to be careful about fan-in and implementation to get it. You'll need to play some tricks with the 32 bit such as pipelining the carry to get the 32 bit counter running near the same rate. That said, 100 MHz is a pretty easy to hit target for a -6. I've been doing 100+ MHz DSP designs with 16-24 bit carry chains in virtex -4's. Lawrence Peregrim wrote: > > What's the fastest binary up-counter speed that can be wrung from a > speed grade 6 Virtex? I need to emulate a few ASIC counters (one 16 > bit and one 32 bit) that are presently implemented with simple chained > toggle flops. These counters have async. clear only, no load/preset. > Before getting to the post P&R sims and after looking at Xilinx literature, > it looks like I should expect around 100 MHz. I'm looking to use the > secondary interconnect lines. > > TIA > Lawrence -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: "Kevin Neilson" Newsgroups: comp.arch.fpga References: <3A5F8CD5.7BAEAA6F@nospam.ksa1.com> <3A5FAB55.3143FA74@andraka.com> Subject: Re: Virtex counter speed Lines: 80 X-Newsreader: Microsoft Outlook Express 4.72.3110.5 X-MimeOLE: Produced By Microsoft MimeOLE V4.72.3110.3 Message-ID: Date: Sat, 13 Jan 2001 02:32:17 GMT NNTP-Posting-Host: 209.245.8.68 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 979353137 209.245.8.68 (Fri, 12 Jan 2001 18:32:17 PST) NNTP-Posting-Date: Fri, 12 Jan 2001 18:32:17 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!merapi!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.skycache.com!Cidera!news-out.usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3796 I'm going to preach about Johnson rings again. If you don't mind using quite a few flops, you can make much faster fully synchronous counters using Johnson ring shift registers. A ring is the fastest possible synchronous structure, because it's just a series of flops with Qs connected to Ds. Such a ring should run with a period of clk->q + setup_time + routing time, which seems like it would be under 2ns (500MHz) in Virtex -6, although the maximum toggle frequency is listed at 333MHz, or period 3ns. (Not sure what that means.) Here's how to do it: the LSB of the counter is the lsb of a 2-flop ring intialized with "10". You can see that the lsb of the ring will alternate between 0 and 1. The next bit of the coutner is the lsb of a 4-flop ring initialized with "1100". Next bit is the lsb of an 8-flop ring initialized with "11110000", and bit3 is the lsb of the ring initialized with "1111111100000000". There is also a ring initialized with "1000000000000000"; the lsb of this bit (which must be replicated to reduce fanout) is used as a clock enable for the rest of the counter. This 4-bit counter is a kind of a fast prescaler. For a 32-bit counter, attach this 4-bit counter to a 28-bit conventional counter, and use the clock enable bit from the clock enable Johnson ring to enable it. Because the 28-bit conventional counter is only enabled every 16th cycle, it is constrained as a 16-cycle path and its carry chain is removed from the critical path. The carry has 16 cycles to propagate. The critical path now is from one Q in the ring to the next D in the ring. This 32-bit counter takes 75 flops, but runs synchronously at at fantastic speeds. You can do a 64-bit counter at the same speed. I Actually, for a 32-bit counter, you probably just need a 3-bit prescaler, so you'd only need 52 flops. -Kevin, IDS Ray Andraka wrote in message <3A5FAB55.3143FA74@andraka.com>... >Depends! (gotta love that answer) > >If you can live with a ripple counter, for example, the speeds can be more than >500MHz. But then you have to deal with non-synchronous outputs. For >synchronous binary counters the carry chain limits non-pipelined performance. >For 16 bits in a -6, you can get about 195 MHz, but you need to be careful about >fan-in on any controls. For a free running counter, the automatic tool flow >should get you pretty close to that. As soon as you add controls, you'll need >to be careful about fan-in and implementation to get it. You'll need to play >some tricks with the 32 bit such as pipelining the carry to get the 32 bit >counter running near the same rate. That said, 100 MHz is a pretty easy to hit >target for a -6. I've been doing 100+ MHz DSP designs with 16-24 bit carry >chains in virtex -4's. > >Lawrence Peregrim wrote: >> >> What's the fastest binary up-counter speed that can be wrung from a >> speed grade 6 Virtex? I need to emulate a few ASIC counters (one 16 >> bit and one 32 bit) that are presently implemented with simple chained >> toggle flops. These counters have async. clear only, no load/preset. >> Before getting to the post P&R sims and after looking at Xilinx literature, >> it looks like I should expect around 100 MHz. I'm looking to use the >> secondary interconnect lines. >> >> TIA >> Lawrence > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com or http://www.fpga-guru.com