From: "Mikhail Matusov" Newsgroups: comp.arch.fpga Subject: Fixing pins on Spartan II Lines: 26 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2314.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2314.1300 Message-ID: Date: Wed, 03 Jan 2001 20:17:53 GMT NNTP-Posting-Host: 209.217.118.78 X-Trace: news 978553073 209.217.118.78 (Wed, 03 Jan 2001 15:17:53 EST) NNTP-Posting-Date: Wed, 03 Jan 2001 15:17:53 EST Organization: Magma Communications Ltd. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!news1.tor.metronet.ca!nntp.magma.ca!news!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3668 Hi all, Egg-chicken kind of problem. I have to give my board design out to a layout person but I haven't yet had chance to start my FPGA work. Usually I do some draft FPGA design and run tools at least once to fix the pins before giving it out to do a layout but this time the schedule is really tight and if I go this route it will be too late. This is not a very demanding design neither in terms of complexity nor in terms of speed and I am using Spartan II family device. Scary part is that the pins utilization is almost 100%. Nonetheless, do you guys think that I can get away with pins fixed beforehand without too much thought (I put my clocks on global clock lines)? Thanks in advance, -- ============================ Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: 1 (613) 271-0044 ext.231 Fax: 1 (613) 271-3007 http://www.squarepeg.ca ###### Message-ID: <3A53AE65.6FAB609E@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 50 Date: Wed, 03 Jan 2001 22:55:03 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 978562503 24.13.238.93 (Wed, 03 Jan 2001 14:55:03 PST) NNTP-Posting-Date: Wed, 03 Jan 2001 14:55:03 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news.uni-ulm.de!rz.uni-karlsruhe.de!blackbush.xlink.net!howland.erols.net!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3620 You can assign your pins before the design is done, but you should apply at least a little thought to make success more likely. Some points to ponder: Try to register all the I/O in the design at the IOB. That isolates the internal timing from the external timing, and makes it more likely to get a design to work. The routing in the the Spartan II is more plentiful than the older 4K/spartan family, so a poor pin placement is not nearly as likely to give you a no-route than it had been previously. Some simple things can reduce the routing congestion greatly and accelerate the place and route times. FIrst, if it is a data flow design that will be using the carry chains, run your data across the chip (as viewed in the floorplanner) with the LSBs at the bottom to line up with the carry chain direction. If you have signals that go in and then back out iwth no or only one registers, then those should be placed nearby to keep the routing delays minimum. Mikhail Matusov wrote: > > Hi all, > > Egg-chicken kind of problem. I have to give my board design out to a layout > person but I haven't yet had chance to start my FPGA work. Usually I do some > draft FPGA design and run tools at least once to fix the pins before giving > it out to do a layout but this time the schedule is really tight and if I go > this route it will be too late. This is not a very demanding design neither > in terms of complexity nor in terms of speed and I am using Spartan II > family device. Scary part is that the pins utilization is almost 100%. > > Nonetheless, do you guys think that I can get away with pins fixed > beforehand without too much thought (I put my clocks on global clock lines)? > > Thanks in advance, > > -- > ============================ > Mikhail Matusov > Hardware Design Engineer > Square Peg Communications > Tel.: 1 (613) 271-0044 ext.231 > Fax: 1 (613) 271-3007 > http://www.squarepeg.ca -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: John Larkin Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II Message-ID: References: X-Newsreader: Forte Agent 1.6/32.525 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Wed, 03 Jan 2001 17:47:58 -0800 NNTP-Posting-Host: 204.182.55.6 X-Complaints-To: news@rmi.net X-Trace: den-news1.rmi.net 978572671 204.182.55.6 (Wed, 03 Jan 2001 18:44:31 MST) NNTP-Posting-Date: Wed, 03 Jan 2001 18:44:31 MST Organization: RMI.NET Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.cwix.com!natasha.rmii.com!den-news1.rmi.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3661 On Wed, 03 Jan 2001 20:17:53 GMT, "Mikhail Matusov" wrote: >Hi all, > >Egg-chicken kind of problem. I have to give my board design out to a layout >person but I haven't yet had chance to start my FPGA work. Usually I do some >draft FPGA design and run tools at least once to fix the pins before giving >it out to do a layout but this time the schedule is really tight and if I go >this route it will be too late. This is not a very demanding design neither >in terms of complexity nor in terms of speed and I am using Spartan II >family device. Scary part is that the pins utilization is almost 100%. > >Nonetheless, do you guys think that I can get away with pins fixed >beforehand without too much thought (I put my clocks on global clock lines)? > > >Thanks in advance, Mikhail, we always preassign pins so that we can do the PCB layout and the FPGA design concurrently. We try to pick a signal flow pattern that makes the PCB layout easy and seems to make FPGA routing happy, or at least make a rough guess at it. Seems to work. John ###### Message-ID: <3A55D04A.C3890567@ics-ltd.com> From: Jakab Tanko X-Mailer: Mozilla 4.5 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Fri, 05 Jan 2001 13:41:41 GMT NNTP-Posting-Host: 206.191.16.10 X-Trace: news 978702101 206.191.16.10 (Fri, 05 Jan 2001 08:41:41 EST) NNTP-Posting-Date: Fri, 05 Jan 2001 08:41:41 EST Organization: Magma Communications Ltd. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!news1.tor.metronet.ca!nntp.magma.ca!news!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3609 NO, pins are better left to be picked by the place&route tool. At minimum I think you should put together a dummy design, if you don't have time for a detailed one, do a quick place and route and go with that. As for the pins 100% is 20% to many used pins, I would select a larger device or different package to get more I/O pins. This is of course just my opinion and I could be wrong, jakab Mikhail Matusov wrote: > Hi all, > > Egg-chicken kind of problem. I have to give my board design out to a layout > person but I haven't yet had chance to start my FPGA work. Usually I do some > draft FPGA design and run tools at least once to fix the pins before giving > it out to do a layout but this time the schedule is really tight and if I go > this route it will be too late. This is not a very demanding design neither > in terms of complexity nor in terms of speed and I am using Spartan II > family device. Scary part is that the pins utilization is almost 100%. > > Nonetheless, do you guys think that I can get away with pins fixed > beforehand without too much thought (I put my clocks on global clock lines)? > > Thanks in advance, > > -- > ============================ > Mikhail Matusov > Hardware Design Engineer > Square Peg Communications > Tel.: 1 (613) 271-0044 ext.231 > Fax: 1 (613) 271-3007 > http://www.squarepeg.ca ###### Message-ID: <3A561198.29529BAB@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: <3A55D04A.C3890567@ics-ltd.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 56 Date: Fri, 05 Jan 2001 18:22:45 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 978718965 24.13.238.93 (Fri, 05 Jan 2001 10:22:45 PST) NNTP-Posting-Date: Fri, 05 Jan 2001 10:22:45 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3615 NO! There are a few things the automatic placement is exceptionally poor at, with pin placement leading the list, followed by tbuf placement, and data-path placement. You should always specify the pin placement rather than letting the tools do it. Even a bad guess is likely to be better than the random placement generated by the tools, especially if you start itrating a design. See earlier posts in this thread for some guidelines on assigning pins. As for number of pins used, 100% is not a problem...most of the designs I touch have 100% of the pins defined. The only time 100% pin utilization becomes a problem is when you let the tools do the assigning! Jakab Tanko wrote: > > NO, pins are better left to be picked by the place&route tool. > At minimum I think you should put together a dummy design, > if you don't have time for a detailed one, do a quick place and route > and go with that. As for the pins 100% is 20% to many used pins, I > would select a larger device or different package to get more I/O pins. > This is of course just my opinion and I could be wrong, > > jakab > > Mikhail Matusov wrote: > > > Hi all, > > > > Egg-chicken kind of problem. I have to give my board design out to a layout > > person but I haven't yet had chance to start my FPGA work. Usually I do some > > draft FPGA design and run tools at least once to fix the pins before giving > > it out to do a layout but this time the schedule is really tight and if I go > > this route it will be too late. This is not a very demanding design neither > > in terms of complexity nor in terms of speed and I am using Spartan II > > family device. Scary part is that the pins utilization is almost 100%. > > > > Nonetheless, do you guys think that I can get away with pins fixed > > beforehand without too much thought (I put my clocks on global clock lines)? > > > > Thanks in advance, > > > > -- > > ============================ > > Mikhail Matusov > > Hardware Design Engineer > > Square Peg Communications > > Tel.: 1 (613) 271-0044 ext.231 > > Fax: 1 (613) 271-3007 > > http://www.squarepeg.ca -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### Message-ID: <3A56387C.7000404@ics-ltd.com> From: Jakab Tanko User-Agent: Mozilla/5.0 (Windows; U; WinNT4.0; en-US; m18) Gecko/20001108 Netscape6/6.0 X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: <3A55D04A.C3890567@ics-ltd.com> <3A561198.29529BAB@andraka.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Lines: 68 Date: Fri, 05 Jan 2001 21:06:14 GMT NNTP-Posting-Host: 206.191.16.10 X-Trace: news 978728774 206.191.16.10 (Fri, 05 Jan 2001 16:06:14 EST) NNTP-Posting-Date: Fri, 05 Jan 2001 16:06:14 EST Organization: Magma Communications Ltd. Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!news1.tor.metronet.ca!nntp.magma.ca!news!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3603 Yes,No,Maybe, If you assign 100% the I/O pins that is plain bad design practice in my opinion, just consider what happens if you need an extra pin afterwards; As for the automatic pin placement it works fine except when you have one of those designs "from hell" (about 5% of all designs) that require extensive floor planing just to get the thing to work. In that case the wrong part was selected for the application or your project deadlines are different from mine because I never have time for doing the job of the P&R tool ....... Ray Andraka wrote: > NO! > > There are a few things the automatic placement is exceptionally poor at, with > pin placement leading the list, followed by tbuf placement, and data-path > placement. You should always specify the pin placement rather than letting the > tools do it. Even a bad guess is likely to be better than the random placement > generated by the tools, especially if you start itrating a design. See earlier > posts in this thread for some guidelines on assigning pins. > > As for number of pins used, 100% is not a problem...most of the designs I touch > have 100% of the pins defined. The only time 100% pin utilization becomes a > problem is when you let the tools do the assigning! > > Jakab Tanko wrote: > >> NO, pins are better left to be picked by the place&route tool. >> At minimum I think you should put together a dummy design, >> if you don't have time for a detailed one, do a quick place and route >> and go with that. As for the pins 100% is 20% to many used pins, I >> would select a larger device or different package to get more I/O pins. >> This is of course just my opinion and I could be wrong, >> >> jakab >> >> Mikhail Matusov wrote: >> >>> Hi all, >>> >>> Egg-chicken kind of problem. I have to give my board design out to a layout >>> person but I haven't yet had chance to start my FPGA work. Usually I do some >>> draft FPGA design and run tools at least once to fix the pins before giving >>> it out to do a layout but this time the schedule is really tight and if I go >>> this route it will be too late. This is not a very demanding design neither >>> in terms of complexity nor in terms of speed and I am using Spartan II >>> family device. Scary part is that the pins utilization is almost 100%. >>> >>> Nonetheless, do you guys think that I can get away with pins fixed >>> beforehand without too much thought (I put my clocks on global clock lines)? >>> >>> Thanks in advance, >>> >>> -- >>> ============================ >>> Mikhail Matusov >>> Hardware Design Engineer >>> Square Peg Communications >>> Tel.: 1 (613) 271-0044 ext.231 >>> Fax: 1 (613) 271-3007 >>> http://www.squarepeg.ca >> ###### Message-ID: <3A5645E1.7E3E54FD@aracnet.com> From: eteam Reply-To: eteam@aracnet.com Organization: The E-Team X-Mailer: Mozilla 4.73 [en] (Windows NT 5.0; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: <3A55D04A.C3890567@ics-ltd.com> <3A561198.29529BAB@andraka.com> <3A56387C.7000404@ics-ltd.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 77 Date: Fri, 05 Jan 2001 14:08:33 -0800 NNTP-Posting-Host: 198.102.179.71 X-Complaints-To: news@aracnet.com X-Trace: typhoon.aracnet.com 978732509 198.102.179.71 (Fri, 05 Jan 2001 14:08:29 PST) NNTP-Posting-Date: Fri, 05 Jan 2001 14:08:29 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!feed.textport.net!typhoon.aracnet.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3621 I agree with Ray. Ray isn't telling anyone to use 100% of the pins, or to *not* provide for any spare/unused pins, or to use 100% of the CLBs/PFUs/LCs... he *is* saying it's a good idea to lock down all pins, used and unused/spare pins alike. So Jakab, you're right, and Ray's not wrong... (did I say that correctly?) The compiler (placement tool) is completely ignorant of the board-level layout or electrical considerations. The designer needs to provide that intelligence. Every "unused" pin should be declared, locked down, and represented on any board-level schematic. In essence, there are no "unused" pins, just "spare" pins that don't yet have a function assigned to them. On many "new" designs, there will be *some* use made of some of the spare pins. Designers are, sadly, all too human. So while we're specifying pinout of all the "used" pins, depending upon the package being used, it is a good idea to A. route some spare pins to square pins or vias, for either probing or hookup of new signals and/or B. assign some of those spare pins to corner pins (e.g. pins 1,52,53,...208 of a PQ208) so that soldering 30AWG wire to the pins by the board assembler has a chance of success. I do not apologize for specifying the pinout before the FPGA is fully implemented, getting the board into layout, and then finishing the FPGA implementation while the layout/fab/assembly is proceeding. It takes some experience (and learning the hard way) to do this and come out smelling like a rose, but that's why we get paid the big bucks. It also helps to oversize the FPGA, using a footprint-compatible device, but that just buys gates and routing resources, not extra pins. So, Ray is right. Jakab is correct that using 100% of all the useable pins is a risky business, but that doesn't contradict what Ray is suggesting, in the slightest. Ray is recommending that all pinouts should be specified by the designer (not the compiler), including the spare pins. Ray *isn't* saying that there shouldn't be any spare pins. Beating another trivial matter to death is what I do best... Bob Elkind, eteam@aracnet.com Jakab Tanko wrote: > > Yes,No,Maybe, > > If you assign 100% the I/O pins that is plain bad design practice in my > opinion, > just consider what happens if you need an extra pin afterwards; > As for the automatic pin placement it works fine except when you have > one of those designs > "from hell" (about 5% of all designs) that require extensive floor > planing just to get the thing > to work. In that case the wrong part was selected for the application or > your project > deadlines are different from mine because I never have time for doing > the job of the > P&R tool ....... > > Ray Andraka wrote: > > > NO! > > > > There are a few things the automatic placement is exceptionally poor at, with > > pin placement leading the list, followed by tbuf placement, and data-path > > placement. You should always specify the pin placement rather than letting the > > tools do it. Even a bad guess is likely to be better than the random placement > > generated by the tools, especially if you start itrating a design. See earlier > > posts in this thread for some guidelines on assigning pins. > > ###### Message-ID: <3A64BAC7.13395DB6@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Fixing pins on Spartan II References: <3A55D04A.C3890567@ics-ltd.com> <3A561198.29529BAB@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 33 Date: Tue, 16 Jan 2001 21:19:03 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 979679879 62.254.210.251 (Tue, 16 Jan 2001 21:17:59 GMT) NNTP-Posting-Date: Tue, 16 Jan 2001 21:17:59 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-fra1.dfn.de!news-lei1.dfn.de!news-nue1.dfn.de!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!newsfeed.icl.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3886 Ray Andraka wrote: > NO! > > There are a few things the automatic placement is exceptionally poor at, with > pin placement leading the list, followed by tbuf placement, and data-path > placement. You should always specify the pin placement rather than letting the > tools do it. Even a bad guess is likely to be better than the random placement > generated by the tools, especially if you start itrating a design. See earlier > posts in this thread for some guidelines on assigning pins. > > As for number of pins used, 100% is not a problem...most of the designs I touch > have 100% of the pins defined. The only time 100% pin utilization becomes a > problem is when you let the tools do the assigning! > > Jakab Tanko wrote: > > > > NO, pins are better left to be picked by the place&route tool. > > At minimum I think you should put together a dummy design, > > if you don't have time for a detailed one, do a quick place and route > > and go with that. As for the pins 100% is 20% to many used pins, I > > would select a larger device or different package to get more I/O pins. > > This is of course just my opinion and I could be wrong, > > > > jakab > > Another consideration is that leaving the pin assignment to the P&R tools can lead to a pinout that makes the PCB autorouter give up & die. Esp the case with the full square FG devices e.g. FG676.