From: blueflyer@my-deja.com Newsgroups: comp.arch.fpga Subject: Newbie question on clock timing generation Date: Tue, 26 Dec 2000 07:35:39 GMT Organization: Deja.com Lines: 45 Message-ID: <929hob$t60$1@nnrp1.deja.com> NNTP-Posting-Host: 38.28.103.239 X-Article-Creation-Date: Tue Dec 26 07:35:39 2000 GMT X-Http-User-Agent: Mozilla/4.73 [en] (Win95; U) X-Http-Proxy: 1.0 x55.deja.com:80 (Squid/1.1.22) for client 38.28.103.239 X-MyDeja-Info: XMYDJUIDblueflyer Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3550 Merry X'mas!! Unfortunated, I am back to work. I have a question and will appreciate anybody who can help clarify it: - I need to generate a clock for a circuit with many subcirccuits in it. - The circuit is driven by a master clock (Clk). - Each subcircuit has it's own clock derived from the master clock, and each clock has different clock rate (say Clk/2, Clk/4, Clk/5, Clk/7). - Each subcircuit is actived at different time and at different Clk edges (say the first subcircuit is activated at 12*Clk'rising_edge, done at 19*Clk'falling_edge. 20*Clk'falling_edge starts the second subcircuit and deactivated at 37*Clk'rising_edge......) - To keep the power low, the clocks for each subcircuit may be gated. Now the question is how to implement this in VHDL and suitable for synthesis? I have tried two ways (1) Having many counters and output appropriate timing when the counters count to a certain number. This require much more thinking to come up with appropriate setup for the counters. It generates couple errors when I tried to synthesize the circuit even it simulated OK. Haven't tried to solve the problem. (2) Using state machine, change state at Clk'event and output appropriate signals at the right state. This seems more friendlier to the synthesis tool (it didn't complain anything) and it is much easier. But the problem is that it has many states and it seems to me that this way is too bruteforce and very tedious. So the question is which way is better? I am targeting at FPGA at this monent and pretty soon mitigration to ASIC is very necessary. TIA Sent via Deja.com http://www.deja.com/ ###### From: Greg Neff Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 27 Dec 2000 17:52:30 GMT Organization: Deja.com Lines: 60 Message-ID: <92da8r$jfj$1@nnrp1.deja.com> References: <929hob$t60$1@nnrp1.deja.com> NNTP-Posting-Host: 216.192.113.16 X-Article-Creation-Date: Wed Dec 27 17:52:30 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 SERVER, 1.0 x71.deja.com:80 (Squid/1.1.22) for client 216.192.113.16 X-MyDeja-Info: XMYDJUIDgregneff Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!blackbush.xlink.net!uni-erlangen.de!fu-berlin.de!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3557 In article <929hob$t60$1@nnrp1.deja.com>, blueflyer@my-deja.com wrote: > Merry X'mas!! Unfortunated, I am back to work. > > I have a question and will appreciate anybody who can help clarify it: > > - I need to generate a clock for a circuit with many subcirccuits in it. > > - The circuit is driven by a master clock (Clk). > Right. You drive *all* flip-flops in the FPGA directly from this master clock, using global clock routing resources. > - Each subcircuit has it's own clock derived from the master clock, > and each clock has different clock rate (say Clk/2, Clk/4, Clk/5, > Clk/7). > Wrong! Don't do this. Instead, use the divider outputs as clock enables for the flip-flops. > - Each subcircuit is actived at different time and at different Clk > edges (say the first subcircuit is activated at 12*Clk'rising_edge, done > at 19*Clk'falling_edge. 20*Clk'falling_edge starts the second subcircuit > and deactivated at 37*Clk'rising_edge......) You can use the rising and falling edges of the master clock, if necessary. > > - To keep the power low, the clocks for each subcircuit may be gated. > No, they may not be gated. Unless you know exactly what you are doing, and the internal architecture of the FPGA, you *must* clock all flip- flops directly from global clock nets. No gates. > Now the question is how to implement this in VHDL and suitable for > synthesis? Don't bother. You are trying do do something in an FPGA that is not supposed to be done, and is contrary to good digital and FPGA design practices. (snip) -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ ###### From: blueflyer@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 27 Dec 2000 20:52:44 GMT Organization: Deja.com Lines: 79 Message-ID: <92dkqo$sm4$1@nnrp1.deja.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> NNTP-Posting-Host: 63.78.179.4 X-Article-Creation-Date: Wed Dec 27 20:52:44 2000 GMT X-Http-User-Agent: Mozilla/4.7 [en] (Win98; U) X-Http-Proxy: 1.1 daprx01.americas.nokia.com (NetCache 4.0R3), 1.0 x70.deja.com:80 (Squid/1.1.22) for client 172.18.141.115, 63.78.179.4 X-MyDeja-Info: XMYDJUIDblueflyer Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!blackbush.xlink.net!netnews.web.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!grolier!news.stealth.net!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3558 Greg, I already realized that gated clock is not good practice in FPGA. My question is how can we clock two subcircuit with different rates if all the FFs are driven by the same Master clock? Say I have two subcircuits, one is clocked at Clk_master/3, and the other Clk_master/2. Thanks. In article <92da8r$jfj$1@nnrp1.deja.com>, Greg Neff wrote: > In article <929hob$t60$1@nnrp1.deja.com>, > blueflyer@my-deja.com wrote: > > Merry X'mas!! Unfortunated, I am back to work. > > > > I have a question and will appreciate anybody who can help clarify it: > > > > - I need to generate a clock for a circuit with many subcirccuits in > it. > > > > - The circuit is driven by a master clock (Clk). > > > > Right. You drive *all* flip-flops in the FPGA directly from this master > clock, using global clock routing resources. > > > - Each subcircuit has it's own clock derived from the master clock, > > and each clock has different clock rate (say Clk/2, Clk/4, Clk/5, > > Clk/7). > > > > Wrong! Don't do this. Instead, use the divider outputs as clock > enables for the flip-flops. > > > - Each subcircuit is actived at different time and at different Clk > > edges (say the first subcircuit is activated at 12*Clk'rising_edge, > done > > at 19*Clk'falling_edge. 20*Clk'falling_edge starts the second > subcircuit > > and deactivated at 37*Clk'rising_edge......) > > You can use the rising and falling edges of the master clock, if > necessary. > > > > > - To keep the power low, the clocks for each subcircuit may be gated. > > > > No, they may not be gated. Unless you know exactly what you are doing, > and the internal architecture of the FPGA, you *must* clock all flip- > flops directly from global clock nets. No gates. > > > Now the question is how to implement this in VHDL and suitable for > > synthesis? > > Don't bother. You are trying do do something in an FPGA that is not > supposed to be done, and is contrary to good digital and FPGA design > practices. > > (snip) > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com > http://www.deja.com/ > Sent via Deja.com http://www.deja.com/ ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 27 Dec 2000 13:35:03 -0800 Organization: Xilinx Lines: 92 Message-ID: <3A4A6086.36E31AC2@xilinx.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> <92dkqo$sm4$1@nnrp1.deja.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: blueflyer@my-deja.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!nntp.abs.net!attmtf.ip.att.net!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3560 You route the common clock to all flip-flops. Then you design a state machine that generates clock enable signals that you route to the appropriate flip-flops' CE inputs.. For example, a CE signal that is High for one out of three clock periods enables your CLK/3 flip-flops. Such state machines ( you might also call them counters ) can easily be designed with a few CLBs. Really very big and fancy ones can be designed with BlockRAM. Peter Alfke, Xilinx Applications ================================================= blueflyer@my-deja.com wrote: > Greg, > > I already realized that gated clock is not good practice in FPGA. My > question is how can we clock two subcircuit with different rates if all > the FFs are driven by the same Master clock? Say I have two subcircuits, > one is clocked at Clk_master/3, and the other Clk_master/2. > > Thanks. > > In article <92da8r$jfj$1@nnrp1.deja.com>, > Greg Neff wrote: > > In article <929hob$t60$1@nnrp1.deja.com>, > > blueflyer@my-deja.com wrote: > > > Merry X'mas!! Unfortunated, I am back to work. > > > > > > I have a question and will appreciate anybody who can help clarify > it: > > > > > > - I need to generate a clock for a circuit with many subcirccuits in > > it. > > > > > > - The circuit is driven by a master clock (Clk). > > > > > > > Right. You drive *all* flip-flops in the FPGA directly from this > master > > clock, using global clock routing resources. > > > > > - Each subcircuit has it's own clock derived from the master clock, > > > and each clock has different clock rate (say Clk/2, Clk/4, Clk/5, > > > Clk/7). > > > > > > > Wrong! Don't do this. Instead, use the divider outputs as clock > > enables for the flip-flops. > > > > > - Each subcircuit is actived at different time and at different Clk > > > edges (say the first subcircuit is activated at 12*Clk'rising_edge, > > done > > > at 19*Clk'falling_edge. 20*Clk'falling_edge starts the second > > subcircuit > > > and deactivated at 37*Clk'rising_edge......) > > > > You can use the rising and falling edges of the master clock, if > > necessary. > > > > > > > > - To keep the power low, the clocks for each subcircuit may be > gated. > > > > > > > No, they may not be gated. Unless you know exactly what you are > doing, > > and the internal architecture of the FPGA, you *must* clock all flip- > > flops directly from global clock nets. No gates. > > > > > Now the question is how to implement this in VHDL and suitable for > > > synthesis? > > > > Don't bother. You are trying do do something in an FPGA that is not > > supposed to be done, and is contrary to good digital and FPGA design > > practices. > > > > (snip) > > > > -- > > Greg Neff > > VP Engineering > > *Microsym* Computers Inc. > > greg@guesswhichwordgoeshere.com > > > > Sent via Deja.com > > http://www.deja.com/ > > > > Sent via Deja.com > http://www.deja.com/ ###### From: blueflyer@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 27 Dec 2000 22:15:30 GMT Organization: Deja.com Lines: 115 Message-ID: <92dplr$rb$1@nnrp1.deja.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> <92dkqo$sm4$1@nnrp1.deja.com> <3A4A6086.36E31AC2@xilinx.com> NNTP-Posting-Host: 63.78.179.5 X-Article-Creation-Date: Wed Dec 27 22:15:30 2000 GMT X-Http-User-Agent: Mozilla/4.7 [en] (Win98; U) X-Http-Proxy: 1.1 daprx02.americas.nokia.com (NetCache 4.0R3), 1.0 x70.deja.com:80 (Squid/1.1.22) for client 172.18.141.115, 63.78.179.5 X-MyDeja-Info: XMYDJUIDblueflyer Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3564 Thanks, it is really useful. In article <3A4A6086.36E31AC2@xilinx.com>, peter.alfke@xilinx.com wrote: > You route the common clock to all flip-flops. > Then you design a state machine that generates clock enable signals > that you route to the appropriate flip-flops' CE inputs.. > For example, a CE signal that is High for one out of three clock periods > enables your CLK/3 flip-flops. > > Such state machines ( you might also call them counters ) > can easily be designed with a few CLBs. > Really very big and fancy ones can be designed with BlockRAM. > > Peter Alfke, Xilinx Applications > ================================================= > blueflyer@my-deja.com wrote: > > > Greg, > > > > I already realized that gated clock is not good practice in FPGA. My > > question is how can we clock two subcircuit with different rates if all > > the FFs are driven by the same Master clock? Say I have two subcircuits, > > one is clocked at Clk_master/3, and the other Clk_master/2. > > > > Thanks. > > > > In article <92da8r$jfj$1@nnrp1.deja.com>, > > Greg Neff wrote: > > > In article <929hob$t60$1@nnrp1.deja.com>, > > > blueflyer@my-deja.com wrote: > > > > Merry X'mas!! Unfortunated, I am back to work. > > > > > > > > I have a question and will appreciate anybody who can help clarify > > it: > > > > > > > > - I need to generate a clock for a circuit with many subcirccuits in > > > it. > > > > > > > > - The circuit is driven by a master clock (Clk). > > > > > > > > > > Right. You drive *all* flip-flops in the FPGA directly from this > > master > > > clock, using global clock routing resources. > > > > > > > - Each subcircuit has it's own clock derived from the master clock, > > > > and each clock has different clock rate (say Clk/2, Clk/4, Clk/5, > > > > Clk/7). > > > > > > > > > > Wrong! Don't do this. Instead, use the divider outputs as clock > > > enables for the flip-flops. > > > > > > > - Each subcircuit is actived at different time and at different Clk > > > > edges (say the first subcircuit is activated at 12*Clk'rising_edge, > > > done > > > > at 19*Clk'falling_edge. 20*Clk'falling_edge starts the second > > > subcircuit > > > > and deactivated at 37*Clk'rising_edge......) > > > > > > You can use the rising and falling edges of the master clock, if > > > necessary. > > > > > > > > > > > - To keep the power low, the clocks for each subcircuit may be > > gated. > > > > > > > > > > No, they may not be gated. Unless you know exactly what you are > > doing, > > > and the internal architecture of the FPGA, you *must* clock all flip- > > > flops directly from global clock nets. No gates. > > > > > > > Now the question is how to implement this in VHDL and suitable for > > > > synthesis? > > > > > > Don't bother. You are trying do do something in an FPGA that is not > > > supposed to be done, and is contrary to good digital and FPGA design > > > practices. > > > > > > (snip) > > > > > > -- > > > Greg Neff > > > VP Engineering > > > *Microsym* Computers Inc. > > > greg@guesswhichwordgoeshere.com > > > > > > Sent via Deja.com > > > http://www.deja.com/ > > > > > > > Sent via Deja.com > > http://www.deja.com/ > > Sent via Deja.com http://www.deja.com/ ###### From: murray@pa.dec.com (Hal Murray) Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: 3 Jan 2001 04:45:53 GMT Organization: Compaq Systems Research Center Lines: 20 Distribution: world Message-ID: <92uaq1$dgj@src-news.pa.dec.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> <92dkqo$sm4$1@nnrp1.deja.com> <3A4A6086.36E31AC2@xilinx.com> NNTP-Posting-Host: quatre.pa.dec.com X-Newsreader: xrn 9.01 Originator: murray@quatre.pa.dec.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!paloalto-snf1.gtei.net!news.gtei.net!newsgate.tandem.com!mailint03.im.hou.compaq.com!pa.dec.com!src.dec.com!murray Xref: chonsp.franklin.ch comp.arch.fpga:3596 > You route the common clock to all flip-flops. > Then you design a state machine that generates clock enable signals > that you route to the appropriate flip-flops' CE inputs.. > For example, a CE signal that is High for one out of three clock periods > enables your CLK/3 flip-flops. Do any languages/tools make it easy to write code like that? I'd really like to write my code so that it uses clock3 rather than using clock and cycle3 and cluttering things up with "if cycle3" all over the place. A simple text preprocessor would probably work, at least for stylized code. But I hate doing things like that when the tools don't support it because you end up with error messages refering to line numbers in the wrong file and such. -- These are my opinions, not necessarily my employers. I hate spam. ###### From: eml@riverside-machines.com.NOSPAM Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 03 Jan 2001 11:46:05 GMT Organization: Riverside Machines Ltd. Lines: 31 Message-ID: <3a530f66.10395943@news.dial.pipex.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> <92dkqo$sm4$1@nnrp1.deja.com> <3A4A6086.36E31AC2@xilinx.com> <92uaq1$dgj@src-news.pa.dec.com> NNTP-Posting-Host: userej29.uk.uudial.com X-Trace: lure.pipex.net 978522425 71 62.188.13.40 (3 Jan 2001 11:47:05 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 3 Jan 2001 11:47:05 GMT X-Newsreader: Forte Free Agent 1.11/32.235 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!grot.news.pipex.net!pipex!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3598 On 3 Jan 2001 04:45:53 GMT, murray@pa.dec.com (Hal Murray) wrote: >> You route the common clock to all flip-flops. >> Then you design a state machine that generates clock enable signals >> that you route to the appropriate flip-flops' CE inputs.. >> For example, a CE signal that is High for one out of three clock periods >> enables your CLK/3 flip-flops. > >Do any languages/tools make it easy to write code like that? > >I'd really like to write my code so that it uses clock3 rather than >using clock and cycle3 and cluttering things up with "if cycle3" all >over the place. > >A simple text preprocessor would probably work, at least for stylized >code. But I hate doing things like that when the tools don't support it >because you end up with error messages refering to line numbers >in the wrong file and such. There are tools (Synopsys Powermill, for example) to do it the other way round - ie. automatically create a gated clock from a clock enable - but I've never heard of anything that'll generate clock enables from clocks. I suspect that it won't be too long before single-clock designs are impractical on large FPGAs, and we'll have local clocks for different sectors of the chip, with synchronisation at the boundaries. Power consumption problems on large designs may also make multiple clocks much more common. Evan ###### From: eml@riverside-machines.com.NOSPAM Newsgroups: comp.arch.fpga Subject: Re: Newbie question on clock timing generation Date: Wed, 03 Jan 2001 11:46:29 GMT Organization: Riverside Machines Ltd. Lines: 13 Message-ID: <3a5310ff.10804430@news.dial.pipex.com> References: <929hob$t60$1@nnrp1.deja.com> <92da8r$jfj$1@nnrp1.deja.com> NNTP-Posting-Host: userej29.uk.uudial.com X-Trace: lure.pipex.net 978522449 71 62.188.13.40 (3 Jan 2001 11:47:29 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 3 Jan 2001 11:47:29 GMT X-Newsreader: Forte Free Agent 1.11/32.235 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!grot.news.pipex.net!pipex!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3599 On Wed, 27 Dec 2000 17:52:30 GMT, Greg Neff wrote: >> - To keep the power low, the clocks for each subcircuit may be gated. >> > >No, they may not be gated. Unless you know exactly what you are doing, >and the internal architecture of the FPGA, you *must* clock all flip- >flops directly from global clock nets. No gates. Remember that you can do all your gating *before* the clock buffer - Evan