From: longwayhome@my-deja.com Newsgroups: comp.arch.fpga Subject: Question about programming xcv100 Date: Sat, 23 Dec 2000 00:48:21 GMT Organization: Deja.com Lines: 23 Message-ID: <920sol$5re$1@nnrp1.deja.com> NNTP-Posting-Host: 195.147.250.190 X-Article-Creation-Date: Sat Dec 23 00:48:21 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; MSN 2.5; Windows 95) X-Http-Proxy: 1.0 wwwcache1-fe, 1.0 x68.deja.com:80 (Squid/1.1.22) for client 195.147.89.236, 195.147.250.190 X-MyDeja-Info: XMYDJUIDlongwayhome Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!News.Amsterdam.UnisourceCS!skynet.be!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3522 Hi I bought an xsv100 board from Xess, which has a Xilinx xcv100 chip on it. With the board came a utility which can send compiled bitstreams to the chip. I'd like to manually generate the bitstreams though, rather than compile them from a vhdl spec though, as my intention is to program it using evolutionary algorithms and I think this would be easier and faster than actually generating vhdl and compiling that then sending that to the chip. Does anyone know where I can find a spec which would show exactly how the bitstreams are interpreted by xcv100 ? I've already had an unsuccessfull look at the Xilinx site (but i've had problems finding what i want there before...) I'm a complete beginner at this, all advice greatfully accepted. Thanks David Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A442CBC.3A9401F8@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 References: <920sol$5re$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 72 Date: Sat, 23 Dec 2000 04:38:16 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 977546296 24.13.238.93 (Fri, 22 Dec 2000 20:38:16 PST) NNTP-Posting-Date: Fri, 22 Dec 2000 20:38:16 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!surfnet.nl!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!xfer13.netnews.com!netnews.com!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3517 This question comes up more often than most of us care to admit. The bitstream is largely considered proprietary, and there is plenty of potential for doing damage if not correct. Before attempting this, one should be thoroughly familiar with the fpga details and then some. Rather than trying to re-invent the tools, you'd be better off working with the tools. The xilinx tools do give you several entry points into the tools from which you can bypass the previous stuff without getting into the nuts and bolts of the bitstream. First stop would be using any one of a number of third party entry tools. The synthesizers as well as the schematic translators all have one of two formats of the output to go into the FPGA point tools. Those are edif and xnf. The edif format is pretty much an industry standard, and while it is not real user friendly, it could be used to enter a design directly. The contents of the edif netlist are xilinx primitives along with any attrubutes passed from the source, plus block boxes for other linked in edif netlists. The xnf format is an older xilinx specific format which frankly is a little easier to decipher or parse. I don't know how long, going into the future it will continue to be supported, as the clear preference is for edif. The advantage of going in to the front end of the xilinx tools is that you can link in third party macros, and you get the full benefit of the mapper, floorplanner, place and route and bitstream generator. If you don't want to use those for whatever reason (evolution is one of the more valid reasons I've heard), then you could use jbits to generate the bitstream from your own stuff. If you are so inclined, you could also enter the design through the FPGA editor, bypassing everything but the bitstream generation, at the espense of more tedious work. longwayhome@my-deja.com wrote: > > Hi > I bought an xsv100 board from Xess, which has a Xilinx xcv100 chip on > it. With the board came a utility which can send compiled bitstreams to > the chip. I'd like to manually generate the bitstreams though, rather > than compile them from a vhdl spec though, as my intention is to > program it using evolutionary algorithms and I think this would be > easier and faster than actually generating vhdl and compiling that then > sending that to the chip. > > Does anyone know where I can find a spec which would show exactly how > the bitstreams are interpreted by xcv100 ? I've already had an > unsuccessfull look at the Xilinx site (but i've had problems finding > what i want there before...) > > I'm a complete beginner at this, all advice greatfully accepted. > > Thanks > > David > > Sent via Deja.com > http://www.deja.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: longwayhome@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Sat, 23 Dec 2000 15:05:08 GMT Organization: Deja.com Lines: 15 Message-ID: <922ev2$7f8$1@nnrp1.deja.com> References: <920sol$5re$1@nnrp1.deja.com> <3A442CBC.3A9401F8@andraka.com> NNTP-Posting-Host: 195.147.250.190 X-Article-Creation-Date: Sat Dec 23 15:05:08 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; MSN 2.5; Windows 95) X-Http-Proxy: 1.0 wwwcache1-fe, 1.0 x55.deja.com:80 (Squid/1.1.22) for client 195.147.87.249, 195.147.250.190 X-MyDeja-Info: XMYDJUIDlongwayhome Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!xfer10.netnews.com!netnews.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3519 In article <3A442CBC.3A9401F8@andraka.com>, Ray Andraka wrote: > This question comes up more often than most of us care to admit. The bitstream [ snip ] Hi Thanks for taking the time to respond to my question. I appreciate it. David Sent via Deja.com http://www.deja.com/ ###### From: Peter Alfke Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Sat, 23 Dec 2000 14:25:19 -0800 Organization: Xilinx Lines: 49 Message-ID: <3A45264E.F4FBE995@xilinx.com> References: <920sol$5re$1@nnrp1.deja.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: longwayhome@my-deja.com CC: delon@xilinx.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!sunqbc.risq.qc.ca!feeder.qis.net!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3531 David, let me talk you out of what you seem to be trying. The vast majority of the bits in the bitstream has a specific function, activating a pass transistor, controlling a multiplexer, driving a metal line etc. ( A few bits are just left-over fill bits, but only a few) If you start "evolving" bitstreams, you will most likely create massive contention on the chip, i.e. two opposite signals driving the same piece of metal. Although the individual contention current may be just a few mA, multiple thousands can literally melt down the plastic package and destroy the chip. Xilinx used to make the XC6200 chip that did not have multiple outputs able to drive the same line, so it was bullet-proof, and it became the darling of experimenters like you. Unfortunately, XC6200 did not find a home in commercial applications, so we stopped making it. If you want to put evolving bitstreams on any Xilinx ( or Altera or Atmel) FPGAs, don't do it ! I copied Delon Levi here at Xilinx who may have additional thoughts. Peter Alfke, Xilinx Applications ================================ longwayhome@my-deja.com wrote: > Hi > I bought an xsv100 board from Xess, which has a Xilinx xcv100 chip on > it. With the board came a utility which can send compiled bitstreams to > the chip. I'd like to manually generate the bitstreams though, rather > than compile them from a vhdl spec though, as my intention is to > program it using evolutionary algorithms and I think this would be > easier and faster than actually generating vhdl and compiling that then > sending that to the chip. > > Does anyone know where I can find a spec which would show exactly how > the bitstreams are interpreted by xcv100 ? I've already had an > unsuccessfull look at the Xilinx site (but i've had problems finding > what i want there before...) > > I'm a complete beginner at this, all advice greatfully accepted. > > Thanks > > David > > Sent via Deja.com > http://www.deja.com/ ###### From: longwayhome@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Sun, 24 Dec 2000 00:29:06 GMT Organization: Deja.com Lines: 51 Message-ID: <923g0f$uju$1@nnrp1.deja.com> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> NNTP-Posting-Host: 195.147.246.156 X-Article-Creation-Date: Sun Dec 24 00:29:06 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; MSN 2.5; Windows 95) X-Http-Proxy: 1.0 wwwcache5-he, 1.0 x53.deja.com:80 (Squid/1.1.22) for client 195.147.172.125, 195.147.246.156 X-MyDeja-Info: XMYDJUIDlongwayhome Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!xfer10.netnews.com!netnews.com!cpk-news-hub1.bbnplanet.com!news.gtei.net!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3534 In article <3A45264E.F4FBE995@xilinx.com>, peter.alfke@xilinx.com wrote: > David, > let me talk you out of what you seem to be trying. Oh dear :-) > Xilinx used to make the XC6200 chip that did not have multiple outputs > able to drive the same line, so it was bullet-proof, and it became the > darling of experimenters like you. > Unfortunately, XC6200 did not find a home in commercial applications, so > we stopped making it. Yes, someone recommended me to get one of those chips, however I learned you weren't producing them anymore (and didn't know why they had become so 'legendary' in this use anyway). > If you want to put evolving bitstreams on any Xilinx ( or Altera or Atmel) > FPGAs, don't do it ! What I was planning on doing (correct me if i'm way out of line here, which is fairly possible) was taking each 'cell' on the fpga (in a given area, for example an area of 20 x 20 cells) then having some simple rules which i'd follow, deciding what the purpose of a given cell was to be (within the rules, eg only one output to drive a given line) then i'd take this meta design (arrived at through an evolving algorithm) convert it to the bitstreams and pass the bitstream to the chip using the xsload (comes with the Xess cdrom) where it would be evaluated. However i'd need to find out what each bit for a cell specified which I could then use to transfer my meta design to a bitstream - is it possible to get this info [i'm just a hobbyist, no danger of me seeking to get any competitive advantage over xilinx i can assure you :-)] I didn't actually want to treat the bitstreams themselves as a piece of 'dna' to mutate/breed etc although now that you've mentioned that idea an XC6200 board would be a nice thing to have (if xilinx have any such boards lying around destined for wastage... :-) Thanks for your warning though. Can you can help with that cell programming info, or suggest any other way of approaching this problem ? (i'm _really_ desperate to try this evolving hardware thing...) David Sent via Deja.com http://www.deja.com/ ###### From: Muzaffer Kal Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Organization: dspia inc. http://www.dspia.com Message-ID: References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 Date: Sun, 24 Dec 2000 07:04:58 GMT NNTP-Posting-Host: 24.11.138.186 X-Complaints-To: abuse@home.net X-Trace: news1.frmt1.sfba.home.com 977641498 24.11.138.186 (Sat, 23 Dec 2000 23:04:58 PST) NNTP-Posting-Date: Sat, 23 Dec 2000 23:04:58 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.frmt1.sfba.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3542 On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: >Thanks for your warning though. Can you can help with that cell >programming info, or suggest any other way of approaching this >problem ? (i'm _really_ desperate to try this evolving hardware >thing...) I have an idea on on this. I think it should be possible to write an EDF as the output of your genetic algorithm and go through the P&R (you can use the command line tools for full automation). If you can also generate the placement with your tool (actually the placement is already fixed; you just need to generate the behaviour of each individual LUT) the P&R should be quick. This might prevent you from programming the FPGA to reprogram itself, i.e. you can't put the growth algorithm into the FPGA and get it to reprogram itself. The pc/workstation has to be in the feedback loop. I think this is a much easier project than reverse-engineering the bit file. hope this helps, Muzaffer FPGA DSP Consulting http://www.dspia.com ###### From: "Simon Bacon" Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Sun, 24 Dec 2000 08:06:52 -0000 Message-ID: <977647015.5652.0.nnrp-01.9e9832fa@news.demon.co.uk> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> NNTP-Posting-Host: tile.demon.co.uk X-NNTP-Posting-Host: tile.demon.co.uk:158.152.50.250 X-Trace: news.demon.co.uk 977647015 nnrp-01:5652 NO-IDENT tile.demon.co.uk:158.152.50.250 X-Complaints-To: abuse@demon.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 Lines: 25 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!transit.news.xs4all.nl!bullseye.news.demon.net!news.demon.co.uk!demon!tile.demon.co.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3540 David Is your 'cell' a few LUTs/FFs with unchanging routing? If so, I believe the experts in the group can help you on this. Simon > What I was planning on doing (correct me if i'm way out of line here, > which is fairly possible) was taking each 'cell' on the fpga (in a > given area, for example an area of 20 x 20 cells) then having some > simple rules which i'd follow, deciding what the purpose of a given > cell was to be (within the rules, eg only one output to drive a given > line) then i'd take this meta design (arrived at through an evolving > algorithm) convert it to the bitstreams and pass the bitstream to the > chip using the xsload (comes with the Xess cdrom) where it would be > evaluated. However i'd need to find out what each bit for a cell > specified which I could then use to transfer my meta design to a > bitstream - is it possible to get this info [i'm just a hobbyist, no > danger of me seeking to get any competitive advantage over xilinx i can > assure you :-)] ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 149 Date: Sun, 24 Dec 2000 00:48:48 -0800 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 977647838 216.103.85.188 (Sun, 24 Dec 2000 00:50:38 PST) NNTP-Posting-Date: Sun, 24 Dec 2000 00:50:38 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!dca1-hub1.news.digex.net!intermedia!cyclone-sf.pbi.net!206.13.28.33!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3539 On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: >In article <3A45264E.F4FBE995@xilinx.com>, > peter.alfke@xilinx.com wrote: >> David, >> let me talk you out of what you seem to be trying. > >Oh dear :-) Well, I wont try and talk you out of it, but I will try and save you some time understanding your options. First, permuting the bit stream directly (using an XC6200) has been done, and there were some interesting results. see http://www.cogs.susx.ac.uk/users/adrianth/ade.html >> Xilinx used to make the XC6200 chip that did not have multiple outputs >> able to drive the same line, so it was bullet-proof, and it became the >> darling of experimenters like you. >> Unfortunately, XC6200 did not find a home in commercial applications, >so >> we stopped making it. > >Yes, someone recommended me to get one of those chips, however I >learned you weren't producing them anymore (and didn't know why they >had become so 'legendary' in this use anyway). > >> If you want to put evolving bitstreams on any Xilinx ( or Altera or >Atmel) >> FPGAs, don't do it ! Do it, but be really careful. >What I was planning on doing (correct me if i'm way out of line here, >which is fairly possible) was taking each 'cell' on the fpga (in a >given area, for example an area of 20 x 20 cells) then having some >simple rules which i'd follow, deciding what the purpose of a given >cell was to be (within the rules, eg only one output to drive a given >line) then i'd take this meta design (arrived at through an evolving >algorithm) convert it to the bitstreams and pass the bitstream to the >chip using the xsload (comes with the Xess cdrom) where it would be >evaluated. However i'd need to find out what each bit for a cell >specified which I could then use to transfer my meta design to a >bitstream - is it possible to get this info [i'm just a hobbyist, no >danger of me seeking to get any competitive advantage over xilinx i can >assure you :-)] What you do depends on how random/constrained you want the primordial soup to be, how long it takes to create an individual, and how long it takes to evaluate the individual. First, the bitstream format is proprietory,and Xilinx has given no indication that this will change. (Others who have seen this thread before (and before, and before) might think this is a wondeful opportunity to restart this thread again. Please, as my holiday wish, dont) Since XC6200 is not readily available either, what that leaves you are neat products like Virtex, which have a wonderful set of features to play with. So a typical Flow from a specification to an individual might be: VHDL -> EDIF -> NCD -> Placed and routed NCD -> Bitstream. For all the following proposals, you probably need to do things to make sure your specification of the individual does not specify anything illegal. If time to create an individual is not an issue, have you individual generator create VHDL. All the following require less time to create an individual, but have progressively more complex generator challenges :-) Generate EDIF directly. Generate unrouted NCD directly. Use a program called XDL which is available from Xilinx, if you ask. You need to do quite a lot of work to make this useable, but you do get full access to the chip's capabilities. Generate routed NCD directly. Use a program called XDL which is available from Xilinx, if you ask. You need to do quite a lot of work to make this useable, but you do get full access to the chip's capabilities. Since you are skipping Place and route, this is faster than the previous suggestion, but now P&R is your responsibility Edit a P&R NCD with JBITS. This program was created by people like you, for you. It is a Java interface to the bitstream. You use it either to creat a bitstream from scratch, or to modify an existing bitstream. The FPGA editor program can be used to modify an NCD file, and it can be run in batch mode. Theoretically you could create a base individual, and create edit scripts to modify it. >I didn't actually want to treat the bitstreams themselves as a piece >of 'dna' to mutate/breed etc although now that you've mentioned that >idea an XC6200 board would be a nice thing to have (if xilinx have any >such boards lying around destined for wastage... :-) This is what Adrian Thompson did see http://www.cogs.susx.ac.uk/users/adrianth/ade.html and in particular: http://www.cogs.susx.ac.uk/users/adrianth/cacm99/paper.html >Thanks for your warning though. Can you can help with that cell >programming info, or suggest any other way of approaching this >problem ? (i'm _really_ desperate to try this evolving hardware >thing...) > >David > Here are some ideas for much easier stuff than above that you might want to consider, as a way to get started, and maybe get some useful results with very fast generation. 1) Create a design that uses the LUTs in dual port RAM mode, and connect them up in some sort of mesh, with some feedback too. Use only one read port for all the logic. I.e. each pair of LUTs that run as 16 x 1 DP RAM, use the read port for building your individual. Connect all the write ports to the individual generator. For this topology, the interconnect is static, but you can vary the gate at an extremely fast rate. 2) Like 1, but add some flipflops to the soup. 3) Like 1 or 2, but allocate some LUTs to implement some muxes, and this then gives you some limited ability to change the routing. 4) More of the same, add in block RAMs (maybe in dual port mode) All of these can be done while avoiding the disaster of creating illegal bitstreams. With a careful design, you may be able to create individuals in as little as a micro second. If you can test them in the same amount of time, you could evolve 500,000 individuals per second, which might make up for the constraints of the soup. Have fun. Philip Freidin Philip Freidin Fliptronics ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: 24 Dec 2000 17:38:09 +0100 Organization: My own Private Self Lines: 60 Message-ID: <6ur92xsrke.fsf@chonsp.franklin.ch> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 977675889 633 10.0.3.2 (24 Dec 2000 16:38:09 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 24 Dec 2000 16:38:09 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:3543 Philip Freidin writes: > On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: > >In article <3A45264E.F4FBE995@xilinx.com>, > > peter.alfke@xilinx.com wrote: > >> David, > >> let me talk you out of what you seem to be trying. > > > >Oh dear :-) > > Well, I wont try and talk you out of it, but I will try and save you some > time understanding your options. And I will add to that. > >> If you want to put evolving bitstreams on any Xilinx ( or Altera or > >Atmel) > >> FPGAs, don't do it ! > > Do it, but be really careful. Or have a tool be carefull for you. Written by someone who does know what the bitstream does. > Edit a P&R NCD with JBITS. This program was created by people > like you, for you. It is a Java interface to the bitstream. You use it > either to creat a bitstream from scratch, or to modify an existing > bitstream. Or even uses Xilinx own prefab FPGA evolver in the JBits package. From: /JBits2.5/ReadMe.html (The JBits 2.5 SDK for Virtex) --------------- begin quote GeneticFPGA GeneticFPGA, is a Java-based tool for evolving circuits on Xilinx Virtex? FPGAs or on the JBits Device Simulator. Using an evolutionary algorithm, the system mutates a bitstream to create a circuit. The user specifies a fitness function that measures how well the circuit performs, along with some stimulus and expected output. The system mutates the bitstream to reduce the error between the actual output and the expected output. The design process is a bit non-traditional. Whereas a designer typically creates a circuit by assembling known structures, here a designer specifies desired behavior and lets the system construct the solution. --------------- end quote And yes, the question mark is in the original text. If you want to go this way, send a mail to jbits@xilinx.com to order your copy (you recieve URL and password by reply email). -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic ###### From: longwayhome@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Mon, 25 Dec 2000 19:38:17 GMT Organization: Deja.com Lines: 41 Message-ID: <9287n9$1jf$1@nnrp1.deja.com> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> <6ur92xsrke.fsf@chonsp.franklin.ch> NNTP-Posting-Host: 195.147.250.191 X-Article-Creation-Date: Mon Dec 25 19:38:17 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.01; MSN 2.5; Windows 95) X-Http-Proxy: 1.0 wwwcache2-fe, 1.0 x54.deja.com:80 (Squid/1.1.22) for client 195.147.106.129, 195.147.250.191 X-MyDeja-Info: XMYDJUIDlongwayhome Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!enews.sgi.com!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3549 In article <6ur92xsrke.fsf@chonsp.franklin.ch>, Neil Franklin wrote: > Or even uses Xilinx own prefab FPGA evolver in the JBits package. Hello everyone, and thanks for all the helpful responses. I've downloaded the jbits package and java 2 sdk from sun, and everything went fine (the jbits package even comes with a very efficient genetic algorithm already included with the evolver mechanism which is great! (you can of course substitute that with your own algorithm object if you want to)). My only problem now is that to use the genetic evolution classes (and any other classes for writing to the virtex device) you need to have a null bitstream file (to guarantee that you don't damage the device - the evolution classes look after that for you once it starts, but you need to have it in a safe state to begin with). The jbits package came with null bit files for the xcv300, 800 and 1000, unfortunately i have an xcv100 board (on which i've already run xess's test program, so im not sure what state the current gates etc are left in although thats probably not so important). According to the documentation "the null bitstream specifies a circuit with all the fpga resources turned off and unconnected. This bitstream is typically generated by the Xilinx Foundation/Alliance tools and is then initialized to a null state using the MakeNullBs program". Am I right in thinking that if I write a small jbits program to read the current configuration and then run MakeNullBs [comes with jbits] on the resulting bitstream I get a 'null bitstream' ? [I don't have Foundation/Alliance btw]. MakeNullBs takes an input bitstream and returns an output one, but other than that its documentation is non existant that I can find. Thanks again and seasons greetings! :-) David Sent via Deja.com http://www.deja.com/ ###### From: "Delon Levi" Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Wed, 27 Dec 2000 12:46:07 -0800 Organization: Xilinx,Inc Lines: 72 Message-ID: <92dk5m$g281@cliff.xsj.xilinx.com> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> NNTP-Posting-Host: 149.199.7.177 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!newsfeed.mathworks.com!news.idt.net!attmtf.ip.att.net!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3559 The XC6200 was the first FPGA used to evolve circuits primarily because the hardware was designed so that random bistreams would not cause contention, which could destroy the chip. Using a slighly modified process, we in the JBits group have been evolving digital circuits on mainstream devices like the Xilinx Virtex series for several years. Instead of protecting against contention at a hardware level, we protect against it using software. Random bitstreams are still generated, but they are contstrained to only generate non-contentious circuits. If anyone is interested in finding out more, there is an evolvable hardware toolkit in the JBits software. You can obtain the software by sending a request to JBits@xilinx.com You can also read some papers that explain the process in more detail: http://www.io.com/~guccione/Papers/Papers.html Delon "Peter Alfke" wrote in message news:3A45264E.F4FBE995@xilinx.com... > David, > let me talk you out of what you seem to be trying. > The vast majority of the bits in the bitstream has a specific function, > activating a pass transistor, controlling a multiplexer, driving a metal > line etc. ( A few bits are just left-over fill bits, but only a few) > If you start "evolving" bitstreams, you will most likely create massive > contention on the chip, i.e. two opposite signals driving the same piece > of metal. Although the individual contention current may be just a few mA, > multiple thousands can literally melt down the plastic package and destroy > the chip. > > Xilinx used to make the XC6200 chip that did not have multiple outputs > able to drive the same line, so it was bullet-proof, and it became the > darling of experimenters like you. > Unfortunately, XC6200 did not find a home in commercial applications, so > we stopped making it. > > If you want to put evolving bitstreams on any Xilinx ( or Altera or Atmel) > FPGAs, don't do it ! > I copied Delon Levi here at Xilinx who may have additional thoughts. > > Peter Alfke, Xilinx Applications > ================================ > > longwayhome@my-deja.com wrote: > > > Hi > > I bought an xsv100 board from Xess, which has a Xilinx xcv100 chip on > > it. With the board came a utility which can send compiled bitstreams to > > the chip. I'd like to manually generate the bitstreams though, rather > > than compile them from a vhdl spec though, as my intention is to > > program it using evolutionary algorithms and I think this would be > > easier and faster than actually generating vhdl and compiling that then > > sending that to the chip. > > > > Does anyone know where I can find a spec which would show exactly how > > the bitstreams are interpreted by xcv100 ? I've already had an > > unsuccessfull look at the Xilinx site (but i've had problems finding > > what i want there before...) > > > > I'm a complete beginner at this, all advice greatfully accepted. > > > > Thanks > > > > David > > > > Sent via Deja.com > > http://www.deja.com/ > ###### From: "Domagoj" Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Wed, 27 Dec 2000 06:35:26 +0100 Organization: CARNet, CROATIA Lines: 24 Message-ID: <92efdd$l6v$1@bagan.srce.hr> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> NNTP-Posting-Host: asy173.jmu.carnet.hr X-Trace: bagan.srce.hr 977977580 21727 193.198.129.53 (28 Dec 2000 04:26:21 GMT) X-Complaints-To: abuse@news.carnet.hr NNTP-Posting-Date: 28 Dec 2000 04:26:21 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2314.1300 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2314.1300 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!blackbush.xlink.net!newsfeed01.sul.t-online.de!t-online.de!newsfeed.online.be!newscore.univie.ac.at!carnet.feed!CARNet.hr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3563 Hi Philip, Philip Freidin wrote in message news:2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com... > On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: > >In article <3A45264E.F4FBE995@xilinx.com>, > Edit a P&R NCD with JBITS. This program was created by people > like you, for you. It is a Java interface to the bitstream. You use it > either to creat a bitstream from scratch, or to modify an existing > bitstream. Do you maybe know the price of JBITS package ? Any discounts for universities ? I haven't found much info on Xilinx site about that sw. Thanks. regards, ------------------------------------------- - Domagoj - - Domagoj@engineer.com - ------------------------------------------- ###### From: Philip Freidin Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Organization: Fliptronics Reply-To: philip@fliptronics.com Message-ID: References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> <92efdd$l6v$1@bagan.srce.hr> X-Newsreader: Forte Agent 1.8/32.548 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 Date: Thu, 28 Dec 2000 00:14:54 -0800 NNTP-Posting-Host: 216.103.85.188 X-Complaints-To: abuse@pacbell.net X-Trace: news.pacbell.net 977991405 216.103.85.188 (Thu, 28 Dec 2000 00:16:45 PST) NNTP-Posting-Date: Thu, 28 Dec 2000 00:16:45 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cyclone0.chicago.il.ameritech.net!cyclone-sf.pbi.net!206.13.28.33!news.pacbell.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3566 On Wed, 27 Dec 2000 06:35:26 +0100, "Domagoj" wrote: >Hi Philip, > >Philip Freidin wrote >> On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: >> >In article <3A45264E.F4FBE995@xilinx.com>, >> Edit a P&R NCD with JBITS. This program was created by people >> like you, for you. It is a Java interface to the bitstream. You use it >> either to creat a bitstream from scratch, or to modify an existing >> bitstream. > > Do you maybe know the price of JBITS package ? It's FREE >Any discounts for universities ? It's FREE for universities too ! >I haven't found much info on Xilinx site about that sw. Send email to JBits@xilinx.com and ask for the access. They will tell you how to get it (via FTP), and docs, and apps. >Thanks. You are welcome. Happy new year. >------------------------------------------- >- Domagoj - >- Domagoj@engineer.com - >------------------------------------------- Philip Freidin Fliptronics ###### From: Phil James-Roxby Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 Date: Thu, 28 Dec 2000 08:33:35 -0700 Organization: Xilinx, Inc. Lines: 24 Message-ID: <3A4B5D4F.BECFC08@xilinx.com> References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> <6ur92xsrke.fsf@chonsp.franklin.ch> <9287n9$1jf$1@nnrp1.deja.com> NNTP-Posting-Host: 149.199.185.56 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla2!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3567 longwayhome@my-deja.com wrote: > Am I right in thinking that if I write a small jbits program to read > the current configuration and then run MakeNullBs [comes with jbits] on > the resulting bitstream I get a 'null bitstream' ? [I don't have > Foundation/Alliance btw]. MakeNullBs takes an input bitstream and > returns an output one, but other than that its documentation is non > existant that I can find. You are indeed right in thinking that. To be honest, you are probably better directing these sorts of questions to jbits@xilinx.com We do read the newsgroup but you'll get a quicker answer if you go straight to the horses mouth as it were. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder --------------------------------------------------------------------- ###### Message-ID: <3A5288D8.A3354967@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Question about programming xcv100 References: <920sol$5re$1@nnrp1.deja.com> <3A45264E.F4FBE995@xilinx.com> <923g0f$uju$1@nnrp1.deja.com> <2sbb4t44310hftg2j35agsc59aq7ma26du@4ax.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 161 Date: Wed, 03 Jan 2001 02:02:36 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 978487356 24.13.238.93 (Tue, 02 Jan 2001 18:02:36 PST) NNTP-Posting-Date: Tue, 02 Jan 2001 18:02:36 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!newshub2.rdc1.sfba.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3588 The dual port mode is one way of updating LUT contents, and will work for 4K as well as Virtex. The Virtex SRL16 provides an even better mechanism for reloading LUTs, as there is very little overhead and the density is the same as a fixed LUT instead of double the resources. Many LUTs can be strunct together and reloaded as a serial shift chain. Philip Freidin wrote: > > On Sun, 24 Dec 2000 00:29:06 GMT, longwayhome@my-deja.com wrote: > >In article <3A45264E.F4FBE995@xilinx.com>, > > peter.alfke@xilinx.com wrote: > >> David, > >> let me talk you out of what you seem to be trying. > > > >Oh dear :-) > > Well, I wont try and talk you out of it, but I will try and save you some > time understanding your options. > > First, permuting the bit stream directly (using an XC6200) has been done, > and there were some interesting results. > > see http://www.cogs.susx.ac.uk/users/adrianth/ade.html > > >> Xilinx used to make the XC6200 chip that did not have multiple outputs > >> able to drive the same line, so it was bullet-proof, and it became the > >> darling of experimenters like you. > >> Unfortunately, XC6200 did not find a home in commercial applications, > >so > >> we stopped making it. > > > >Yes, someone recommended me to get one of those chips, however I > >learned you weren't producing them anymore (and didn't know why they > >had become so 'legendary' in this use anyway). > > > >> If you want to put evolving bitstreams on any Xilinx ( or Altera or > >Atmel) > >> FPGAs, don't do it ! > > Do it, but be really careful. > > >What I was planning on doing (correct me if i'm way out of line here, > >which is fairly possible) was taking each 'cell' on the fpga (in a > >given area, for example an area of 20 x 20 cells) then having some > >simple rules which i'd follow, deciding what the purpose of a given > >cell was to be (within the rules, eg only one output to drive a given > >line) then i'd take this meta design (arrived at through an evolving > >algorithm) convert it to the bitstreams and pass the bitstream to the > >chip using the xsload (comes with the Xess cdrom) where it would be > >evaluated. However i'd need to find out what each bit for a cell > >specified which I could then use to transfer my meta design to a > >bitstream - is it possible to get this info [i'm just a hobbyist, no > >danger of me seeking to get any competitive advantage over xilinx i can > >assure you :-)] > > What you do depends on how random/constrained you want the > primordial soup to be, how long it takes to create an individual, > and how long it takes to evaluate the individual. > > First, the bitstream format is proprietory,and Xilinx has given no > indication that this will change. (Others who have seen this > thread before (and before, and before) might think this is a > wondeful opportunity to restart this thread again. Please, as my > holiday wish, dont) > > Since XC6200 is not readily available either, what that leaves > you are neat products like Virtex, which have a wonderful set > of features to play with. > > So a typical Flow from a specification to an individual might be: > > VHDL -> EDIF -> NCD -> Placed and routed NCD -> Bitstream. > > For all the following proposals, you probably need to do things > to make sure your specification of the individual does not specify > anything illegal. > > If time to create an individual is not an issue, have you individual > generator create VHDL. > > All the following require less time to create an individual, but have > progressively more complex generator challenges :-) > > Generate EDIF directly. > > Generate unrouted NCD directly. Use a program called XDL which > is available from Xilinx, if you ask. You need to do quite a lot of work > to make this useable, but you do get full access to the chip's > capabilities. > > Generate routed NCD directly. Use a program called XDL which > is available from Xilinx, if you ask. You need to do quite a lot of work > to make this useable, but you do get full access to the chip's > capabilities. Since you are skipping Place and route, this is faster > than the previous suggestion, but now P&R is your responsibility > > Edit a P&R NCD with JBITS. This program was created by people > like you, for you. It is a Java interface to the bitstream. You use it > either to creat a bitstream from scratch, or to modify an existing > bitstream. > > The FPGA editor program can be used to modify an NCD file, and > it can be run in batch mode. Theoretically you could create a base > individual, and create edit scripts to modify it. > > >I didn't actually want to treat the bitstreams themselves as a piece > >of 'dna' to mutate/breed etc although now that you've mentioned that > >idea an XC6200 board would be a nice thing to have (if xilinx have any > >such boards lying around destined for wastage... :-) > > This is what Adrian Thompson did > see http://www.cogs.susx.ac.uk/users/adrianth/ade.html > and in particular: > http://www.cogs.susx.ac.uk/users/adrianth/cacm99/paper.html > > >Thanks for your warning though. Can you can help with that cell > >programming info, or suggest any other way of approaching this > >problem ? (i'm _really_ desperate to try this evolving hardware > >thing...) > > > >David > > > > Here are some ideas for much easier stuff than above that you might > want to consider, as a way to get started, and maybe get some > useful results with very fast generation. > > 1) Create a design that uses the LUTs in dual port RAM mode, and > connect them up in some sort of mesh, with some feedback too. > Use only one read port for all the logic. I.e. each pair of LUTs that > run as 16 x 1 DP RAM, use the read port for building your individual. > Connect all the write ports to the individual generator. For this > topology, the interconnect is static, but you can vary the gate at > an extremely fast rate. > > 2) Like 1, but add some flipflops to the soup. > > 3) Like 1 or 2, but allocate some LUTs to implement some muxes, > and this then gives you some limited ability to change the routing. > > 4) More of the same, add in block RAMs (maybe in dual port mode) > > All of these can be done while avoiding the disaster of creating > illegal bitstreams. With a careful design, you may be able to create > individuals in as little as a micro second. If you can test them in the > same amount of time, you could evolve 500,000 individuals per > second, which might make up for the constraints of the soup. > > Have fun. > > Philip Freidin > > Philip Freidin > Fliptronics -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com