From: hoyte@ucsu.colorado.edu Newsgroups: comp.arch.fpga Subject: FPGA and Board for Microprocessor Design? Date: Tue, 19 Dec 2000 01:29:39 GMT Organization: Deja.com Lines: 13 Message-ID: <91mdlq$pi6$1@nnrp1.deja.com> NNTP-Posting-Host: 199.174.238.168 X-Article-Creation-Date: Tue Dec 19 01:29:39 2000 GMT X-Http-User-Agent: Mozilla/4.6 [en] (Win98; I) X-Http-Proxy: 1.0 x57.deja.com:80 (Squid/1.1.22) for client 199.174.238.168 X-MyDeja-Info: XMYDJUIDexley Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.bme.hu!news.tele.dk!144.212.100.101!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3383 I recently worked on a senior project where we designed a 16-bit RISC microprocessor, and implemented the design in an FPGA. I'd like to be able to do something similar on my own, and I'm trying to find a good FPGA/board combination that is (relatively) affordable, and compatible with the Xilinx student edition software. If anyone has any suggestions, they would be greatly appreciated. Thanks, Eric Hoyt Sent via Deja.com http://www.deja.com/ ###### From: Dave Vanden Bout Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? Date: Tue, 19 Dec 2000 06:55:50 -0500 Organization: XESS Corp. Lines: 26 Message-ID: <3A3F4CC6.5D49C69C@xess.com> References: <91mdlq$pi6$1@nnrp1.deja.com> NNTP-Posting-Host: 3f.32.36.0a Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Server-Date: 19 Dec 2000 11:55:41 GMT X-Mailer: Mozilla 4.75 [en] (Win95; U) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.onemain.com!feed1.onemain.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3404 hoyte@ucsu.colorado.edu wrote: > I recently worked on a senior project where we designed a 16-bit RISC > microprocessor, and implemented the design in an FPGA. I'd like to be > able to do something similar on my own, and I'm trying to find a good > FPGA/board combination that is (relatively) affordable, and compatible > with the Xilinx student edition software. If anyone has any suggestions, > they would be greatly appreciated. > I'll propose using an XS40 Board. You can see more about those by checking the links at http://www.xess.com/ho04000.html. You can find information about Jan Gray's XSOC CPU and associated C compiler that work with the XS40-005XL Board at http://www.fpgacpu.org. You can also look at the list of FPGA boards at http://www.optimagic.com. The list summarizes various features and prices so you can make a quick determination of suitable manufacturers. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || ###### From: "Tony Burch" Newsgroups: comp.arch.fpga References: <91mdlq$pi6$1@nnrp1.deja.com> Subject: Re: FPGA and Board for Microprocessor Design? Lines: 50 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 X-Original-NNTP-Posting-Host: tntwc01-3-110.idx.com.au Message-ID: <3a3f6a3d@news1.idx.com.au> Date: Wed, 20 Dec 2000 00:51:31 +1100 NNTP-Posting-Host: 203.14.30.196 X-Complaints-To: abuse@telstra.net X-Trace: nsw.nnrp.telstra.net 977233872 203.14.30.196 (Wed, 20 Dec 2000 00:51:12 EST) NNTP-Posting-Date: Wed, 20 Dec 2000 00:51:12 EST Organization: Customer of Telstra Big Pond Direct Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!sjc1.nntp.concentric.net!newsfeed.concentric.net!newsfeed.ozemail.com.au!nsw.nnrp.telstra.net!news1.idx.com.au!tntwc01-3-110.idx.com.au Xref: chonsp.franklin.ch comp.arch.fpga:3374 Hi Eric, You may wish to consider the new, low cost BED-SPARTAN2+ FPGA Protoyping Kit from Burch Electronic Designs http://www.burched.com.au (Also see announcement posted on this group "New 200K gate, low cost FPGA proto kit") There are also some very neat Plug-On Modules that may be appropriate for you project: - BED-SRAM (2 MBit) - BED-FPGA-CPU-IO (for computer architecture experimenters) - BED-7SEG-DISPLAYS - BED-DIP-SWITCH See http://www.burched.com.au/products.html The Xilinx Webpack software CD comes in the box with the kit. Great free software, no license required! Supports Spartan II. You can also download this software for free from the Xilinx website. 200K gates is alot of gates :) Quite suitable for some serious computer architecture investigation, and for implementing your own RISC CPUs. As an aside, here's a link with some great work from the highly esteemed Jan Gray: http://www.fpgacpu.org Well worth a visit to this site. Good luck with your project! Best regards Tony Burch www.BurchED.com.au wrote in message news:91mdlq$pi6$1@nnrp1.deja.com... > I recently worked on a senior project where we designed a 16-bit RISC > microprocessor, and implemented the design in an FPGA. I'd like to be > able to do something similar on my own, and I'm trying to find a good > FPGA/board combination that is (relatively) affordable, and compatible > with the Xilinx student edition software. If anyone has any suggestions, > they would be greatly appreciated. > > Thanks, > Eric Hoyt > > > Sent via Deja.com > http://www.deja.com/ ###### Message-ID: <3A3FA329.C726271@jetnet.ab.ca> Date: Tue, 19 Dec 2000 11:04:25 -0700 From: Ben Franchuk X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.15 i586) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? References: <91mdlq$pi6$1@nnrp1.deja.com> <3A3FF921.5E35A296@unique-id.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 207.153.6.40 X-Trace: 19 Dec 2000 20:39:49 -0700, 207.153.6.40 Organization: OA Internet Lines: 14 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!west2.newsfeed.sprint-canada.net!news.oanet.com!207.153.6.40 Xref: chonsp.franklin.ch comp.arch.fpga:3420 Simon Gornall wrote: > > I may end up buying a BED board as well (just to get the gates :-) but > I'll need to figure out how easy/stable it is when you get rid of the > 24MHz clock. Presumably there's a good reason why they've crippled it > like this - maybe it just doesn't run any faster. I guess I'll find > out when I buy one. This could be for VGA output. One clock does all. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk ###### Message-ID: <3A3FF921.5E35A296@unique-id.com> From: Simon Gornall X-Mailer: Mozilla 4.75 [en] (X11; U; Linux 2.2.17-21mdk i686) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? References: <91mdlq$pi6$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 36 Date: Wed, 20 Dec 2000 00:11:13 +0000 NNTP-Posting-Host: 195.44.209.108 X-Trace: news2-hme0 977272734 195.44.209.108 (Wed, 20 Dec 2000 00:38:54 GMT) NNTP-Posting-Date: Wed, 20 Dec 2000 00:38:54 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!newsfeed00.sul.t-online.de!t-online.de!colt.net!newspeer.clara.net!news.clara.net!peernews!peer.cwci.net!news2-hme0.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3432 hoyte@ucsu.colorado.edu wrote: > > I recently worked on a senior project where we designed a 16-bit RISC > microprocessor, and implemented the design in an FPGA. I'd like to be > able to do something similar on my own, and I'm trying to find a good > FPGA/board combination that is (relatively) affordable, and compatible > with the Xilinx student edition software. If anyone has any suggestions, > they would be greatly appreciated. > Hi Eric, i think it's probably a good thing to point out that the previous 2 posts are from people who want to sell you stuff. I've just bought the XS40 and I'm happy with it. The XS40 is pretty good for prototyping stuff with. It has a 100MHz clock, but only ~5000 gates (advertised at ~9000 by Xilinx, but that's misleading IMHO). The BED board is pretty cool in that it has loadsagates (200,000), which is a *lot* to play with. For some weird reason they've only put a ~24MHz clock on it though. Ruins it for me. YMMV. I may end up buying a BED board as well (just to get the gates :-) but I'll need to figure out how easy/stable it is when you get rid of the 24MHz clock. Presumably there's a good reason why they've crippled it like this - maybe it just doesn't run any faster. I guess I'll find out when I buy one. All IMHO, of course. Simon -- Physicists get hadrons! ###### From: sulimma@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? Date: Wed, 20 Dec 2000 10:37:43 GMT Organization: Deja.com Lines: 24 Message-ID: <91q25n$mfh$1@nnrp1.deja.com> References: <91mdlq$pi6$1@nnrp1.deja.com> <3A3FF921.5E35A296@unique-id.com> <3A3FA329.C726271@jetnet.ab.ca> NNTP-Posting-Host: 141.2.84.221 X-Article-Creation-Date: Wed Dec 20 10:37:43 2000 GMT X-Http-User-Agent: Mozilla/4.74 [en] (X11; U; Linux 2.3.99-pre1 i686) X-Http-Proxy: 1.0 x71.deja.com:80 (Squid/1.1.22) for client 141.2.84.221 X-MyDeja-Info: XMYDJUIDsulimma Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3429 In article <3A3FA329.C726271@jetnet.ab.ca>, Ben Franchuk wrote: > Simon Gornall wrote: > > I'll need to figure out how easy/stable it is when you get rid of the > > 24MHz clock. Presumably there's a good reason why they've crippled it > > like this > > This could be for VGA output. One clock does all. As would a 48 MHz or 96 Mhz or 144 MHz Clock. So they really might have a problem with the power supply or similar. I use the ICS525-01 together with a bunch of DIP switches. This gives me whatever clock I want (some kHz to 160MHz) from a single crystal. You should be able to pathe this to the BED board. CU, Kolja Sent via Deja.com http://www.deja.com/ ###### From: harveytwyman@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? Date: Wed, 20 Dec 2000 10:51:37 GMT Organization: Deja.com Lines: 42 Message-ID: <91q2vo$n5g$1@nnrp1.deja.com> References: <91mdlq$pi6$1@nnrp1.deja.com> NNTP-Posting-Host: 194.82.103.40 X-Article-Creation-Date: Wed Dec 20 10:51:37 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.5; Windows 95) X-Http-Proxy: 1.0 wwwcache1.ukc.ac.uk:3128 (Squid/2.2.STABLE3), 1.0 jalapeno.ulcc.wwwcache.ja.net:8080 (Squid/2.2.STABLE5-hno.20000202), 1.0 x65.deja.com:80 (Squid/1.1.22) for client 129.12.50.213, 129.12.1.65, 194.82.103.40 X-MyDeja-Info: XMYDJUIDharveytwyman Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!nntp-out.monmouth.com!newspeer.monmouth.com!feed2.onemain.com!feed1.onemain.com!feeder.qis.net!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3431 I'm currently working on a teaching board that contains an Altera Flex 10K FPGA and a PIC16F877 processor. I have a Web Page describing it in detail: http://www.Makaton-Signs.org.uk/uPL-Trainer -- ___________________________________________ ===| |=== ===| H A R V E Y T W Y M A N |=== ===| ----------------------------------------- |=== ===| Department of Electronics, |=== ===| University of Kent. |=== ===| Canterbury. U.K. |=== ===| ----------------------------------------- |=== ===| ABOUT ME: http://www.Twyman.org.uk/CV.htm |=== ===| ----------------------------------------- |=== ===| EMAIL ME: H.E.Twyman@ukc.ac.uk |=== ===|___________________________________________|=== In article <91mdlq$pi6$1@nnrp1.deja.com>, hoyte@ucsu.colorado.edu wrote: > I recently worked on a senior project where we designed a 16-bit RISC > microprocessor, and implemented the design in an FPGA. I'd like to be > able to do something similar on my own, and I'm trying to find a good > FPGA/board combination that is (relatively) affordable, and compatible > with the Xilinx student edition software. If anyone has any suggestions, > they would be greatly appreciated. > > Thanks, > Eric Hoyt > > Sent via Deja.com > http://www.deja.com/ > Sent via Deja.com http://www.deja.com/ ###### Path: chonsp.franklin.ch!not-for-mail From: Neil Franklin Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? Date: 20 Dec 2000 21:34:48 +0100 Organization: My own Private Self Lines: 36 Message-ID: <6uelz2rfvb.fsf@chonsp.franklin.ch> References: <91mdlq$pi6$1@nnrp1.deja.com> <3A3FF921.5E35A296@unique-id.com> <3A3FA329.C726271@jetnet.ab.ca> <91q25n$mfh$1@nnrp1.deja.com> NNTP-Posting-Host: chonsp.franklin.ch X-Trace: chonsp.franklin.ch 977344488 1329 10.0.3.2 (20 Dec 2000 20:34:48 GMT) X-Complaints-To: news@chonsp.franklin.ch NNTP-Posting-Date: 20 Dec 2000 20:34:48 GMT X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: chonsp.franklin.ch comp.arch.fpga:3452 sulimma@my-deja.com writes: > In article <3A3FA329.C726271@jetnet.ab.ca>, > Ben Franchuk wrote: > > Simon Gornall wrote: > > > I'll need to figure out how easy/stable it is when you get rid of > the > > > 24MHz clock. Presumably there's a good reason why they've crippled > it > > > like this Cheaper clock chip? This is after all only the default "good for most users" chip, which can be replaced by "we want max power" users. Also don't forget that the XC2S chips like the XCV have 4 on-chip DLLs which can do f*2 and of which pairs can be cascaded (App note says so). So you can go up to 96MHz with that default Osc. > > This could be for VGA output. One clock does all. > As would a 48 MHz or 96 Mhz or 144 MHz Clock. So they really might > have a problem with the power supply or similar. The post from Burch also mentioned expansion boards. One of these has an VGA connector and 3*4bit DACs on it. That board also has an second 24MHz Osc (and an 3.xxxMHz for the RS 232 on it). So the 24MHz on the main board is not for VGA. Hmmm. Having 24MHz for the VGA board would make reducing inventory positions an further reason for an 24MHz default. Given that Burch seems to be aiming for absolute minimal cost that could be it. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic ###### From: "Tony Burch" Newsgroups: comp.arch.fpga References: <91mdlq$pi6$1@nnrp1.deja.com> <3A3FF921.5E35A296@unique-id.com> <3A3FA329.C726271@jetnet.ab.ca> <91q25n$mfh$1@nnrp1.deja.com> <6uelz2rfvb.fsf@chonsp.franklin.ch> Subject: Re: FPGA and Board for Microprocessor Design? Lines: 68 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 X-Original-NNTP-Posting-Host: idxwc07-47.idx.com.au Message-ID: <3a418788@news1.idx.com.au> Date: Thu, 21 Dec 2000 15:20:59 +1100 NNTP-Posting-Host: 203.14.30.196 X-Complaints-To: abuse@telstra.net X-Trace: nsw.nnrp.telstra.net 977372443 203.14.30.196 (Thu, 21 Dec 2000 15:20:43 EST) NNTP-Posting-Date: Thu, 21 Dec 2000 15:20:43 EST Organization: Customer of Telstra Big Pond Direct Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.mathworks.com!intgwlon.nntp.telstra.net!nsw.nnrp.telstra.net!news1.idx.com.au!idxwc07-47.idx.com.au Xref: chonsp.franklin.ch comp.arch.fpga:3455 Neil, You are right-on! We didn't need to put a higher frequency osc module on the kit because of the Spartan II on-chip DLLs - they are used to multiply up the clock on chip if necessary. No problem with the power supply, or supply decoupling. Indeed, one of the reasons the 24MHz was chosen was because of rationalising the inventory (a 24MHz osc module is also included with the BED-FPGA-CPU-IO kit). The BED-FPGA-CPU-IO module can also plug onto the other BED FPGA proto kits, which don't always have a 24MHz oscillator on them. So in alot of cases it is not redundant. Please note that BurchED is a small enough company that we will consider all requests such as "can you ship the kit with a different frequency oscillator module?". We are always happy to receive requests - just email me. Best regards and seasons greetings Tony www.BurchED.com.au "Neil Franklin" wrote in message news:6uelz2rfvb.fsf@chonsp.franklin.ch... > sulimma@my-deja.com writes: > > > In article <3A3FA329.C726271@jetnet.ab.ca>, > > Ben Franchuk wrote: > > > Simon Gornall wrote: > > > > I'll need to figure out how easy/stable it is when you get rid of > > the > > > > 24MHz clock. Presumably there's a good reason why they've crippled > > it > > > > like this > > Cheaper clock chip? This is after all only the default "good for most > users" chip, which can be replaced by "we want max power" users. > > Also don't forget that the XC2S chips like the XCV have 4 on-chip DLLs > which can do f*2 and of which pairs can be cascaded (App note says > so). So you can go up to 96MHz with that default Osc. > > > > > This could be for VGA output. One clock does all. > > As would a 48 MHz or 96 Mhz or 144 MHz Clock. So they really might > > have a problem with the power supply or similar. > > The post from Burch also mentioned expansion boards. One of these has > an VGA connector and 3*4bit DACs on it. That board also has an second > 24MHz Osc (and an 3.xxxMHz for the RS 232 on it). So the 24MHz on the > main board is not for VGA. > > Hmmm. Having 24MHz for the VGA board would make reducing inventory > positions an further reason for an 24MHz default. Given that Burch > seems to be aiming for absolute minimal cost that could be it. > > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic ###### From: msimon@xta.com (M. Simon) Newsgroups: comp.arch.fpga Subject: Re: FPGA and Board for Microprocessor Design? Message-ID: <3a42720c.32009556@news.xta.com> References: <91mdlq$pi6$1@nnrp1.deja.com> X-Newsreader: Forte Free Agent 1.11/32.235 Lines: 13 Date: Thu, 21 Dec 2000 21:12:30 GMT NNTP-Posting-Host: 209.83.110.33 X-Complaints-To: abuse@alpha.net X-Trace: homer.alpha.net 977433220 209.83.110.33 (Thu, 21 Dec 2000 15:13:40 CST) NNTP-Posting-Date: Thu, 21 Dec 2000 15:13:40 CST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!newspump.sol.net!news.execpc.com!newspeer.sol.net!homer.alpha.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3470 Take a look at my site below: Let me know if you have questions. M. Simon Space-Time Productions http://www.spacetimepro.com Free CNC Machine Control Software Free Source Code Control the World From a Parallel Port