Message-ID: <3A3F3339.AC12CB9E@sqf.hp.com> Date: Tue, 19 Dec 2000 10:06:49 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: 3V -> 5V clock signal level conversion Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 19 Dec 2000 10:06:49 GMT, hpqt0797.sqf.hp.com Lines: 29 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 19 Dec 2000 03:07:16 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!feed2.news.rcn.net!rcn!news2.best.com!news1.best.com!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3363 I'm looking at a problem where we need to drive a couple of 5V CMOS clock inputs from a SpartanII 3v output. There are data lines being driven from the 3V output, we can get away with the 'tristate and pull high for logic high' trick, but I don't want to do this with the clock signals. The active (rising) edges are _very_ slow and the risk of double clocking etc would be too high. Space is fairly tight so my immediate thought was to use an 8 pin soic dual comparator with the -ve input tied to 1.8V (power plane). My only concern with this is that I think I read a while ago that comparators shouldn't be used for this sort of application, I can't remember where I read this so I can't check if I'm right. It might have been because of the lask of hysteresis on the input, but if the -ve input is set to a 'clean' part of the waveform I don't think we should see any problems. Can anyone think of any drawbacks of using a fast comparator for this conversion? Nial. ###### From: Tomppa Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 11:02:02 GMT Organization: Deja.com Lines: 56 Message-ID: <91nf77$i8o$1@nnrp1.deja.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> NNTP-Posting-Host: 213.138.128.36 X-Article-Creation-Date: Tue Dec 19 11:02:02 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.5; Windows 95; TUCOWS) X-Http-Proxy: 1.1 netapp (NetCache 4.1R1), 1.0 x51.deja.com:80 (Squid/1.1.22) for client 141.192.20.245, 213.138.128.36 X-MyDeja-Info: XMYDJUIDapsku Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!fu-berlin.de!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3377 Hi, You could use HCT- logic since it's inputs high-state is about 2.4V. I read this at some manufactures datasheets so that should be ok. At least Philips (and maybe others) have single logic ports in one tiny package (picogate). If your clock inputs are allready TTL- compatible, there's no problem to drive those signals directly. I have used this method in my mp3 player (still proto) where the decoder works with 3.3V and the dac (CS4334) needs 5V supply. According to dac's datasheets it's inputs are TTL-compatible. Works fine! Hope this helps. Tommi In article <3A3F3339.AC12CB9E@sqf.hp.com>, nials@sqf.hp.com wrote: > I'm looking at a problem where we need to drive a > couple of 5V CMOS clock inputs from a SpartanII > 3v output. > > There are data lines being driven from the 3V output, > we can get away with the 'tristate and pull high > for logic high' trick, but I don't want to do this with > the clock signals. The active (rising) edges are > _very_ slow and the risk of double clocking etc > would be too high. > > Space is fairly tight so my immediate thought was > to use an 8 pin soic dual comparator with the -ve > input tied to 1.8V (power plane). > > My only concern with this is that I think I read a > while ago that comparators shouldn't be used for this > sort of application, I can't remember where I read this > so I can't check if I'm right. It might have been > because of the lask of hysteresis on the input, > but if the -ve input is set to a 'clean' part > of the waveform I don't think we should see > any problems. > > Can anyone think of any drawbacks of using a fast > comparator for this conversion? > > Nial. > Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A3F61AA.13A69394@sqf.hp.com> Date: Tue, 19 Dec 2000 13:24:58 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91nf77$i8o$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 19 Dec 2000 13:24:58 GMT, hpqt0797.sqf.hp.com Lines: 15 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 19 Dec 2000 06:25:25 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3362 Tomppa wrote: > You could use HCT- logic since it's inputs high-state > is about 2.4V. I read this at some manufactures datasheets > so that should be ok. At least Philips (and maybe others) > have single logic ports in one tiny package (picogate). Vinhigh for these two signals is 3.5V, and we're getting a 'glitch' at ~2.4V that would cause double clocking if that was the threshold. I also don't think you can get any 74XX series devices in an 8 pin package. Nial. ###### From: Søren A.Møller Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 15:22:31 +0100 Organization: SAMtronic Lines: 25 Message-ID: References: <3A3F3339.AC12CB9E@sqf.hp.com> <91nf77$i8o$1@nnrp1.deja.com> <3A3F61AA.13A69394@sqf.hp.com> NNTP-Posting-Host: cpe.atm0-0-0-152117.boanxx3.customer.tele.dk X-Trace: news.inet.tele.dk 977235644 26764 194.192.106.170 X-Complaints-To: the appropriate department of the poster's provider X-Newsreader: MicroPlanet Gravity v2.30 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!news.tele.dk!Tele.Dk.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3395 In article <3A3F61AA.13A69394@sqf.hp.com>, nials@sqf.hp.com says... > Tomppa wrote: > > > You could use HCT- logic since it's inputs high-state > > is about 2.4V. I read this at some manufactures datasheets > > so that should be ok. At least Philips (and maybe others) > > have single logic ports in one tiny package (picogate). > > Vinhigh for these two signals is 3.5V, and we're getting > a 'glitch' at ~2.4V that would cause double clocking if that > was the threshold. > > I also don't think you can get any 74XX series devices in an > 8 pin package. No, but you can get them in SOT23-5 and SC70-5 from e.g. TI: http://www-s.ti.com/cgi-bin/sc/family3.cgi?family=SINGLE-GATES or Fairchild (they have some in US-8): http://www.fairchildsemi.com/products/logic/tinylogic/ or Philips: http://www.philipslogic.com/products/picogate/ http://www.philipslogic.com/products/picogate/overview/ or Toshiba or On-semi and probably others. Søren A.Møller ###### From: Greg Neff Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 16:15:55 GMT Organization: Deja.com Lines: 27 Message-ID: <91o1jh$17h$1@nnrp1.deja.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> NNTP-Posting-Host: 216.192.102.8 X-Article-Creation-Date: Tue Dec 19 16:15:55 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 SERVER, 1.0 x58.deja.com:80 (Squid/1.1.22) for client 216.192.102.8 X-MyDeja-Info: XMYDJUIDgregneff Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3376 In article <3A3F3339.AC12CB9E@sqf.hp.com>, nials@sqf.hp.com wrote: > I'm looking at a problem where we need to drive a > couple of 5V CMOS clock inputs from a SpartanII > 3v output. > (snip) I like to have a reel of these on hand: http://www.fairchildsemi.com/pf/NC/NC7ST86.html They can be used as inverters or buffers, depending on how you strap the other input. Other manufacturers (such as Toshiba) make similar parts. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ ###### From: Peter Alfke Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 09:07:42 -0800 Organization: Xilinx Lines: 24 Message-ID: <3A3F95DF.2876800A@xilinx.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91nf77$i8o$1@nnrp1.deja.com> <3A3F61AA.13A69394@sqf.hp.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!newsfeed.mathworks.com!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3367 I am sure that the reborn Fairchild ( I am an old Fairchilder of 30 years ago!) has circuits with an input threshold of 2.4 V and available in really tiny packages. Peter Alfke Nial Stewart wrote: > Tomppa wrote: > > > You could use HCT- logic since it's inputs high-state > > is about 2.4V. I read this at some manufactures datasheets > > so that should be ok. At least Philips (and maybe others) > > have single logic ports in one tiny package (picogate). > > Vinhigh for these two signals is 3.5V, and we're getting > a 'glitch' at ~2.4V that would cause double clocking if that > was the threshold. > > I also don't think you can get any 74XX series devices in an > 8 pin package. > > Nial. ###### Message-ID: <3A3F99A7.2A9E3931@earthlink.net> From: Robert X-Mailer: Mozilla 4.5 [en] (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 39 Date: Tue, 19 Dec 2000 17:25:37 GMT NNTP-Posting-Host: 38.30.131.72 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 977246737 38.30.131.72 (Tue, 19 Dec 2000 09:25:37 PST) NNTP-Posting-Date: Tue, 19 Dec 2000 09:25:37 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!xfer13.netnews.com!netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3390 Greg Neff wrote: > In article <3A3F3339.AC12CB9E@sqf.hp.com>, > nials@sqf.hp.com wrote: > > I'm looking at a problem where we need to drive a > > couple of 5V CMOS clock inputs from a SpartanII > > 3v output. > > > (snip) > > I like to have a reel of these on hand: > > http://www.fairchildsemi.com/pf/NC/NC7ST86.html > > They can be used as inverters or buffers, depending on how you strap > the other input. > > Other manufacturers (such as Toshiba) make similar parts. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > Greg, This is a super suggestion, but I would use the dual Schmitt trigger: http://www.fairchildsemi.com/pf/NC/NC7WZ14.html Total input protection against power down as well as ESD, absolutely tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still use a nominal RC on input though. The threshold spec extremes stink- so he would need a pull-up. ###### Message-ID: <3A3F9EF8.DA0F24A7@sqf.hp.com> Date: Tue, 19 Dec 2000 17:46:32 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 19 Dec 2000 17:46:33 GMT, hpqt0797.sqf.hp.com Lines: 33 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 19 Dec 2000 10:46:59 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!enews.sgi.com!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3364 Jason Daughenbaugh wrote: > > "There are data lines being driven from the 3V output, > we can get away with the 'tristate and pull high > for logic high' trick, but I don't want to do this with > the clock signals. The active (rising) edges are > _very_ slow and the risk of double clocking etc > would be too high." > > Something worth considering would be a modified version > of this method. I have had great success driving a clock > line by configuring the logic so that it drives the output > pad high until it is a high level and then tristate and let > the pullup work the rest. This allows the output to be > driven all of the way up to 3V, creating some much faster > slew rates. > > Xilinx clains that this can decrease the rise time from > 0.4 to 3.0V from 20ns to 3ns. I have seen this to be true > on a spartan-2 The threshold Vin low for the chip I'm clocking is 3.5V. I've implemented the technique above (and increased the 'DRIVE' property on the CLk output pins). It's working on the bench, but I'm not happy with the slope of the signals as they pass through the high input voltage threshold, it needs to be more robust. I really want to drive the input with something that'll take the input cleanly through 3.5V. Nial. ###### Message-ID: <3A3FA128.682262F5@sqf.hp.com> Date: Tue, 19 Dec 2000 17:55:52 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 19 Dec 2000 17:55:52 GMT, hpqt0797.sqf.hp.com Lines: 17 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 19 Dec 2000 10:56:19 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!enews.sgi.com!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3360 Robert wrote: > > Greg, > > This is a super suggestion, but I would use the dual Schmitt trigger: > http://www.fairchildsemi.com/pf/NC/NC7WZ14.html > > Total input protection against power down as well as ESD, absolutely > tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still use > a nominal RC on input though. The threshold spec extremes stink- so he > would need a pull-up. Thanks for the suggestions guys, I'll get the guy who's designing the board to have a look at this. Nial. ###### From: Greg Neff Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 18:03:11 GMT Organization: Deja.com Lines: 33 Message-ID: <91o7so$7as$1@nnrp1.deja.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> NNTP-Posting-Host: 216.192.102.8 X-Article-Creation-Date: Tue Dec 19 18:03:11 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 SERVER, 1.0 x70.deja.com:80 (Squid/1.1.22) for client 216.192.102.8 X-MyDeja-Info: XMYDJUIDgregneff Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!fu-berlin.de!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3380 In article <3A3F99A7.2A9E3931@earthlink.net>, Robert wrote: (snip) > > This is a super suggestion, but I would use the dual Schmitt trigger: > http://www.fairchildsemi.com/pf/NC/NC7WZ14.html > > Total input protection against power down as well as ESD, absolutely > tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still use > a nominal RC on input though. The threshold spec extremes stink- so he > would need a pull-up. > > Just one caveat: With Xilinx FPGAs you need to be careful about using output pullup resistors to drive CMOS inputs. Many of the I/O configurations are not 5V tolerant. The non-5V tolerant output configurations will actively clamp the output to VCCO plus a diode. The OP is probably using LVTTL mode, and if this is the case then your suggestion is okay. We have to be careful not to generalize when dealing with Xilinx FPGAs. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A3FA882.51138D7E@earthlink.net> From: Robert X-Mailer: Mozilla 4.5 [en] (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 31 Date: Tue, 19 Dec 2000 18:28:59 GMT NNTP-Posting-Host: 38.30.131.72 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 977250539 38.30.131.72 (Tue, 19 Dec 2000 10:28:59 PST) NNTP-Posting-Date: Tue, 19 Dec 2000 10:28:59 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.skycache.com!Cidera!xfer10.netnews.com!netnews.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3389 Greg Neff wrote: > In article <3A3F99A7.2A9E3931@earthlink.net>, > Robert wrote: > (snip) > > > > This is a super suggestion, but I would use the dual Schmitt trigger: > > http://www.fairchildsemi.com/pf/NC/NC7WZ14.html > > > > Total input protection against power down as well as ESD, absolutely > > tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still > use > > a nominal RC on input though. The threshold spec extremes stink- so he > > would need a pull-up. > > > > > > Just one caveat: With Xilinx FPGAs you need to be careful about using > output pullup resistors to drive CMOS inputs. Many of the I/O > configurations are not 5V tolerant. The non-5V tolerant output > configurations will actively clamp the output to VCCO plus a diode. The > OP is probably using LVTTL mode, and if this is the case then your > suggestion is okay. We have to be careful not to generalize when > dealing with Xilinx FPGAs. This is good to know, and a good point. I was talking about pull-ups on the input though. ###### Message-ID: <3A3FAAC9.ACDDAFFE@earthlink.net> From: Robert X-Mailer: Mozilla 4.5 [en] (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 37 Date: Tue, 19 Dec 2000 18:38:49 GMT NNTP-Posting-Host: 38.30.131.72 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 977251129 38.30.131.72 (Tue, 19 Dec 2000 10:38:49 PST) NNTP-Posting-Date: Tue, 19 Dec 2000 10:38:49 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!news-out.usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3392 I see what you are saying now. His source is 3V logic from a Spartan II. Keen observation. Greg Neff wrote: > In article <3A3F99A7.2A9E3931@earthlink.net>, > Robert wrote: > (snip) > > > > This is a super suggestion, but I would use the dual Schmitt trigger: > > http://www.fairchildsemi.com/pf/NC/NC7WZ14.html > > > > Total input protection against power down as well as ESD, absolutely > > tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still > use > > a nominal RC on input though. The threshold spec extremes stink- so he > > would need a pull-up. > > > > > > Just one caveat: With Xilinx FPGAs you need to be careful about using > output pullup resistors to drive CMOS inputs. Many of the I/O > configurations are not 5V tolerant. The non-5V tolerant output > configurations will actively clamp the output to VCCO plus a diode. The > OP is probably using LVTTL mode, and if this is the case then your > suggestion is okay. We have to be careful not to generalize when > dealing with Xilinx FPGAs. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com > http://www.deja.com/ ###### From: Greg Neff Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 19:00:27 GMT Organization: Deja.com Lines: 57 Message-ID: <91ob84$aog$1@nnrp1.deja.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> <3A3FA882.51138D7E@earthlink.net> NNTP-Posting-Host: 216.192.102.8 X-Article-Creation-Date: Tue Dec 19 19:00:27 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 SERVER, 1.0 x69.deja.com:80 (Squid/1.1.22) for client 216.192.102.8 X-MyDeja-Info: XMYDJUIDgregneff Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3378 In article <3A3FA882.51138D7E@earthlink.net>, Robert wrote: > > > Greg Neff wrote: > > > In article <3A3F99A7.2A9E3931@earthlink.net>, > > Robert wrote: > > (snip) > > > > > > This is a super suggestion, but I would use the dual Schmitt trigger: > > > http://www.fairchildsemi.com/pf/NC/NC7WZ14.html > > > > > > Total input protection against power down as well as ESD, absolutely > > > tiny package, lightning fast, 1.8-5.5Vcc, 1V hysteresis- would still > > use > > > a nominal RC on input though. The threshold spec extremes stink- so he > > > would need a pull-up. > > > > > > > > > > Just one caveat: With Xilinx FPGAs you need to be careful about using > > output pullup resistors to drive CMOS inputs. Many of the I/O > > configurations are not 5V tolerant. The non-5V tolerant output > > configurations will actively clamp the output to VCCO plus a diode. The > > OP is probably using LVTTL mode, and if this is the case then your > > suggestion is okay. We have to be careful not to generalize when > > dealing with Xilinx FPGAs. > > This is good to know, and a good point. I was talking about pull-ups on the > input though. > > The NC7WZ14 input would be driven by the FPGA output, so the pullup would source current to both the NC7WZ14 input, and the FPGA output driver and protection circuit. This is why I made the comment. My "output pullup resistor" statement was probably a bad choice of words. Sorry for the confusion. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A3FB450.668A606A@sqf.hp.com> Date: Tue, 19 Dec 2000 19:17:36 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 19 Dec 2000 19:17:36 GMT, hpqt0797.sqf.hp.com Lines: 21 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 19 Dec 2000 12:18:02 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!news-hog.berkeley.edu!ucberkeley!enews.sgi.com!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3361 Greg Neff wrote: > > a nominal RC on input though. The threshold spec extremes stink- so he > > would need a pull-up. > > > > > > Just one caveat: With Xilinx FPGAs you need to be careful about using > output pullup resistors to drive CMOS inputs. Many of the I/O > configurations are not 5V tolerant. The non-5V tolerant output > configurations will actively clamp the output to VCCO plus a diode. The > OP is probably using LVTTL mode, and if this is the case then your > suggestion is okay. We have to be careful not to generalize when > dealing with Xilinx FPGAs. > Greg, it's a Spartan II so using a pull up on the op is OK, it's not actively clamped. Nial. ###### From: Peter Alfke Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 11:03:22 -0800 Organization: Xilinx Lines: 13 Message-ID: <3A3FB0FA.82934627@xilinx.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> <3A3FA882.51138D7E@earthlink.net> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: Robert Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!feeder.qis.net!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3405 Robert wrote > > This is good to know, and a good point. I was talking about pull-ups on the > input though. Every input is also a 3-stated output. There are hardly any dedicated inputs ! Peter Alfke ###### From: Greg Neff Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 20:51:13 GMT Organization: Deja.com Lines: 41 Message-ID: <91ohnv$go9$1@nnrp1.deja.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> <3A3FB450.668A606A@sqf.hp.com> NNTP-Posting-Host: 216.192.102.8 X-Article-Creation-Date: Tue Dec 19 20:51:13 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 SERVER, 1.0 x58.deja.com:80 (Squid/1.1.22) for client 216.192.102.8 X-MyDeja-Info: XMYDJUIDgregneff Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3408 In article <3A3FB450.668A606A@sqf.hp.com>, nials@sqf.hp.com wrote: > Greg Neff wrote: > > > > a nominal RC on input though. The threshold spec extremes stink- so he > > > would need a pull-up. > > > > > > > > > > Just one caveat: With Xilinx FPGAs you need to be careful about using > > output pullup resistors to drive CMOS inputs. Many of the I/O > > configurations are not 5V tolerant. The non-5V tolerant output > > configurations will actively clamp the output to VCCO plus a diode. The > > OP is probably using LVTTL mode, and if this is the case then your > > suggestion is okay. We have to be careful not to generalize when > > dealing with Xilinx FPGAs. > > > > Greg, it's a Spartan II so using a pull up on the op is > OK, it's not actively clamped. > > Nial. > Take a look at page 4 of the Spartan II data sheet (V1.1). It says that for non-5V compliant outputs, a clamp diode may be connected to VCCO. So to be safe, make sure that you are using a 5V compliant output mode such as LVTTL. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A3FF494.5C2CFD35@dspmedia.com.au> Date: Wed, 20 Dec 2000 09:51:48 +1000 From: Garry Allen X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91nf77$i8o$1@nnrp1.deja.com> <3A3F61AA.13A69394@sqf.hp.com> <3A3F95DF.2876800A@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 16 NNTP-Posting-Host: 198.142.201.103 X-Trace: 977266263 news01.syd.optusnet.com.au 7488 198.142.201.103 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news-fra1.dfn.de!news-koe1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!xfer13.netnews.com!netnews.com!newshub2.rdc1.sfba.home.com!news.home.com!sjc1.nntp.concentric.net!newsfeed.concentric.net!newsfeed.ozemail.com.au!news1.optus.net.au!optus!news1.mpx.com.au.MISMATCH!news01.syd.optusnet.com.au!nnrp01.syd.optusnet.com.au!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3435 Peter Alfke wrote: > > I am sure that the reborn Fairchild ( I am an old Fairchilder of 30 > years ago!) has circuits with an input threshold of 2.4 V and > available in really tiny packages. > > Peter Alfke > Fairchild has at least AHCT available in single gate (didn't they buy TIs logic?) (as does Philips) e.g. 74AHCT1G14GW - single gate inverter with hysteresis. these are more expensive than the larger chips but work well Garry Allen It is also worth downloading the TI logic family application notes. Level conversion is one thing they spend a lot of time discussing. ###### From: Kent Orthner Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: 20 Dec 2000 11:57:52 +0900 Organization: ... Lines: 71 Sender: korthner@KENT Message-ID: References: <3A3F3339.AC12CB9E@sqf.hp.com> NNTP-Posting-Host: dhcp237.inf.furukawa.co.jp X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Canyonlands" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!nntp.cs.ubc.ca!news.ksw.feedmania.org!nf1.xephion.ne.jp!fintnews!ifnews!inf-gw!postmaster Xref: chonsp.franklin.ch comp.arch.fpga:3443 Nial, Something else you *might* consider (I don't know how fast your clock is, or how fast a rising edge you need) is using the FPGA to pull up to a 3.3v level, and then tristating, letting the resistor pull it up the ret of the way. I think this solution comes from Peter Afke, but I'm not sure. The VHDL process to drive your pins would be as follows, assuming that PIN is of type inout, and that OUTPUT is the output level that you want. process (PIN, OUTPUT) is begin if OUTPUT = '0' then PIN <= '0'; elsif PIN = '0' then -- This is when OUTPUT is '1, -- but PIN isn't there yet, so PIN <= '1'; -- you keep driving with the -- FPGA. else -- This is when PIN is above the -- the FPGA's Vih threshold, and PIN <= 'Z'; -- you let the resistor do the rest -- of the work. end if; end process; Disclaimer: I have not done this myself, and I don't know if it's a particularly good idea to do it with a clock signal. HTH, Kent. Nial Stewart writes: > I'm looking at a problem where we need to drive a > couple of 5V CMOS clock inputs from a SpartanII > 3v output. > > There are data lines being driven from the 3V output, > we can get away with the 'tristate and pull high > for logic high' trick, but I don't want to do this with > the clock signals. The active (rising) edges are > _very_ slow and the risk of double clocking etc > would be too high. > > > Space is fairly tight so my immediate thought was > to use an 8 pin soic dual comparator with the -ve > input tied to 1.8V (power plane). > > My only concern with this is that I think I read a > while ago that comparators shouldn't be used for this > sort of application, I can't remember where I read this > so I can't check if I'm right. It might have been > because of the lask of hysteresis on the input, > but if the -ve input is set to a 'clean' part > of the waveform I don't think we should see > any problems. > > Can anyone think of any drawbacks of using a fast > comparator for this conversion? > > Nial. ###### From: "Jim Pennell" Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Tue, 19 Dec 2000 19:46:13 -0800 Organization: MindSpring Enterprises Lines: 23 Message-ID: <91pa23$hgp$1@slb7.atl.mindspring.net> References: <3A3F3339.AC12CB9E@sqf.hp.com> Reply-To: "Jim Pennell" NNTP-Posting-Host: d1.6f.d4.19 X-Server-Date: 20 Dec 2000 03:46:11 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.bme.hu!news.tele.dk!128.230.129.106!news.maxwell.syr.edu!howland.erols.net!newsfeed.mindspring.net.MISMATCH!news.mindspring.net!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3442 Another possibility is the LT1016 chip... It is a fast comparator/TTL out device that we use with a 10 MHz clock and it works very nicely. There is a Texas Instrument equivalent that may be easier to get, although I forget the exact part number.... TI3016 or 3018 ??? I have used it for years, and it will work nicely to convert from 3.3 to 5 volt logic. Jim Pennell ======================= jpennell at ix.netcom.com ###### Message-ID: <3A406870.6212E94E@sqf.hp.com> Date: Wed, 20 Dec 2000 08:06:08 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <91o1jh$17h$1@nnrp1.deja.com> <3A3F99A7.2A9E3931@earthlink.net> <91o7so$7as$1@nnrp1.deja.com> <3A3FB450.668A606A@sqf.hp.com> <91ohnv$go9$1@nnrp1.deja.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 20 Dec 2000 08:06:08 GMT, hpqt0797.sqf.hp.com Lines: 23 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 20 Dec 2000 01:06:33 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!newsfeed1.online.no!nextra.com!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3411 Greg Neff wrote: > > > > > > > Greg, it's a Spartan II so using a pull up on the op is > > OK, it's not actively clamped. > > > > Nial. > > > > Take a look at page 4 of the Spartan II data sheet (V1.1). It says > that for non-5V compliant outputs, a clamp diode may be connected to > VCCO. So to be safe, make sure that you are using a 5V compliant > output mode such as LVTTL. > Should have said "Greg, it's a Spartan II so using a pull up on the op is OK _with out configuration (ie LVTTL)_ , it's not actively clamped". Nial. ###### From: Peter Alfke Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Wed, 20 Dec 2000 11:06:58 -0800 Organization: Xilinx Lines: 59 Message-ID: <3A410351.5A6ED19B@xilinx.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: Kent Orthner Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!sunqbc.risq.qc.ca!cpk-news-hub1.bbnplanet.com!news.gtei.net!nntp.abs.net!attmtf.ip.att.net!attla2!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3456 This is the way I normally describe it: Drive the internal OE signal with an internal 2-input NAND gate. One of its inputs is the same signal driving the output buffer, the other one comes from the input buffer that looks at the output pin we want to drive. If you drive a 0, the NAND output is High, output is active. When you change to driving a 1, the output will first still be below the threshold, so the output driver stays active for a while, giving us a fast rise time. When the output passes through the threshold, the NAND gate output will go Low, 3-stating the output, and leaving it up to the external pull-up resistor to finish the job. Clearly, it is in your interest to make the feedback signal into the NAND gate reasonably slow, not fast! Peter Alfke Kent Orthner wrote: > Nial, > > Something else you *might* consider (I don't know > how fast your clock is, or how fast a rising edge > you need) is using the FPGA to pull up to a 3.3v > level, and then tristating, letting the resistor > pull it up the ret of the way. > > I think this solution comes from Peter Afke, but > I'm not sure. > > The VHDL process to drive your pins would be as > follows, assuming that PIN is of type inout, and > that OUTPUT is the output level that you want. > > process (PIN, OUTPUT) is > begin > if OUTPUT = '0' then > > PIN <= '0'; > > elsif PIN = '0' then -- This is when OUTPUT is '1, > -- but PIN isn't there yet, so > PIN <= '1'; -- you keep driving with the > -- FPGA. > else -- This is when PIN is above the > -- the FPGA's Vih threshold, and > PIN <= 'Z'; -- you let the resistor do the rest > -- of the work. > end if; > end process; > > Disclaimer: I have not done this myself, and I > don't know if it's a particularly good idea to do it > with a clock signal. > > HTH, > Kent. > ###### From: "markp" Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Wed, 20 Dec 2000 21:34:17 -0000 Organization: UUNET WorldCom server (post doesn't reflect views of UUNET WorldCom Lines: 56 Message-ID: <91r88v$cqb$2@lure.pipex.net> References: <3A3F3339.AC12CB9E@sqf.hp.com> Reply-To: "markp" NNTP-Posting-Host: userdy33.uk.uudial.com X-Trace: lure.pipex.net 977347679 13131 62.188.8.225 (20 Dec 2000 21:27:59 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 20 Dec 2000 21:27:59 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!news.tele.dk!212.54.64.131!news100.image.dk!cass.news.pipex.net!pipex!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3477 "Nial Stewart" wrote in message news:3A3F3339.AC12CB9E@sqf.hp.com... > I'm looking at a problem where we need to drive a > couple of 5V CMOS clock inputs from a SpartanII > 3v output. > > There are data lines being driven from the 3V output, > we can get away with the 'tristate and pull high > for logic high' trick, but I don't want to do this with > the clock signals. The active (rising) edges are > _very_ slow and the risk of double clocking etc > would be too high. > I guess you mean open collector signals have slow rise times (which they usually do). I would suggest using totem pole clock output, series terminate with 50R or so into the input of a 74ACT device (e.g. 74ACT244), then series terminating from that gate to your CMOS clock input. I would also recommend stuffing your data through one of these too. Some of these devices are available in different speed grades, and some even define skew between signals. In my experience series terminating clocks is superior to other forms of clock termination, but I'll leave that can of worms to another thread! > > Space is fairly tight so my immediate thought was > to use an 8 pin soic dual comparator with the -ve > input tied to 1.8V (power plane). > The above devices are available in QSOP and TSSOP, so shouldn't be that much larger once all the discretes are taken into account > My only concern with this is that I think I read a > while ago that comparators shouldn't be used for this > sort of application, I can't remember where I read this > so I can't check if I'm right. It might have been > because of the lask of hysteresis on the input, > but if the -ve input is set to a 'clean' part > of the waveform I don't think we should see > any problems. > > Can anyone think of any drawbacks of using a fast > comparator for this conversion? I wouldn't use comparators for this - even fast ones are much slower than the logic equivalent and it is difficult if not impossible to control skew. I don't know what the impedance on the line would be as it crosses the threshold, but if it does change as Robert suggests then there could be unwanted reflections. I wouldn't take the risk with a clock! Mark. ###### Message-ID: <3A412CCF.6265005A@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <3A410351.5A6ED19B@xilinx.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 72 Date: Wed, 20 Dec 2000 22:01:52 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 977349712 24.13.238.93 (Wed, 20 Dec 2000 14:01:52 PST) NNTP-Posting-Date: Wed, 20 Dec 2000 14:01:52 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3461 WOrks as long as 1) you can tolerate the ringing that inevitably occurs when the driver shuts off, and 2) it is not a wired or bus like you might have with a processor bus control signal (transfer start in a motorola processor with multiple masters comes to mind). Peter Alfke wrote: > > This is the way I normally describe it: > Drive the internal OE signal with an internal 2-input NAND gate. > One of its inputs is the same signal driving the output buffer, the > other one comes from the input buffer that looks at the output pin > we want to drive. > If you drive a 0, the NAND output is High, output is active. > When you change to driving a 1, the output will first still be below > the threshold, so the output driver stays active for a while, giving > us a fast rise time. > When the output passes through the threshold, the NAND gate output > will go Low, 3-stating the output, and leaving it up to the external > pull-up resistor to finish the job. > Clearly, it is in your interest to make the feedback signal into the > NAND gate reasonably slow, not fast! > > Peter Alfke > > Kent Orthner wrote: > > > Nial, > > > > Something else you *might* consider (I don't know > > how fast your clock is, or how fast a rising edge > > you need) is using the FPGA to pull up to a 3.3v > > level, and then tristating, letting the resistor > > pull it up the ret of the way. > > > > I think this solution comes from Peter Afke, but > > I'm not sure. > > > > The VHDL process to drive your pins would be as > > follows, assuming that PIN is of type inout, and > > that OUTPUT is the output level that you want. > > > > process (PIN, OUTPUT) is > > begin > > if OUTPUT = '0' then > > > > PIN <= '0'; > > > > elsif PIN = '0' then -- This is when OUTPUT is '1, > > -- but PIN isn't there yet, so > > PIN <= '1'; -- you keep driving with the > > -- FPGA. > > else -- This is when PIN is above the > > -- the FPGA's Vih threshold, and > > PIN <= 'Z'; -- you let the resistor do the rest > > -- of the work. > > end if; > > end process; > > > > Disclaimer: I have not done this myself, and I > > don't know if it's a particularly good idea to do it > > with a clock signal. > > > > HTH, > > Kent. > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: Peter Alfke Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Wed, 20 Dec 2000 14:15:07 -0800 Organization: Xilinx Lines: 32 Message-ID: <3A412F6A.ACE1B0D6@xilinx.com> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91r88v$cqb$2@lure.pipex.net> Reply-To: peter.alfke@xilinx.com NNTP-Posting-Host: peter.xsj.xilinx.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7C-CCK-MCD {C-UDP; EBM-APPLE} (Macintosh; I; PPC) X-Accept-Language: en To: markp Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!newsfeed.mathworks.com!ptdnetP!newsgate.ptd.net!attmtf.ip.att.net!attla2!attla1!ip.att.net!newsgate.xilinx.com!cliff.xsj.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3460 markp wrote: > In my experience series terminating clocks is superior to other forms of > clock termination, but I'll leave that can of worms to another thread! > Series termination is great for signals that go from one source to one destination. Since the drive impdance is adjusted to match the transmission line Z0, a half-amplitude signal travels down the line, is reflected at the unterminated far end to become a full signal "instantaneously", then travels back to the source, where it is swallowed up in the output impedance = Z0. Neat trick. It USES the reflection instead of FIGHTING it. But beware: Never ever (NEVER EVER!) use series termination for a signal that has to travel to multiple destinations. All but the farthest of these destinations will see the half-amplitude signal for some time, which is the worst level possible. Poor noise immunity, double-triggering etc. Ugly stuff. The best way to terminate a clock that drives multiple loads is to have a strong ( low-impedance ) driver, then terminate the farthest end of the clock "snake" with a resistor (=Z0) in series with a capacitor to ground. (RC in SERIES, and this combination used as a parallel termination) Make the RC larger than the transition time, but smaller than the clock High or Low time. 50 Ohm and 100 pF is a proven combination for all but the very fastest clocks. Peter Alfke, Xilinx Applications ###### From: "markp" Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Thu, 21 Dec 2000 00:58:45 -0000 Organization: UUNET WorldCom server (post doesn't reflect views of UUNET WorldCom Lines: 42 Message-ID: <91rk6k$jnj$1@lure.pipex.net> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91r88v$cqb$2@lure.pipex.net> <3A412F6A.ACE1B0D6@xilinx.com> Reply-To: "markp" NNTP-Posting-Host: userds04.uk.uudial.com X-Trace: lure.pipex.net 977359892 20211 62.188.6.110 (21 Dec 2000 00:51:32 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 21 Dec 2000 00:51:32 GMT X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4522.1200 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!grot.news.pipex.net!pipex!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3478 Yes, I should have said 'series terminating clocks is superior to other forms of clock termination for point to point connections'. This is a subject in its own right, but off topic for this thread so I'll leave it at that! Mark. > Series termination is great for signals that go from one source to one > destination. > Since the drive impdance is adjusted to match the transmission line Z0, a > half-amplitude signal travels down the line, is reflected at the unterminated > far end to become a full signal "instantaneously", then travels back to the > source, where it is swallowed up in the output impedance = Z0. > > Neat trick. It USES the reflection instead of FIGHTING it. > > But beware: Never ever (NEVER EVER!) use series termination for a signal that > has to travel to multiple destinations. All but the farthest of these > destinations will see the half-amplitude signal for some time, which is the > worst level possible. Poor noise immunity, double-triggering etc. Ugly stuff. > > The best way to terminate a clock that drives multiple loads is to have a > strong ( low-impedance ) driver, then terminate the farthest end of the clock > "snake" with a resistor (=Z0) in series with a capacitor to ground. (RC in > SERIES, and this combination used as a parallel termination) > Make the RC larger than the transition time, but smaller than the clock High or > Low time. > 50 Ohm and 100 pF is a proven combination for all but the very fastest clocks. > > Peter Alfke, Xilinx Applications > ###### Message-ID: <3A41D527.4F3C91B0@sqf.hp.com> Date: Thu, 21 Dec 2000 10:02:15 +0000 From: Nial Stewart Reply-To: nials@sqf.hp.com Organization: Agilent X-Mailer: Mozilla 4.75 [en] (X11; U; HP-UX B.10.20 9000/785) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <3A410351.5A6ED19B@xilinx.com> <3A412CCF.6265005A@andraka.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Original-NNTP-Posting-Host: hpqt0797.sqf.hp.com X-Original-Trace: 21 Dec 2000 10:02:15 GMT, hpqt0797.sqf.hp.com Lines: 16 NNTP-Posting-Host: hpsqftk.sqf.hp.com X-Trace: 21 Dec 2000 03:02:38 -0700, hpsqftk.sqf.hp.com Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!ihnp4.ucsd.edu!sdd.hp.com!hp-corv.cv.hp.com!hpb10302.boi.hp.com!hpsqftk!hpqt0797.sqf.hp.com Xref: chonsp.franklin.ch comp.arch.fpga:3453 Ray Andraka wrote: > > WOrks as long as 1) you can tolerate the ringing that inevitably occurs when the > driver shuts off, Ray, I clearly saw this effect on a 'scope when experimenting with different configurations for driving the op. As you might expect it gets worse as the DRIVE attribute is increased. It's actually very hard to properly terminate the track whilst pulling the line high as hard as possible. Nial. ###### From: Andy Peters <"apeters <"@> n o a o [.] e d u> Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion Date: Thu, 21 Dec 2000 10:33:39 -0700 Organization: National Optical Astronomy Observatory Lines: 59 Message-ID: <91tev5$9pm$1@noao.edu> References: <3A3F3339.AC12CB9E@sqf.hp.com> <91r88v$cqb$2@lure.pipex.net> <3A412F6A.ACE1B0D6@xilinx.com> NNTP-Posting-Host: theremin.tuc.noao.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: noao.edu 977420069 10038 140.252.18.68 (21 Dec 2000 17:34:29 GMT) X-Complaints-To: abuse@noao.edu NNTP-Posting-Date: 21 Dec 2000 17:34:29 GMT X-Mailer: Mozilla 4.61 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!cyclone.bc.net!arclight.uoregon.edu!news.asu.edu!ennfs.eas.asu.edu!noao!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3504 Peter Alfke wrote: > > markp wrote: > > > In my experience series terminating clocks is superior to other forms of > > clock termination, but I'll leave that can of worms to another thread! > > > > Series termination is great for signals that go from one source to one > destination. > Since the drive impdance is adjusted to match the transmission line Z0, a > half-amplitude signal travels down the line, is reflected at the unterminated > far end to become a full signal "instantaneously", then travels back to the > source, where it is swallowed up in the output impedance = Z0. > > Neat trick. It USES the reflection instead of FIGHTING it. > > But beware: Never ever (NEVER EVER!) use series termination for a signal that > has to travel to multiple destinations. All but the farthest of these > destinations will see the half-amplitude signal for some time, which is the > worst level possible. Poor noise immunity, double-triggering etc. Ugly stuff. Actually -- you can get away with series termination for something driving multiple loads IFF you pay strict attention to the layout (keep all arms the same length, etc etc etc). Simulation of the PCB with something like Hyperlynx is required. I know it works because I just did an XC4013XLA SRDAM controller design. The FPGA talked to four SDRAM devices. The series terminations (the CTS four-banger SMT jobs) were installed as close as we could get them to the FPGA. Two of the SDRAMs were on the top of the board; the other two were on the bottom. We also made sure line lengths were equal, and the SDRAM and FPGA clocks were all driven by a zero-delay PLL clock buffer chip. Works fine (the board runs at 80 MHz) and looking at the signals on a fast 'scope (with proper probing, etc etc) shows real clean signals for everything. > The best way to terminate a clock that drives multiple loads is to have a > strong ( low-impedance ) driver, then terminate the farthest end of the clock > "snake" with a resistor (=Z0) in series with a capacitor to ground. (RC in > SERIES, and this combination used as a parallel termination) > Make the RC larger than the transition time, but smaller than the clock High or > Low time. > 50 Ohm and 100 pF is a proven combination for all but the very fastest clocks. But only use AC termination for 50% duty-cycle signals like clocks. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt." ###### Message-ID: <3A42AFC2.D87E8FCD@earthlink.net> From: Robert X-Mailer: Mozilla 4.5 [en] (Win95; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga,sci.electronics.design Subject: Re: 3V -> 5V clock signal level conversion References: <3A3F3339.AC12CB9E@sqf.hp.com> <3A410351.5A6ED19B@xilinx.com> <3A412CCF.6265005A@andraka.com> <3A41D527.4F3C91B0@sqf.hp.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 45 Date: Fri, 22 Dec 2000 01:35:16 GMT NNTP-Posting-Host: 63.36.6.121 X-Complaints-To: abuse@earthlink.net X-Trace: newsread1.prod.itd.earthlink.net 977448916 63.36.6.121 (Thu, 21 Dec 2000 17:35:16 PST) NNTP-Posting-Date: Thu, 21 Dec 2000 17:35:16 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!dca1-hub1.news.digex.net!intermedia!howland.erols.net!cyclone2.usenetserver.com.MISMATCH!news-out.usenetserver.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread1.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3479 Nial Stewart wrote: > Ray Andraka wrote: > > > > WOrks as long as 1) you can tolerate the ringing that inevitably occurs when the > > driver shuts off, > > Ray, > > I clearly saw this effect on a 'scope when experimenting with > different configurations for driving the op. As you might expect > it gets worse as the DRIVE attribute is increased. > > It's actually very hard to properly terminate the track whilst > pulling the line high as hard as possible. > > Nial. When the buffer turns off, you are inducing a negative current step of -I traveling down the line. Here I is the current still being delivered by the buffer at the instant of turn-off. The net result is a voltage of magnitude -I*Zo superimposed upon the line voltage already established and traveling to the destination. This tells you that until I has decayed to negligible levels, you have accomplished nothing. The timing will be a function of your termination RC time constant and the travel time down the line. The simplest fix here would be to use one or two diodes, or even a zener, to lower the Vcc of the receiver Schmitt trigger so that the worst case Vin,h threshold can be met by the Xilinx Voh output level. This will certainly be the case at Vcc=3.0V so you have lots of room to work with. You terminate the line in a series RC in shunt with the line with R=Z0 and C=Trise/(2.2*R) where Trise is the fastest expected rise time from the Xilinx under this loading. This will yield a reasonable value of C that produces negligible reflection. Having done this, you can use the Schmitt to directly drive any TTL compatible load under light loading. It pulls right up to its rails at 100uA. The outputs are not 5V tolerant but there should be no problem with driving an ACT/HCT type of CMOS input with a leakage pulldown of 33K ohm (100uA limit). In summary then, use the NC7SZ14 single Schmitt trigger from the UHS (CMOS) line running off 3.0V, for a maximum Vin,h threshold of 2.2V, to receive the clock line. This can drive the NC7ST04 (TTL Input and input leakage ~0.1uA) single inverter running off 5V. Use precautionary resistive pulldown at output of Schmitt not to exceed 100uA at Voh=3V.