From: "Damir Danijel Zagar" Newsgroups: comp.arch.fpga Subject: Verilog or VHDL Date: Thu, 14 Dec 2000 09:36:21 +0100 Organization: HiNet Lines: 14 Message-ID: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: ad2-m150.net.hinet.hr X-Trace: as121.tel.hr 976785024 499690 195.29.130.150 (14 Dec 2000 09:10:24 GMT) X-Complaints-To: abuse@hinet.hr NNTP-Posting-Date: Thu, 14 Dec 2000 09:10:24 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!blackbush.xlink.net!news.csl-gmbh.net!newsfeed2.news.nl.uu.net!sun4nl!ams.uu.net!news-hub.siol.net!news1.hinet.hr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3270 I'm starting new FPGA design. In some previous projects I've used schematic entry, but for this one I would like to dive into HDL. My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. What are advantages/disadvantages for both of them? Which one to pick up? Thank you for all suggestions. Damir From: "Damir Danijel Zagar" Newsgroups: comp.arch.fpga Subject: Verilog or VHDL Date: Thu, 14 Dec 2000 09:36:21 +0100 Organization: HiNet Lines: 14 Message-ID: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: ad2-m150.net.hinet.hr X-Trace: as121.tel.hr 976785024 499690 195.29.130.150 (14 Dec 2000 09:10:24 GMT) X-Complaints-To: abuse@hinet.hr NNTP-Posting-Date: Thu, 14 Dec 2000 09:10:24 +0000 (UTC) X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!blackbush.xlink.net!news.csl-gmbh.net!newsfeed2.news.nl.uu.net!sun4nl!ams.uu.net!news-hub.siol.net!news1.hinet.hr!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3270 I'm starting new FPGA design. In some previous projects I've used schematic entry, but for this one I would like to dive into HDL. My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. What are advantages/disadvantages for both of them? Which one to pick up? Thank you for all suggestions. Damir ###### From: Eduardo Augusto Bezerra Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Thu, 14 Dec 2000 18:47:20 +0000 Organization: University of Sussex - http://www.sussex.ac.uk Lines: 20 Message-ID: <3A3915B8.AE59F618@sussex.ac.uk> References: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: engg101-101.engg.susx.ac.uk Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: ames.central.susx.ac.uk 976819186 14729 139.184.101.101 (14 Dec 2000 18:39:46 GMT) X-Complaints-To: usenet@newshost.central.susx.ac.uk NNTP-Posting-Date: 14 Dec 2000 18:39:46 GMT X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!colt.net!newspeer.clara.net!news.clara.net!server3.netnews.ja.net!newshost.central.susx.ac.uk!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3283 Hi It's a difficult decision. I suggest you to look around and try to find out which language is the most used among your colleagues. In Europe it's easier to find VHDL users than in the USA. BTW, have you heard of Handel-C? Eduardo. "Jason A. Daughenbaugh" wrote: > > When we asked this same question about 2 years ago, and our Xilinx FAE told us to go with Verilog. So all of my experience since then has been with verilog. My guess is that eveyone would respond that whatever hdl they use is best, and like them, I cannot give a very objective opinion. I can supply a couple of observations. One is that Verilog is much more dense - If you look at a Xilinx app note that supplies example code in VHDL and Verilog, it always seems that the VHDL is 4x as long. Not that this is necessarily a bad thing... You might want to take a look at one of these and see which you find more readable. > Also, a big advantage to us has been that all of our clients use Verilog - in fact I have not yet come in contact with anyone who uses VHDL, but again, this is just me. I do know that much of the world's ASIC design is done in verilog. > I once heard that the difference is like the programming languages C and ADA. They both can get the job done. C is quicker to code, but easier to shoot yourself in the foot. ADA has a lot of conventions to prevent this (resulting in longer listings). > > Your Xilinx FAE might be a good person to ask. > > Jason Daughenbaugh > http://www.aedinc.net ###### From: "Jamie Sanderson" Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Thu, 14 Dec 2000 14:13:34 -0500 Organization: Nortel Lines: 27 Message-ID: <91b64u$9gl$1@bcarh8ab.ca.nortel.com> References: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: jamie-2.ca.nortel.com X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!arclight.uoregon.edu!!nrchh45.us.nortel.com!zcarh46f.ca.nortel.com!bcarh8ac.ca.nortel.com!bcarh8ab.ca.nortel.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3321 "Damir Danijel Zagar" wrote in message news:91a2q0$f7va$1@as121.tel.hr... > I'm starting new FPGA design. In some previous projects I've used > schematic entry, but for this one I would like to dive into HDL. > My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. > What are advantages/disadvantages for both of them? Which one > to pick up? Thank you for all suggestions. > > Damir It would be easy to go on at length about the relative merits of each language, and start a massive debate. My belief is that if you're doing FPGA design as a profession, you should learn both Verilog and VHDL. Still, I recommend VHDL for beginners. As someone else pointed out, Verilog is easier to make mistakes in. For example, you can assign one signal to another, even if they aren't of the same width. VHDL considers this a mistake, and won't compile. Usually it come down to what the people you work with know. You probably wouldn't want to be the lone person using VHDL or Verilog in your outfit because you'd have no one to turn to with questions. Cheers, Jamie ###### From: gah@ugcs.caltech.edu (glen herrmannsfeldt) Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: 14 Dec 2000 20:21:35 GMT Organization: California Institute of Technology, Pasadena Lines: 13 Message-ID: <91ba4f$slr@gap.cco.caltech.edu> References: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: seniti.ugcs.caltech.edu X-Newsreader: NN version 6.5.0 #1 (NOV) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!news-nue1.dfn.de!news-lei1.dfn.de!news-was.dfn.de!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!nntp-server.caltech.edu!gah Xref: chonsp.franklin.ch comp.arch.fpga:3315 "Damir Danijel Zagar" writes: >I'm starting new FPGA design. In some previous projects I've used >schematic entry, but for this one I would like to dive into HDL. >My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. >What are advantages/disadvantages for both of them? Which one >to pick up? Thank you for all suggestions. Oversimpifying, as usual, if you like coding in C you will probably like verilog better. If you don't like C, maybe Pascal, Fortran, or COBOL, then maybe VHDL. -- glen ###### Message-ID: <3A39605A.80319943@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 68 Date: Fri, 15 Dec 2000 00:05:46 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 976838751 62.254.210.251 (Fri, 15 Dec 2000 00:05:51 GMT) NNTP-Posting-Date: Fri, 15 Dec 2000 00:05:51 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!diablo.netcom.net.uk!netcom.net.uk!newsfeed.icl.net!nntp.news.xara.net!xara.net!gxn.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3297 Jamie Sanderson wrote: > "Damir Danijel Zagar" wrote in message > news:91a2q0$f7va$1@as121.tel.hr... > > I'm starting new FPGA design. In some previous projects I've used > > schematic entry, but for this one I would like to dive into HDL. > > My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. > > What are advantages/disadvantages for both of them? Which one > > to pick up? Thank you for all suggestions. > > > > Damir > > It would be easy to go on at length about the relative merits of each > language, and start a massive debate. My belief is that if you're doing FPGA > design as a profession, you should learn both Verilog and VHDL. > > Still, I recommend VHDL for beginners. As someone else pointed out, Verilog > is easier to make mistakes in. For example, you can assign one signal to > another, even if they aren't of the same width. VHDL considers this a > mistake, and won't compile. > Its interesting that this width thing is always the difference first mentioned in this VHDL/Verilog discussion and its actually misleading. Verilog, at least at the synthesisable level, really only has three data types and no ability for creating any form of structure. wire: Only has a value when driven, defaults to 'z' when not driven reg: retains the last value assigned to it. integer these can be either single bit or [a:b] vectors i.e. wire [a:b] foo; because of this `width' rules can be defined that are very simple. Very approximately [see LRM for details]: if the lhs is wider than the rhs fill the top bits of the lhs with 0's. if the lhs is narrower than the rhs only use the ls bits of the rhs. if the rhs is some complex expression then its width is the width of the largest operand. Some care is needed when mixing reg/wire with integer since the former are considered unsigned and the latter signed. VHDL, by contrast, allows complex derived data types and therefore *needs* strong type checking [Historical question: Which came first, complex types or strong typing ?]. Because Verilog's types are restricted these sort of issues can mostly be taken care of by some careful self-discipline or formal coding styles. If necessary you could invest in one of the `lint' style tools [Anyone know if there's a shareware or GPL'ed one ?]. The **big** thing that bites people with Verilog esp those brought up on VHDL is the blocking/non-blocking assignment thing on which whole tomes have been written. Without care & attention to this its perfectly possible to write Verilog that simulates fine at RTL, synthesises o.k., but whose synth results don't actually match the RTL. Ultimately its not that hard to grasp but it does expose the actions of the simulator, basically the way different classes of event are scheduled becomes visible at the HDL level. ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <91a2q0$f7va$1@as121.tel.hr> Subject: Re: Verilog or VHDL Lines: 73 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Fri, 15 Dec 2000 04:01:46 GMT NNTP-Posting-Host: 65.33.87.186 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 976852906 65.33.87.186 (Thu, 14 Dec 2000 23:01:46 EST) NNTP-Posting-Date: Thu, 14 Dec 2000 23:01:46 EST Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.skycache.com!Cidera!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3330 Damir, The truth to the matter is that it doesn't matter which language you go with, unless you consider certain factors which probably don't apply to you. At one time, I would have recommended VHDL for FPGA design. The reason WAS that there were more tools supporting VHDL than Verilog. They were cheaper, easier to get and relatively common. VHDL tools were cheaper probably because the VHDL standards committee made it into IEEE standard 1076 in 1987, while Verilog was nowhere near a standard. It was owned by Gateway Design Automation, which was bought out by Cadence; therefore, most designers and tools manufacturers considered Verilog as a proprietary language. During that time, Verilog was adopted by most of the ASIC industry in the United States due to its fast gate level simulation, higher levels of abstraction, introduction by Synopsis of the first Verilog synthesizer (1988), and Cadence Verilog-XL simulator sign off certification by ASIC vendors (1989). As you can see, many things caused Verilog to kick off in the ASIC world in the late 1980s. So the difference between ASICs and FPGAs back around 1990 was much more pronounced than it is today, not just in gate count but in the tools suites. FPGAs were the cheapie versions of ASICs, and along with them came cheapie VHDL tools. I am convinced that the IEEE standard caused tools vendors to be more efficient and thus produce cheaper tools. They did this, because Cadence and Synopsis had a stranglehold on the Verilog language, and VHDL was the only other HDL that could compete with it. Then around 1994-1997, things started to turn around in the FPGA world. The Verilog language was handed over to OVI (Open Verilog International), which drastically improved the Language Reference Manual, and promoted Verilog openly to become IEEE standard 1364 in 1995. All of this occurred mostly due to the HDL war with VHDL. Now that it was an open language and carried the prestigious IEEE logo, tools vendors started coming out with Verilog versions of FPGA tools. My personal experience was that most FPGA tools did not support Verilog until around 1996-1997. But when they did, they came on like gangbusters. Today engineers flame each other on which language is better. The truth is that both languages will do the job. VHDL will do some things better (e.g. better control of synthesis, error checking, etc.); Verilog will do other things better (e.g. faster quicky jobs, PLI, etc.). But both will do the job, and both are supported by most tools today. If you are an FPGA tool vendor or plan to become one, then you'd better support both HDLs. A decade ago, there was a true, compelling reason to go with VHDL due to tools support for FPGAs. Today, the only compelling reason I can think of to go with an HDL is if you plan to migrate to ASICs. If you are in the U.S., then Verilog is the preferred ASIC HDL. If you are in Europe, then VHDL is the preffered HDL. I don't know about the Pacific Rim -- maybe one or some of our Pacific Rim brothers/sisters can answer that one. I am glad that both HDLs exist. If you read the brief history given above, one can understand that it was competition that made both languages what they are today. Competition resulted in cheaper and better tools, proliferation of HDL design entry, and better end results. As an experienced VHDL and Verilog user, I will advise you to select one of the HDLs and just start using it. If you have to switch later on, then just do it! You'll have plenty of time to do so before you become a power user that is stuck in one language. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL "Damir Danijel Zagar" wrote in message news:91a2q0$f7va$1@as121.tel.hr... > I'm starting new FPGA design. In some previous projects I've used > schematic entry, but for this one I would like to dive into HDL. > My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. > What are advantages/disadvantages for both of them? Which one > to pick up? Thank you for all suggestions. > > Damir ###### From: eml@riverside-machines.com.NOSPAM Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Fri, 15 Dec 2000 10:45:48 GMT Organization: Riverside Machines Ltd. Lines: 27 Message-ID: <3a39f5d5.8107937@news.dial.pipex.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> NNTP-Posting-Host: userfg03.uk.uudial.com X-Trace: lure.pipex.net 976877328 17440 62.188.22.5 (15 Dec 2000 10:48:48 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 15 Dec 2000 10:48:48 GMT X-Newsreader: Forte Free Agent 1.11/32.235 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!tank.news.pipex.net!pipex!eyre.news.uk.uu.net!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3320 On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz wrote: >VHDL, by contrast, allows complex derived data types and therefore *needs* >strong type checking [Historical question: Which came first, complex types or >strong typing ?]. Historical musing: C has complex derived data types, but K&R C didn't have strong type checking. The IEEE version added more rigorous checking later. The original C, it could be argued, simply got it wrong. As an aside, it always annoys me to see statements that it's easy to learn Verilog if you know C. There are minor similarities, but very little that'll help you learn Verilog. It could even be argued that an understanding of types will help you learn VHDL. As another gratuitous aside, I'd like to know why people who write forewords to Verilog books always see fit to badmouth VHDL. J. Gordon Bell wrote a breathtaking foreword to Moorby's book, in which he stated that Verilog was better than VHDL because it had been written by one person, and VHDL had been designed by a committee. I hope he was around when an IEEE committee decided to add non-blocking statements to Verilog, changing it from an unusable curiosity into a half-usable language. Evan ###### Message-ID: <3A3A5D25.24E6A12D@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <3a39f5d5.8107937@news.dial.pipex.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 46 Date: Fri, 15 Dec 2000 18:04:21 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 976903464 62.254.210.251 (Fri, 15 Dec 2000 18:04:24 GMT) NNTP-Posting-Date: Fri, 15 Dec 2000 18:04:24 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeeds.belnet.be!news.belnet.be!diablo.netcom.net.uk!netcom.net.uk!nntp.news.xara.net!xara.net!gxn.net!server6.netnews.ja.net!server4.netnews.ja.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3300 eml@riverside-machines.com.NOSPAM wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz > wrote: > > >VHDL, by contrast, allows complex derived data types and therefore *needs* > >strong type checking [Historical question: Which came first, complex types or > >strong typing ?]. > > Historical musing: C has complex derived data types, but K&R C didn't > have strong type checking. The IEEE version added more rigorous > checking later. The original C, it could be argued, simply got it > wrong. > Yes & I remember a lot of old-fashioned C hackers moaning about the restrictions imposed when C was ANSI-fied, mainly because it exposed a lot of code that really only worked by the grace of the goddess of programmers. > > As an aside, it always annoys me to see statements that it's easy to > learn Verilog if you know C. There are minor similarities, but very > little that'll help you learn Verilog. It could even be argued that an > understanding of types will help you learn VHDL. > Absolutely. The pernicious confusion here is that C might help you to write Verilog but that's several parsecs from learning/understanding it. > > As another gratuitous aside, I'd like to know why people who write > forewords to Verilog books always see fit to badmouth VHDL. J. Gordon > Bell wrote a breathtaking foreword to Moorby's book, in which he > stated that Verilog was better than VHDL because it had been written > by one person, and VHDL had been designed by a committee. I hope he > was around when an IEEE committee decided to add non-blocking > statements to Verilog, changing it from an unusable curiosity into a > half-usable language. > > Evan Yes, a blot on an otherwise excellent book. ###### From: kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: 15 Dec 2000 19:16:06 GMT Organization: Helsinki University of Technology Lines: 56 Message-ID: References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> NNTP-Posting-Host: gamma.hut.fi X-Trace: nntp.hut.fi 976907766 29762 130.233.224.52 (15 Dec 2000 19:16:06 GMT) X-Complaints-To: usenet@nntp.hut.fi NNTP-Posting-Date: 15 Dec 2000 19:16:06 GMT User-Agent: slrn/0.9.6.2 (OSF1) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed1.telenordia.se!algonet!newsfeed1.funet.fi!newsfeeds.funet.fi!news.cs.hut.fi!nntp.hut.fi!kenkovaa Xref: chonsp.franklin.ch comp.arch.fpga:3327 On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz wrote: >Its interesting that this width thing is always the difference first mentioned >in this VHDL/Verilog discussion and its actually misleading. Verilog, at least >at the synthesisable level, really only has three data types and no ability for >creating any form of structure. ..... >because of this `width' rules can be defined that are very simple. Very >approximately [see LRM for details]: > >if the lhs is wider than the rhs fill the top bits of the lhs with 0's. > >if the lhs is narrower than the rhs only use the ls bits of the rhs. > >if the rhs is some complex expression then its width is the width of the largest >operand. The problem is that it is easy to connect two different sized busses in Verilog and the problems can be very difficult to detect during testing. For example topmost bit missing etc. I have seen too many problems caused by the fact that Verilog doesn't check the bus widths. The errors are easy to make for example when one big bitvector is built from tens of other busses and one width is defined incorrectly. In VHDL the compiler complains immediatly about bus sizes. Those bugs can take days to find in complex designs. >VHDL, by contrast, allows complex derived data types and therefore *needs* >strong type checking [Historical question: Which came first, complex types or >strong typing ?]. Quite few people actually use the data types in synthesizable code altough it is very wise thing to do. One example is the control bus if it is defined as record the compiler immediatly complains if the bus is connected to wrong place. Bit vectors can be by chance same sized and connected incorrectly. >Because Verilog's types are restricted these sort of issues can mostly be taken >care of by some careful self-discipline or formal coding styles. If necessary >you could invest in one of the `lint' style tools [Anyone know if there's a >shareware or GPL'ed one ?]. Try sometimes running lint tools to Verilog designs. For example I tried one working Verilog design with synopsys synthesis linting rules and I got about 20000 violations. Most of them were caused by Verilog coding style where different sized busses are connected together and the designer expects the topmost bits to be 0 etc. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file system ###### Message-ID: <3A3A8531.E4A48BAE@hotmail.com> From: "x-guy@hotmail.com" Reply-To: x-guy@hotmail.com Organization: @Planet X-Mailer: Mozilla 4.7 [en] (Win98; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 59 Date: Fri, 15 Dec 2000 20:55:32 GMT NNTP-Posting-Host: 172.18.141.115 X-Complaints-To: newsmaster@nokia.com X-Trace: news2.nokia.com 976913732 172.18.141.115 (Fri, 15 Dec 2000 22:55:32 EET) NNTP-Posting-Date: Fri, 15 Dec 2000 22:55:32 EET Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed1.telenordia.se!algonet!newsfeed1.nokia.com!news1.nokia.com!news2.nokia.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3303 I agree. Tools are developed to alleviate the burden and help catch any mistake (even the most experienced guy makes mistakes and particularly get tired, have blurred eyes...). Expecting people to take care lots things is not a good way. Kim Gunnar Enkovaara wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz wrote: > > >Its interesting that this width thing is always the difference first mentioned > >in this VHDL/Verilog discussion and its actually misleading. Verilog, at least > >at the synthesisable level, really only has three data types and no ability for > >creating any form of structure. > ..... > >because of this `width' rules can be defined that are very simple. Very > >approximately [see LRM for details]: > > > >if the lhs is wider than the rhs fill the top bits of the lhs with 0's. > > > >if the lhs is narrower than the rhs only use the ls bits of the rhs. > > > >if the rhs is some complex expression then its width is the width of the largest > >operand. > > The problem is that it is easy to connect two different sized busses > in Verilog and the problems can be very difficult to detect during > testing. For example topmost bit missing etc. I have seen too many > problems caused by the fact that Verilog doesn't check the bus widths. > The errors are easy to make for example when one big bitvector is built > from tens of other busses and one width is defined incorrectly. In > VHDL the compiler complains immediatly about bus sizes. Those bugs can > take days to find in complex designs. > > >VHDL, by contrast, allows complex derived data types and therefore *needs* > >strong type checking [Historical question: Which came first, complex types or > >strong typing ?]. > > Quite few people actually use the data types in synthesizable code > altough it is very wise thing to do. One example is the control bus if > it is defined as record the compiler immediatly complains if the bus is > connected to wrong place. Bit vectors can be by chance same sized and > connected incorrectly. > > >Because Verilog's types are restricted these sort of issues can mostly be taken > >care of by some careful self-discipline or formal coding styles. If necessary > >you could invest in one of the `lint' style tools [Anyone know if there's a > >shareware or GPL'ed one ?]. > > Try sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > > -- > ============================================================================= > Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian > Iirislahdentie 47 E | IRC: embo | curved-space fault in > 02230 Espoo,Finland | | write-only file system ###### Message-ID: <3A3AC8A1.13679898@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!unknown@rfhome.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 29 Date: Sat, 16 Dec 2000 01:42:57 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 976930977 62.254.210.251 (Sat, 16 Dec 2000 01:42:57 GMT) NNTP-Posting-Date: Sat, 16 Dec 2000 01:42:57 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!colt.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3298 Kim Gunnar Enkovaara wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz Try > sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > > -- The millions of warnings stuff will be familiar to anyone who's used a PCB design systems DRC checkers which insist on complaining about all unconnected pins, or 200 warnings caused by placing a component under the EPROM socket, or ... Usually takes about 20 min to write a rough&ready bit of perl to reduce the warnings by 2 orders of magnitude. Then you pipe that through some flavour of diff to compare it with the previous set, stick everything in makefile, ... There's actually a serious point here. Verilog is a much more exposed language and doesn't presume to try to stop you making a fool of yourself. Coding styles, lint, formal verification and so forth are thing the user defines or imposes his/her self. Set your paranoia level according to taste. In this sense its like C. I suspect that those, like myself, who can live with or even appreciate this `caveat emptor' philosophy will tend to go for Verilog. ###### From: Srinivasan Venkataramanan Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog or VHDL Date: Sat, 16 Dec 2000 13:28:07 +0530 Organization: RealChip, Chennai, India Lines: 50 Message-ID: <3A3B208F.FBE185D5@realchip.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> NNTP-Posting-Host: 206.103.12.197 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fu-berlin.de 976953534 4312267 206.103.12.197 (16 [63087]) X-Mailer: Mozilla 4.72 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!fu-berlin.de!uni-berlin.de!206.103.12.197!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3307 Hi, Kim Gunnar Enkovaara wrote: > > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz wrote: > Quite few people actually use the data types in synthesizable code > altough it is very wise thing to do. One example is the control bus if > it is defined as record the compiler immediatly complains if the bus is > connected to wrong place. Bit vectors can be by chance same sized and > connected incorrectly. > That's an interesting approach. Do you mean to say that use records for control bus ? I am not sure whether low end synthesis tools (don't have a list..) support records. But I would be very much interested in seeing a tiny example - if that doesn't burden you too much :-) > > Try sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > Well I don't know the tool that you talk about. But IMHO a *GOOD* lint tool MUST be 1.> "configurable" i.e. the user should be able to specify *with ease* new rules 2.> It should be possible to turn the checks ON & OFF with ease On top of these you could use PERL etc. to filter out unwanted stuff. With the above qualities I think a lint tool can be of GREAT help to the design community (especially Verilog). Now if you ask me if I have ever seen such a linter, the answer is YES! I have evaluated LEDA's ProVHDL (Now LEDA is part of Synopsys..) they also have a Verilog version, ProVerilog. Regards, Srini -- Srinivasan Venkataramanan (Srini) ASIC Design Engineer, Chennai (Madras), India ###### From: kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog or VHDL Date: 16 Dec 2000 16:44:22 GMT Organization: Helsinki University of Technology Lines: 53 Message-ID: References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <3A3B208F.FBE185D5@realchip.com> NNTP-Posting-Host: gamma.hut.fi X-Trace: nntp.hut.fi 976985062 9676 130.233.224.52 (16 Dec 2000 16:44:22 GMT) X-Complaints-To: usenet@nntp.hut.fi NNTP-Posting-Date: 16 Dec 2000 16:44:22 GMT User-Agent: slrn/0.9.6.2 (OSF1) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed1.telenordia.se!algonet!newsfeed1.funet.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!nntp.hut.fi!kenkovaa Xref: chonsp.franklin.ch comp.arch.fpga:3326 On Sat, 16 Dec 2000 13:28:07 +0530, Srinivasan Venkataramanan wrote: >Hi, > > > That's an interesting approach. Do you mean to say that use records >for control bus ? I am not sure whether low end synthesis tools (don't >have a list..) support records. But I would be very much interested in >seeing a tiny example - if that doesn't burden you too much :-) For example digital clock is good example. All the numbers can be defined independently in a record and that record can be used in the data bus definition. I think it's easier to say bus.sec than bus[10:15]. The code is much easier to read when the names are used. I got the idea of using records from one VHDL course where the trainer was very experienced VHDL coder and synthesis tool trainer, Those records even synthesized very well. The tools I tried were Synplify Pro 6.0 (or 6.1 but that doesn't matter) and Synopsys Design Compiler so the tools were not low end. I get my net connection up in few days, after that I can give some examples if you want. I have been quite impressed about Synplify also in other codes. It really creates better results than Leonardo or Synopsys FPGA Compiler and it creates the results much faster. The one good thing about leonardo is that it sometimes creates smaller designs and that matters if the chip is 99% full. > Well I don't know the tool that you talk about. But IMHO a *GOOD* >lint tool MUST be > >1.> "configurable" i.e. the user should be able to specify *with ease* >new rules >2.> It should be possible to turn the checks ON & OFF with ease I tried TransEDA VNCheck. I think the tool was excellent and I customized the rules but the Verilog coding style was still the problem. It's difficult for the tool to guess what the designer was thinking when he/she coded something weird. >With the above qualities I think a lint tool can be of GREAT help to >the design community (especially Verilog). I think that without good lint tools coding Verilog is quite difficult. The lint tools do what VHDL compiler does during the compilation. Human errors are just too easy to make, even the best coder can make error at some point. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file system ###### From: Srinivasan Venkataramanan Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog or VHDL Date: Sun, 17 Dec 2000 17:14:50 +0530 Organization: RealChip, Chennai, India Lines: 66 Message-ID: <3A3CA732.A85DACA3@realchip.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <3A3B208F.FBE185D5@realchip.com> NNTP-Posting-Host: 206.103.12.197 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: fu-berlin.de 977053535 4435134 206.103.12.197 (16 [63087]) X-Mailer: Mozilla 4.72 [en] (Win98; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!newsfeed1.online.no!nextra.com!news.algonet.se!newsfeed1.telenordia.se!algonet!uni-erlangen.de!fu-berlin.de!uni-berlin.de!206.103.12.197!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3308 Hi, Kim Gunnar Enkovaara wrote: > > On Sat, 16 Dec 2000 13:28:07 +0530, Srinivasan Venkataramanan wrote: > > For example digital clock is good example. All the numbers can be > defined independently in a record and that record can be used in the > data bus definition. I think it's easier to say bus.sec than > bus[10:15]. The code is much easier to read when the names are used. > I got the idea of using records from one VHDL course where the trainer > was very experienced VHDL coder and synthesis tool trainer, > Very interesting indeed. > Those records even synthesized very well. The tools I tried were > Synplify Pro 6.0 (or 6.1 but that doesn't matter) and Synopsys Design > Compiler so the tools were not low end. I get my net connection up in > few days, after that I can give some examples if you want. > Would really appreciate that, TIA. > > > Well I don't know the tool that you talk about. But IMHO a *GOOD* > >lint tool MUST be > > > >1.> "configurable" i.e. the user should be able to specify *with ease* > >new rules > >2.> It should be possible to turn the checks ON & OFF with ease > > I tried TransEDA VNCheck. I think the tool was excellent and I > customized the rules but the Verilog coding style was still > the problem. It's difficult for the tool to guess what the designer > was thinking when he/she coded something weird. > Well, with a *GOOD* linter, you can "filter" out unwanted messages. But when you don't know whether the message is unwanted (I guess that's the situation that depicted) - I can imagine how annoying it could be. It is a BAD coding style (as you yourself mentioned) rather than a *BAD* lint tool itself. > >With the above qualities I think a lint tool can be of GREAT help to > >the design community (especially Verilog). > > I think that without good lint tools coding Verilog is quite > difficult. The lint tools do what VHDL compiler does during the > compilation. Human errors are just too easy to make, even the best > coder can make error at some point. Agreed :-) Regards, Srini -- Srinivasan Venkataramanan (Srini) ASIC Design Engineer, Chennai (Madras), India ###### From: bobdittmar@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Mon, 18 Dec 2000 02:39:05 GMT Organization: Deja.com Lines: 39 Message-ID: <91jtc9$o1j$1@nnrp1.deja.com> References: <91a2q0$f7va$1@as121.tel.hr> NNTP-Posting-Host: 172.138.247.94 X-Article-Creation-Date: Mon Dec 18 02:39:05 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Mac_PowerPC) X-Http-Proxy: 1.1 x62.deja.com:80 (Squid/1.1.22) for client 172.138.247.94 X-MyDeja-Info: XMYDJUIDbobdittmar Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3348 In article <91a2q0$f7va$1@as121.tel.hr>, "Damir Danijel Zagar" wrote: > I'm starting new FPGA design. In some previous projects I've used > schematic entry, but for this one I would like to dive into HDL. > My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. > What are advantages/disadvantages for both of them? Which one > to pick up? Thank you for all suggestions. > > Damir > > When selecting which one is "better" you should also keep in mind what your verification strategy is. I find verilog to be good for doing behavioral modeling of my test objects : processor bus models, data packet generators/monitors etc that reside in the testbench and are "wired" to the FPGA under test. These test objects have tasks that your testcase file can "call" and then your test case file make actions based on results returned from task. This allows great control over the flow of the test. Also in verilog you can place parameter specifications in your models to test setup and hold times etc... I'm not real VHDL literate but I have not seen this same testability in VHDL. Bottom line is the synthable code effort is a smaller task than the verification effort. So don't disregard language impact on your verification strategy. Bob Dittmar Sent via Deja.com http://www.deja.com/ ###### Message-ID: <3A3D96A4.1C325B92@andraka.com> From: Ray Andraka Organization: Andraka Consulting Group, Inc X-Mailer: Mozilla 4.73 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 81 Date: Mon, 18 Dec 2000 04:44:28 GMT NNTP-Posting-Host: 24.13.238.93 X-Complaints-To: abuse@home.net X-Trace: news1.wwck1.ri.home.com 977114668 24.13.238.93 (Sun, 17 Dec 2000 20:44:28 PST) NNTP-Posting-Date: Sun, 17 Dec 2000 20:44:28 PST Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newshub2.home.com!news.home.com!news1.wwck1.ri.home.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3342 It depends on what level you are coding at too. VHDL makes it fairly easy to embed placement (you know, RLOCs) in your code. I haven't figured out how to do that with verilog yet. Granted, I do much mure structural coding than your average bear, but the truth of the matter is that I can't do what I need to do in verilog, at least not yet. "S. Ramirez" wrote: > > Damir, > The truth to the matter is that it doesn't matter which language you go > with, unless you consider certain factors which probably don't apply to you. > At one time, I would have recommended VHDL for FPGA design. The reason > WAS that there were more tools supporting VHDL than Verilog. They were > cheaper, easier to get and relatively common. VHDL tools were cheaper > probably because the VHDL standards committee made it into IEEE standard > 1076 in 1987, while Verilog was nowhere near a standard. It was owned by > Gateway Design Automation, which was bought out by Cadence; therefore, most > designers and tools manufacturers considered Verilog as a proprietary > language. > During that time, Verilog was adopted by most of the ASIC industry in > the United States due to its fast gate level simulation, higher levels of > abstraction, introduction by Synopsis of the first Verilog synthesizer > (1988), and Cadence Verilog-XL simulator sign off certification by ASIC > vendors (1989). As you can see, many things caused Verilog to kick off in > the ASIC world in the late 1980s. So the difference between ASICs and FPGAs > back around 1990 was much more pronounced than it is today, not just in gate > count but in the tools suites. FPGAs were the cheapie versions of ASICs, > and along with them came cheapie VHDL tools. I am convinced that the IEEE > standard caused tools vendors to be more efficient and thus produce cheaper > tools. They did this, because Cadence and Synopsis had a stranglehold on > the Verilog language, and VHDL was the only other HDL that could compete > with it. > Then around 1994-1997, things started to turn around in the FPGA world. > The Verilog language was handed over to OVI (Open Verilog International), > which drastically improved the Language Reference Manual, and promoted > Verilog openly to become IEEE standard 1364 in 1995. All of this occurred > mostly due to the HDL war with VHDL. Now that it was an open language and > carried the prestigious IEEE logo, tools vendors started coming out with > Verilog versions of FPGA tools. My personal experience was that most FPGA > tools did not support Verilog until around 1996-1997. But when they did, > they came on like gangbusters. > Today engineers flame each other on which language is better. The > truth is that both languages will do the job. VHDL will do some things > better (e.g. better control of synthesis, error checking, etc.); Verilog > will do other things better (e.g. faster quicky jobs, PLI, etc.). But both > will do the job, and both are supported by most tools today. If you are an > FPGA tool vendor or plan to become one, then you'd better support both HDLs. > A decade ago, there was a true, compelling reason to go with VHDL due > to tools support for FPGAs. Today, the only compelling reason I can think > of to go with an HDL is if you plan to migrate to ASICs. If you are in the > U.S., then Verilog is the preferred ASIC HDL. If you are in Europe, then > VHDL is the preffered HDL. I don't know about the Pacific Rim -- maybe one > or some of our Pacific Rim brothers/sisters can answer that one. > I am glad that both HDLs exist. If you read the brief history given > above, one can understand that it was competition that made both languages > what they are today. Competition resulted in cheaper and better tools, > proliferation of HDL design entry, and better end results. > As an experienced VHDL and Verilog user, I will advise you to select > one of the HDLs and just start using it. If you have to switch later on, > then just do it! You'll have plenty of time to do so before you become a > power user that is stuck in one language. > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL > > "Damir Danijel Zagar" wrote in message > news:91a2q0$f7va$1@as121.tel.hr... > > I'm starting new FPGA design. In some previous projects I've used > > schematic entry, but for this one I would like to dive into HDL. > > My dilemma is - VERILOG or VHDL. Design is Xilinx Spartan II based. > > What are advantages/disadvantages for both of them? Which one > > to pick up? Thank you for all suggestions. > > > > Damir -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com ###### From: "Victor Schutte" Newsgroups: comp.arch.fpga References: <91a2q0$f7va$1@as121.tel.hr> Subject: Re: Verilog or VHDL Date: Mon, 18 Dec 2000 07:27:02 +0200 Lines: 58 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6600 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6600 NNTP-Posting-Host: pta-dial-196-31-185-85.mweb.co.za Message-ID: <3a3da10a.0@news1.mweb.co.za> X-Trace: 18 Dec 2000 07:30:50 +0200, pta-dial-196-31-185-85.mweb.co.za Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!enews.sgi.com!iafrica.com!news1.mweb.co.za!pta-dial-196-31-185-85.mweb.co.za Xref: chonsp.franklin.ch comp.arch.fpga:3347 For the last 3 projects (on an Altera 7128) I tried VHDL,Verilog and AHDL. All of them ended up compiling to the same gate amount, although one AHDL design was about 10ns faster. AHDL (Altera HDL) is initially difficult to understand because of the lack of documentation and is only suited for Altera devices. Even if you can port some of it to another manufacturer's IC it would be stupid to do so. VHDL is a strict language and everything must be explicitly defined, especially data type. Try converting between integer, std_logic_vectors etc... I would say that I have a greater degree of gate count control with VHDL. Verilog I would somtimes compare to a language like Basic. The data types are easier to use and you are left with a simpler syntax to design and understand. The problem is that if you don't know what you are doing that you can easily use up most of the gates on a simple design. Both VHDL and Verilog have advantages. Quite a few of my PLD designer friends are starting to mix these two languages in their designs as the one might prove easier to implement an ALU and the other easier to implement procedures and sequential statements. Remember, PLD tool suppliers are also looking at implementing some sort of a C compiler for FPGAs. That will be the source of more confusion for years to come. Victor ###### From: Andy Peters <"apeters <"@> n o a o [.] e d u> Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Mon, 18 Dec 2000 09:46:47 -0700 Organization: National Optical Astronomy Observatory Lines: 30 Message-ID: <91lf3l$29ue$1@noao.edu> References: <91a2q0$f7va$1@as121.tel.hr> <91jtc9$o1j$1@nnrp1.deja.com> NNTP-Posting-Host: theremin.tuc.noao.edu Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: noao.edu 977158069 75726 140.252.18.68 (18 Dec 2000 16:47:49 GMT) X-Complaints-To: abuse@noao.edu NNTP-Posting-Date: 18 Dec 2000 16:47:49 GMT X-Mailer: Mozilla 4.61 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!arclight.uoregon.edu!news.asu.edu!ennfs.eas.asu.edu!noao!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3354 bobdittmar@my-deja.com wrote: > > These test objects have tasks that your testcase file can "call" and > then your test case file make actions based on results returned > from task. This allows great control over the flow of the test. You can do that in VHDL. Parameters in procedures, for example. > Also in verilog you can place parameter specifications in your > models to test setup and hold times etc... You can use generics. I do. > I'm not real VHDL literate but I have not seen this same testability > in VHDL. It's there, and arguably better, IMHO. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt." ###### From: "Jamie Sanderson" Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Mon, 18 Dec 2000 13:13:58 -0500 Organization: Nortel Lines: 82 Message-ID: <91lk56$791$1@bcarh8ab.ca.nortel.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> NNTP-Posting-Host: jamie-2.ca.nortel.com X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!blackbush.xlink.net!howland.erols.net!logbridge.uoregon.edu!arclight.uoregon.edu!!nrchh45.us.nortel.com!zcarh46f.ca.nortel.com!bcarh8ac.ca.nortel.com!bcarh8ab.ca.nortel.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3350 "Rick Filipkiewicz" wrote in message news:3A39605A.80319943@algor.co.uk... > Jamie Sanderson wrote: > > Still, I recommend VHDL for beginners. As someone else pointed out, Verilog > > is easier to make mistakes in. For example, you can assign one signal to > > another, even if they aren't of the same width. VHDL considers this a > > mistake, and won't compile. > > Its interesting that this width thing is always the difference first mentioned > in this VHDL/Verilog discussion and its actually misleading. I imagine it's mentioned first because it causes much confusion, a fact attested to by a number of the other posts in this thread (and comp.lang.verilog, for that matter). > Verilog, at least > at the synthesisable level, really only has three data types and no ability for > creating any form of structure. Many VHDL designs use nothing more than std_logic and std_logic_vector. The difference is that you are forced to connect things such that each line matches one-for-one, rather than having the compiler "fill in the blanks". > wire: Only has a value when driven, defaults to 'z' when not driven > reg: retains the last value assigned to it. > integer While I distinctly didn't want to start a big argument, I guess it's inevitable. The "reg" declaration in Verilog has always been a thorn in my side. To the novice, it implies that it will be a register, typically with a clock input. Actually, all it means is that the assignment must occur within an "always" block. Therefore, some regs are "registers", while others are combinational. However, the combinational variety can typically be done as a wire outside of an "always" block. Confusing... In VHDL, a signal becomes a register by virtue of being assigned on a rising or falling clock edge. I'm also philosophically opposed to the "always @ (posedge clock or negedge reset)" terminology. You typically want level sensitivity, not edge sensitivity on your reset. In fact, that's what you get once this code is synthesized. VHDL is much more clear in this aspect. The process is sensitive to the clock and reset, but the "if" statement indicates that only the clock has an edge sensitivity. > Because Verilog's types are restricted these sort of issues can mostly be taken > care of by some careful self-discipline or formal coding styles. If necessary > you could invest in one of the `lint' style tools [Anyone know if there's a > shareware or GPL'ed one ?]. Or you could use VHDL and get much of the checking for free with the compiler. > The **big** thing that bites people with Verilog esp those brought up on VHDL is > the blocking/non-blocking assignment thing on which whole tomes have been > written. Without care & attention to this its perfectly possible to write > Verilog that simulates fine at RTL, synthesises o.k., but whose synth results > don't actually match the RTL. Ultimately its not that hard to grasp but it does > expose the actions of the simulator, basically the way different classes of > event are scheduled becomes visible at the HDL level. I always thought the problem was that simulation didn't match the designer's intentions, as opposed to the synthesized results. At least, this has been my experience with the blocking/non-blocking mix-ups. Anyhow, I'm using Verilog now, and will be for the foreseeable future. It's a fine language to use, and I would love it if we could all just agree to disagree (while being sure that each language steals the best aspects from the other, while building on its own strengths, a la Windows and MacOS). Cheers, Jamie ###### From: "S. Ramirez" Newsgroups: comp.arch.fpga References: <91a2q0$f7va$1@as121.tel.hr> <3A3D96A4.1C325B92@andraka.com> Subject: Re: Verilog or VHDL Lines: 31 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Tue, 19 Dec 2000 00:56:38 GMT NNTP-Posting-Host: 65.33.85.4 X-Complaints-To: abuse@rr.com X-Trace: typhoon.tampabay.rr.com 977187398 65.33.85.4 (Mon, 18 Dec 2000 19:56:38 EST) NNTP-Posting-Date: Mon, 18 Dec 2000 19:56:38 EST Organization: RoadRunner - Central Florida Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!newsfeed-zh.ip-plus.net!news.ip-plus.net!news.tesion.net!news.belwue.de!news-stu1.dfn.de!news-mue1.dfn.de!news.augsburg.net!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.skycache.com!Cidera!cyclone.tampabay.rr.com!typhoon.tampabay.rr.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3402 Ray, I said it wrong below ("better control of synthesis..). What I meant to say is that VHDL has better control of placement (you know, the RLOCing thing). Thanks for pointing this out, you very un-average bear! Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL "Ray Andraka" wrote in message news:3A3D96A4.1C325B92@andraka.com... > It depends on what level you are coding at too. VHDL makes it fairly easy to > embed placement (you know, RLOCs) in your code. I haven't figured out how to do > that with verilog yet. Granted, I do much mure structural coding than your > average bear, but the truth of the matter is that I can't do what I need to do > in verilog, at least not yet. > > "S. Ramirez" wrote: > > truth is that both languages will do the job. VHDL will do some things > > better (e.g. better control of synthesis, error checking, etc.); Verilog > > will do other things better (e.g. faster quicky jobs, PLI, etc.). But both > > will do the job, and both are supported by most tools today. If you are an ###### Message-ID: <3A3FF7D2.6728243F@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <91lk56$791$1@bcarh8ab.ca.nortel.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 86 Date: Wed, 20 Dec 2000 00:05:38 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 977270743 62.254.210.251 (Wed, 20 Dec 2000 00:05:43 GMT) NNTP-Posting-Date: Wed, 20 Dec 2000 00:05:43 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!fr.clara.net!heighliner.fr.clara.net!news.tele.dk!212.74.64.35!colt.net!newspeer.clara.net!news.clara.net!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3422 Jamie Sanderson wrote: > > > wire: Only has a value when driven, defaults to 'z' when not driven > > reg: retains the last value assigned to it. > > integer > > While I distinctly didn't want to start a big argument, I guess it's > inevitable. The "reg" declaration in Verilog has always been a thorn in my > side. To the novice, it implies that it will be a register, typically with a > clock input. Actually, all it means is that the assignment must occur within > an "always" block. Therefore, some regs are "registers", while others are > combinational. However, the combinational variety can typically be done as a > wire outside of an "always" block. Confusing... In VHDL, a signal becomes a > register by virtue of being assigned on a rising or falling clock edge. > I thought this at first but after a while I realised that the two uses of `reg' aren't really that far apart. In Verilog a reg can only be assigned inside an always block [for synthesis at least, ignoring ``initial'']. This block has a sensitivity list so that it gets executed only when one of the signals changes i.e. when there's an edge on one of the signals in the list. So you can, if you like, look on a `reg' as a `register' with a, possibly very complex & async, clock. > > I'm also philosophically opposed to the "always @ (posedge clock or negedge > reset)" terminology. You typically want level sensitivity, not edge > sensitivity on your reset. In fact, that's what you get once this code is > synthesized. VHDL is much more clear in this aspect. The process is > sensitive to the clock and reset, but the "if" statement indicates that only > the clock has an edge sensitivity. > You're right that the difference is philosophical since the Verilog approach is to keep all the stuff inside the always block free of timing information & to put all the control of the block's execution in the sensitivity list - which should really be called an event list. From the simulation point of view the construct you mention is nicely minimal since you don't really care about the rising edge of an active low async reset. You also get the sync/async change just by removing the second condition as opposed to having to move the position of the ``if'' statement inside the block. Note that you can put further @(xxx) statements inside an always block but I don't think many synth tools can handle this. > > > Because Verilog's types are restricted these sort of issues can mostly be > taken > > care of by some careful self-discipline or formal coding styles. If > necessary > > you could invest in one of the `lint' style tools [Anyone know if there's > a > > shareware or GPL'ed one ?]. > > Or you could use VHDL and get much of the checking for free with the > compiler. Again philosophical: I prefer to be allowed to do as I please, esp with FPGAs, & if necessary use a separate tool to measure how much risk I'm taking. > > > The **big** thing that bites people with Verilog esp those brought up on > VHDL is > > the blocking/non-blocking assignment thing on which whole tomes have been > > written. Without care & attention to this its perfectly possible to write > > Verilog that simulates fine at RTL, synthesises o.k., but whose synth > results > > don't actually match the RTL. Ultimately its not that hard to grasp but it > does > > expose the actions of the simulator, basically the way different classes > of > > event are scheduled becomes visible at the HDL level. > > I always thought the problem was that simulation didn't match the designer's > intentions, as opposed to the synthesized results. At least, this has been > my experience with the blocking/non-blocking mix-ups. I think one of the biggest problems with the blocking/non-blocking thing is that designers can realise their intentions in ways that *will* simulate correctly at the RTL level but will fail after synthesis. Its sort of a more subtle way of getting it wrong than using #delay's to get your RTL to work right. ###### From: eml@riverside-machines.com.NOSPAM Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Wed, 20 Dec 2000 22:08:46 GMT Organization: Riverside Machines Ltd. Lines: 18 Message-ID: <3a412dca.48637792@news.dial.pipex.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <91lk56$791$1@bcarh8ab.ca.nortel.com> NNTP-Posting-Host: useri607.uk.uudial.com X-Trace: lure.pipex.net 977350179 14756 194.69.106.217 (20 Dec 2000 22:09:39 GMT) X-Complaints-To: abuse@uk.uu.net NNTP-Posting-Date: 20 Dec 2000 22:09:39 GMT X-Newsreader: Forte Free Agent 1.11/32.235 Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!join.news.pipex.net!pipex!grot.news.pipex.net!pipex!tube.news.pipex.net!pipex!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3495 On Mon, 18 Dec 2000 13:13:58 -0500, "Jamie Sanderson" wrote: >While I distinctly didn't want to start a big argument, I guess it's >inevitable. The "reg" declaration in Verilog has always been a thorn in my >side. To the novice, it implies that it will be a register, typically with a >clock input. Actually, all it means is that the assignment must occur within >an "always" block. Therefore, some regs are "registers", while others are >combinational. Verilog 2000, as you may know, is replacing the term 'register' with 'variable' for exactly this reason. It's before my time, but I suspect that Verilog's original intention was that the register types should be used only for coding real registers, and that the net types were intended for all the combinatorial stuff. It would be interesting to hear from someone who can remember this far back. Evan ###### From: kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: 24 Dec 2000 08:00:58 GMT Organization: Helsinki University of Technology Lines: 32 Message-ID: References: <91a2q0$f7va$1@as121.tel.hr> <91jtc9$o1j$1@nnrp1.deja.com> NNTP-Posting-Host: gamma.hut.fi X-Trace: nntp.hut.fi 977644858 598 130.233.224.52 (24 Dec 2000 08:00:58 GMT) X-Complaints-To: usenet@nntp.hut.fi NNTP-Posting-Date: 24 Dec 2000 08:00:58 GMT User-Agent: slrn/0.9.6.2 (OSF1) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!surfnet.nl!newsfeed.wirehub.nl!newsfeeds.belnet.be!news.belnet.be!news1.ebone.net!news.ebone.net!newsrouter.euroconnect.net!news.clinet.fi!news.cs.hut.fi!nntp.hut.fi!kenkovaa Xref: chonsp.franklin.ch comp.arch.fpga:3537 On Mon, 18 Dec 2000 02:39:05 GMT, bobdittmar@my-deja.com wrote: >When selecting which one is "better" you should also keep in >mind what your verification strategy is. I find verilog to be good >for doing behavioral modeling of my test objects : processor bus >models, data packet generators/monitors etc that reside in the >testbench and are "wired" to the FPGA under test. Without PLI Verilog is quite difficult language to use for really complex behavioral models. The Verilog language itself is quite restricted, for example file i/o is poor compared to VHDL (altough it's easier to use in Verilog). Also without real data types complex behavioral models are not fun thing to do. For verification I would suggest new verification languages (Vera, e). I have used Vera quite extensivly and wouldn't go back easily to HDL languages in testbenches. I can't even think of writing 30-40k lines of complex TB code in some HDL language :) Object orientation speeds up the TB-design considerably. >I'm not real VHDL literate but I have not seen this same testability >in VHDL. You should propably read some VHDL book. VHDL was originally designed for system modeling and is quite strong language in modelling. Only small part of the language is used in synthesizable models. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file system ###### From: Srinivasan Venkataramanan Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Sun, 24 Dec 2000 18:37:57 GMT Organization: Deja.com Lines: 48 Message-ID: <925fq5$911$1@nnrp1.deja.com> References: <91a2q0$f7va$1@as121.tel.hr> <91jtc9$o1j$1@nnrp1.deja.com> NNTP-Posting-Host: 202.141.24.2 X-Article-Creation-Date: Sun Dec 24 18:37:57 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.0; Windows 98; DigExt) X-Http-Proxy: 1.0 www-proxy.iitm.ernet.in:8080 (Squid/1.1.22), 1.0 x62.deja.com:80 (Squid/1.1.22) for client 144.16.251.150, 202.141.24.2 X-MyDeja-Info: XMYDJUIDsrinivasan_v Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!tungurahua!news-ge.switch.ch!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3544 Hi, In article , kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) wrote: > On Mon, 18 Dec 2000 02:39:05 GMT, bobdittmar@my-deja.com wrote: > > Without PLI Verilog is quite difficult language to use for really > complex behavioral models. The Verilog language itself is quite > restricted, for example file i/o is poor compared to VHDL (altough > it's easier to use in Verilog). Also without real data types complex > behavioral models are not fun thing to do. > Just wanted to comment that Verilog indeed has "real data type" and I have used it to model ADC, DAC etc. at Behavioural level. Nevertheless I agree with you STRONGLY that VHDL is way ahead in terms of its Behavioural modelling capabilities (compared to Verilog). > For verification I would suggest new verification languages (Vera, > e). I have used Vera quite extensivly and wouldn't go back easily to > HDL languages in testbenches. I can't even think of writing 30-40k > lines of complex TB code in some HDL language :) Object orientation > speeds up the TB-design considerably. > Interesting opinion, Thanks for sharing that :-) But how much is this difficult, do you think, that for a Hardware Guy to understand this OO stuff. I attended a course on VERA, found it nice, but was having hard time in coding with it - I must admit that I didn't spend enough time with it (and have just changed the company where there is no VERA yet, so can't continue (:- ) and was kind of "convinced by others that OO stuff is difficult for H/W guys". Regards, Srini -- Srinivasan Venkataramanan ASIC Design Engineer Chennai, India Sent via Deja.com http://www.deja.com/ ###### From: kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: 25 Dec 2000 08:59:24 GMT Organization: Helsinki University of Technology Lines: 58 Message-ID: References: <91a2q0$f7va$1@as121.tel.hr> <91jtc9$o1j$1@nnrp1.deja.com> <925fq5$911$1@nnrp1.deja.com> NNTP-Posting-Host: gamma.hut.fi X-Trace: nntp.hut.fi 977734764 1458 130.233.224.52 (25 Dec 2000 08:59:24 GMT) X-Complaints-To: usenet@nntp.hut.fi NNTP-Posting-Date: 25 Dec 2000 08:59:24 GMT User-Agent: slrn/0.9.6.2 (OSF1) Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news-ge.switch.ch!news.tele.dk!194.255.56.67!newsfeed101.telia.com!newsrouter.euroconnect.net!news.clinet.fi!news.cs.hut.fi!nntp.hut.fi!kenkovaa Xref: chonsp.franklin.ch comp.arch.fpga:3552 On Sun, 24 Dec 2000 18:37:57 GMT, Srinivasan Venkataramanan wrote: >> it's easier to use in Verilog). Also without real data types complex >> behavioral models are not fun thing to do. >> > > Just wanted to comment that Verilog indeed has "real data type" and I >have used it to model ADC, DAC etc. at Behavioural level. Nevertheless I meant with real data types possibility to define own data types etc. >> For verification I would suggest new verification languages (Vera, >> e). I have used Vera quite extensivly and wouldn't go back easily to > > Interesting opinion, Thanks for sharing that :-) But how much is >this difficult, do you think, that for a Hardware Guy to understand >this OO stuff. I attended a course on VERA, found it nice, but was >having hard time in coding with it - I must admit that I didn't spend For normal small testbenches OO is not needed and the code is quite like Verilog or C with some additions. But the possibility to use OO abstraction enables huge possibilities in TB design. I think the biggest step is to just start using Vera (possibly needs some forcing from the management, nobody wants to spend time with new tool usually) It takes few weeks to learn the new language propely, but after that the gains can be huge. I admit that this is difficult for current generation of HW-engineers, but the ones graduating now have experience in Java/C++ and can easily code Vera. At least I see that OO based testbenches are the future. It is just too difficult to manage these big testbenches in HDL languages. >enough time with it (and have just changed the company where there is >no VERA yet, so can't continue (:- ) and was kind of "convinced by >others that OO stuff is difficult for H/W guys". I think the important factor is that there is someone with SW experience doing the basic design of the TB, at least in the beginning. I designed one of our TB structures and it was quite easy for HW-designers to code parts to the framework when they saw how everyting was attached together. When the verification effort starts to be 60-70% of the whole effort I don't think it is a bad idea to hire pure SW guy to the team to do TB code etc. At least SW guy has the needed experience to design propely those big testbenches possibly using UML and other SW design tools. For example I'm now thinking about distributed testbenches where each chip in a big chipset (and it's testbench) is running on different machine and the testbenches are communicating all trough network with eachother. That is one way of getting more speed to the simulations. But the code of doing these kinds of things starts to be quite complex but can be done in Vera. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file system ###### From: jaime.aranguren@ieee.org Newsgroups: comp.arch.fpga Subject: Re: Verilog or VHDL Date: Fri, 29 Dec 2000 07:53:41 GMT Organization: Deja.com Lines: 90 Message-ID: <92hfu4$roa$1@nnrp1.deja.com> References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> NNTP-Posting-Host: 193.170.121.114 X-Article-Creation-Date: Fri Dec 29 07:53:41 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 5.5; Windows 95) X-Http-Proxy: 1.1 x54.deja.com:80 (Squid/1.1.22) for client 193.170.121.114 X-MyDeja-Info: XMYDJUIDjaimearanguren Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!news.tele.dk!144.212.100.101!newsfeed.mathworks.com!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3570 Come on guys. It's all about types. For example, jsut look at C/C++. Without regarding the OO aspects of C++, one of the most powerful introductions of it comparing to C was the HARD TYPE CHECKING capabilities it offers, which allows to easily find mistakes and make all the coding stage of a design easier, since it's not just about writing lots of lines of code, but to make it work as desired. Who wants to spend long hours coding to find at the end that while it compiles it doesn't work as expected? And then, spend more and more hours attempting to find the bugs? What about "time to market"? Isn't it coding pointing (among other purposes) to design verification? And what if that verification is exposed to failure from the very beginning? In article , kenkovaa@gamma.hut.fi (Kim Gunnar Enkovaara) wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz wrote: > > >Its interesting that this width thing is always the difference first mentioned > >in this VHDL/Verilog discussion and its actually misleading. Verilog, at least > >at the synthesisable level, really only has three data types and no ability for > >creating any form of structure. > ..... > >because of this `width' rules can be defined that are very simple. Very > >approximately [see LRM for details]: > > > >if the lhs is wider than the rhs fill the top bits of the lhs with 0's. > > > >if the lhs is narrower than the rhs only use the ls bits of the rhs. > > > >if the rhs is some complex expression then its width is the width of the largest > >operand. > > The problem is that it is easy to connect two different sized busses > in Verilog and the problems can be very difficult to detect during > testing. For example topmost bit missing etc. I have seen too many > problems caused by the fact that Verilog doesn't check the bus widths. > The errors are easy to make for example when one big bitvector is built > from tens of other busses and one width is defined incorrectly. In > VHDL the compiler complains immediatly about bus sizes. Those bugs can > take days to find in complex designs. > > >VHDL, by contrast, allows complex derived data types and therefore *needs* > >strong type checking [Historical question: Which came first, complex types or > >strong typing ?]. > > Quite few people actually use the data types in synthesizable code > altough it is very wise thing to do. One example is the control bus if > it is defined as record the compiler immediatly complains if the bus is > connected to wrong place. Bit vectors can be by chance same sized and > connected incorrectly. > > >Because Verilog's types are restricted these sort of issues can mostly be taken > >care of by some careful self-discipline or formal coding styles. If necessary > >you could invest in one of the `lint' style tools [Anyone know if there's a > >shareware or GPL'ed one ?]. > > Try sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > > -- > ======================================================================== ===== > Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian > Iirislahdentie 47 E | IRC: embo | curved-space fault in > 02230 Espoo,Finland | | write-only file system > Sent via Deja.com http://www.deja.com/ ###### From: "Joel Kolstad" Newsgroups: comp.arch.fpga References: <91a2q0$f7va$1@as121.tel.hr> <91b64u$9gl$1@bcarh8ab.ca.nortel.com> <3A39605A.80319943@algor.co.uk> <92hfu4$roa$1@nnrp1.deja.com> Subject: Re: Verilog or VHDL Lines: 36 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Message-ID: Date: Mon, 01 Jan 2001 18:42:47 GMT NNTP-Posting-Host: 63.53.236.106 X-Complaints-To: abuse@earthlink.net X-Trace: newsread2.prod.itd.earthlink.net 978374567 63.53.236.106 (Mon, 01 Jan 2001 10:42:47 PST) NNTP-Posting-Date: Mon, 01 Jan 2001 10:42:47 PST Organization: EarthLink Inc. -- http://www.EarthLink.net Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!feed2.onemain.com!feed1.onemain.com!newsfeed2.earthlink.net!newsfeed.earthlink.net!newsmaster1.prod.itd.earthlink.net!newsread2.prod.itd.earthlink.net.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3578 wrote in message news:92hfu4$roa$1@nnrp1.deja.com... > Come on guys. It's all about types. For example, jsut look at C/C++. > Without regarding the OO aspects of C++, one of the most powerful > introductions of it comparing to C was the HARD TYPE CHECKING > capabilities it offers, which allows to easily find mistakes and make > all the coding stage of a design easier, since it's not just about > writing lots of lines of code, but to make it work as desired. True enough, but what you're not mentioning is that C++ is also powerful enough that you can sit around and create your own copy or conversion constructors that take in any other object type and convert it to whatever you're really after. VHDL doesn't allow such flexibility -- operating overloading is about as close as you get. And you can't even overload the assignment operator! (The fact that resolution functions are not well supported by synthesis is also unfortunate.) Granted, this functionality can be abused in C++, and the list of rules on how a C++ compiler is supposed to find the right operator is long enough to choke a horse, but there C++ is just being true to its C roots -- all the power you want, seat belts are optional. We've got a bunch of people where I work who complain about the use of 'const' in C++ ("Now I have to make all my code const-correct to call your functions!") and exception handling (we actually have one guy who was trying to convince me not to throw him an exception if he fed me garbage because, "Hidden bugs are better than crashing applications," i.e., he wasn't about to catch the exception himself, hence Windoze would, and shut down his program... arrrggghhh!); these are probably the same people who only see the annoyance and none of the benefit of VHDL's strict type checking. (I see the benefit, but I still find it annoying at times. :-) ) ---Joel Kolstad