From: Kent Orthner Newsgroups: comp.arch.fpga Subject: Wide AND function. Date: 29 Nov 2000 11:07:05 +0900 Organization: ... Lines: 38 Sender: korthner@KENT Message-ID: NNTP-Posting-Host: dhcp237.inf.furukawa.co.jp X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Canyonlands" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!logbridge.uoregon.edu!newsfeed.media.kyoto-u.ac.jp!onodera-news!onion.ish.org!nf1.xephion.ne.jp!fintnews!ifnews!inf-gw!postmaster Xref: chonsp.franklin.ch comp.arch.fpga:2985 Hi, everyone. I'm looking to impement a wide trinary compare function (32 bits), in once clock cycle. The bit-wise compare function consist of three bits; a Data bit (D), a Comparand bit (C), and a Mask bit (M). If the bit is masked with M, then the bit match is always a success. Otherwise it's a success only if D = C. This is easy enough, and takes up almost no logic. If all of the bitwise compare functions are a success, then the compare itself is a success, wheras if one fails, then the compare fails. This is basically a big 'ole and gate. Seeing as I want to do this in one clock cycle, and *really* don't want to pipeline it, is there a fancy way of implementing a wide AND-function? I was thinking of something along the lines of 32 trisate drivers and a pull-up. If one of them failes, it drives the common bus low; if none of them fail, the bus is pulled high, and a 'success' is registered. Unless I'm missing something (which is entirely possible), there is nothing like this on the inside of a Virtex/SpartanII FPGA. Does anyone have any other ideas or suggestions? Thanks a bunch, Kent. ###### From: Duane Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: Tue, 28 Nov 2000 19:14:21 -0800 Organization: http://extra.newsguy.com Lines: 50 Message-ID: <3A24748D.4E7A13CD@junkmail.com> References: NNTP-Posting-Host: p-649.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.12-20 i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!news1 Xref: chonsp.franklin.ch comp.arch.fpga:2968 Kent Orthner wrote: > > Hi, everyone. > > I'm looking to impement a wide trinary compare > function (32 bits), in once clock cycle. > > The bit-wise compare function consist of three > bits; a Data bit (D), a Comparand bit (C), and > a Mask bit (M). > > If the bit is masked with M, then the bit match > is always a success. Otherwise it's a success > only if D = C. This is easy enough, and takes > up almost no logic. > > If all of the bitwise compare functions are a > success, then the compare itself is a success, > wheras if one fails, then the compare fails. > This is basically a big 'ole and gate. > > Seeing as I want to do this in one clock cycle, > and *really* don't want to pipeline it, is > there a fancy way of implementing a wide > AND-function? I was thinking of something along > the lines of 32 trisate drivers and a pull-up. > If one of them failes, it drives the common bus > low; if none of them fail, the bus is pulled high, > and a 'success' is registered. Unless I'm missing > something (which is entirely possible), there is > nothing like this on the inside of a Virtex/SpartanII > FPGA. Actually, there is. For clues, take a look in the Libraries guide at the Virtex/SpartanII implementation of the COMPMC8. Basically what you would do would be to implement the logic for the three bits in the LUT, and use the output to control the S select of the MUXCY in the ripple carry chain. This chain is very fast, and should easily handle 32 bits for all but very fast clocks. The way I have done almost the exact same thing in one of my designs is to connect GND to all the DI inputs of the MUXCYs in the chain and connect VCC to the CI input of the first MUXCY in the chain. The rest are chained together the standard way with O of one MUXCY going to CI of the next one. At the top of the chain, the of the last MUXCY is low if any of the bit tests failed, else the VCC from the first MUX ripples all the way through and the result is a high. -- My real email is akamail.com@dclark (or something like that). ###### From: Kent Orthner Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: 29 Nov 2000 13:38:31 +0900 Organization: ... Lines: 33 Sender: korthner@KENT Message-ID: References: <3A24748D.4E7A13CD@junkmail.com> NNTP-Posting-Host: dhcp237.inf.furukawa.co.jp X-Newsreader: Gnus v5.6.45/XEmacs 21.1 - "Canyonlands" Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.stanford.edu!newsfeed.mesh.ad.jp!newsfeed.media.kyoto-u.ac.jp!onodera-news!onion.ish.org!nf1.xephion.ne.jp!fintnews!ifnews!inf-gw!postmaster Xref: chonsp.franklin.ch comp.arch.fpga:2986 > Kent Orthner wrote: > > > > Seeing as I want to do this in one clock cycle, > > and *really* don't want to pipeline it, is > > there a fancy way of implementing a wide > > nothing like this on the inside of a Virtex/SpartanII > > FPGA. > Duane writes: > Actually, there is. For clues, take a look in the Libraries guide at the > the way through and the result is a high. Duane, Thanks. This is exactly the kind of "Fancy way" that I was looking for. In the data book it shown Cin to Cout delay to be 0.2ns max, which should give me 6.4 ns for the entire thing. I'm hoping for 9.6ns for everything, including the compare, but maybe I'm being too optimistic. (I'm stuck with the cheapest speed grade, after all.) Maybe I'll run it as a tree of CinCout chains or something; we'll see. Thanks for the advice. On a side note, when I look at the CY Muxes, do you know what the 'BX' input is, and what it's for? -Kent ###### Message-ID: <3A24E6D8.B6480C2F@algor.co.uk> From: Rick Filipkiewicz X-Mailer: Mozilla 4.75 [en] (WinNT; U) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. References: <3A24748D.4E7A13CD@junkmail.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Organization: Algorithmics Ltd. Cache-Post-Path: mudchute.algor.co.uk!root@oval.algor.co.uk X-Cache: nntpcache 2.4.0b2 (see http://www.nntpcache.org/) Lines: 41 Date: Wed, 29 Nov 2000 11:22:01 +0000 NNTP-Posting-Host: 62.254.210.251 X-Complaints-To: abuse@ntlworld.com X-Trace: news2-win.server.ntlworld.com 975496925 62.254.210.251 (Wed, 29 Nov 2000 11:22:05 GMT) NNTP-Posting-Date: Wed, 29 Nov 2000 11:22:05 GMT Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!psinet-eu-nl!newsfeeds.belnet.be!news.belnet.be!btnet-peer1!btnet-peer0!btnet!news5-gui.server.ntli.net!ntli.net!news2-win.server.ntlworld.com.POSTED!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:2963 Kent Orthner wrote: > > Kent Orthner wrote: > > > > > > Seeing as I want to do this in one clock cycle, > > > and *really* don't want to pipeline it, is > > > there a fancy way of implementing a wide > > > > nothing like this on the inside of a Virtex/SpartanII > > > FPGA. > > > > Duane writes: > > Actually, there is. For clues, take a look in the Libraries guide at the > > > the way through and the result is a high. > > Duane, > > Thanks. This is exactly the kind of "Fancy way" that I was looking for. > In the data book it shown Cin to Cout delay to be 0.2ns max, which should > give me 6.4 ns for the entire thing. I'm hoping for 9.6ns for everything, > including the compare, but maybe I'm being too optimistic. (I'm stuck > with the cheapest speed grade, after all.) > > Maybe I'll run it as a tree of CinCout chains or something; we'll see. > > Thanks for the advice. > > On a side note, when I look at the CY Muxes, do you know what the 'BX' > input is, and what it's for? > > -Kent You might be able to do even better if you split the thing into 2 16 bit chains using the left & right slices of a CLB column. Use local routing in the last CLB to and them togther via an LUT (or MULT_AND ?) and the result might come in under 5ns. ###### From: Phil James-Roxby Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: Mon, 04 Dec 2000 08:41:17 -0700 Organization: Xilinx, Inc. Lines: 21 Message-ID: <3A2BBB1D.91B758C@xilinx.com> References: <3A24748D.4E7A13CD@junkmail.com> NNTP-Posting-Host: 149.199.185.56 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!nntp.primenet.com!nntp.gblx.net!nntp.giganews.com!nntp2.aus1.giganews.com!NetNews1!attla1!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3085 Kent Orthner wrote: > On a side note, when I look at the CY Muxes, do you know what the 'BX' > input is, and what it's for? I'm presuming you mean the BX input of the CLB. The BX input is used to inject a constant 0 or 1 into the carry chain. If no signal is connected to the BX input, it is pulled high. Then by passing this high through a configurable buffer/invertor, you can get a 0 or 1. BX is also used as the select line for the F5 mux, and finally acts as the data input when using the LUT as a shift register or a RAM. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder --------------------------------------------------------------------- ###### From: erika_uk@my-deja.com Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: Tue, 05 Dec 2000 13:35:12 GMT Organization: Deja.com - Before you buy. Lines: 17 Message-ID: <90iqug$av$1@nnrp1.deja.com> References: <3A24748D.4E7A13CD@junkmail.com> <3A2BBB1D.91B758C@xilinx.com> NNTP-Posting-Host: 143.117.5.22 X-Article-Creation-Date: Tue Dec 05 13:35:12 2000 GMT X-Http-User-Agent: Mozilla/4.7 [en] (Win95; I) X-Http-Proxy: 1.0 x55.deja.com:80 (Squid/1.1.22) for client 143.117.5.22 X-MyDeja-Info: XMYDJUIDerika_uk Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!uni-erlangen.de!newsfeed.germany.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!ptdnetP!newsgate.ptd.net!feeder.qis.net!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3101 hey, <..> If no signal is connected to the BX input, it is pulled high. Then by passing this high through a configurable buffer/invertor, you can get a 0 or 1. <..> how can i control the use of BX?.can i direct the tool to get 0 or 1 from what you said above ? --Erika Sent via Deja.com http://www.deja.com/ Before you buy. ###### From: Phil James-Roxby Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: Tue, 05 Dec 2000 11:03:02 -0700 Organization: Xilinx, Inc. Lines: 17 Message-ID: <3A2D2DD6.ECD3B35F@xilinx.com> References: <3A24748D.4E7A13CD@junkmail.com> <3A2BBB1D.91B758C@xilinx.com> <90iqug$av$1@nnrp1.deja.com> NNTP-Posting-Host: 149.199.185.56 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.ifi.unizh.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsfeed.direct.ca!look.ca!nntp2.aus1.giganews.com!NetNews1!attla1!ip.att.net!newsgate.xilinx.com!xbc-news.xilinx.com!not-for-mail Xref: chonsp.franklin.ch comp.arch.fpga:3094 erika_uk@my-deja.com wrote: > how can i control the use of BX?.can i direct the tool to get 0 or 1 > from what you said above ? The mainstream tools will/should infer the use of this structure. If you need total control and would enjoy messing with CLB resources like this, the only tool that works at this level is JBits. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder --------------------------------------------------------------------- ###### From: Duane Newsgroups: comp.arch.fpga Subject: Re: Wide AND function. Date: Wed, 06 Dec 2000 15:11:07 -0800 Organization: http://extra.newsguy.com Lines: 18 Message-ID: <3A2EC78B.82F75914@junkmail.com> References: <3A24748D.4E7A13CD@junkmail.com> <3A2BBB1D.91B758C@xilinx.com> <90iqug$av$1@nnrp1.deja.com> <3A2D2DD6.ECD3B35F@xilinx.com> NNTP-Posting-Host: p-837.newsdawg.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Mailer: Mozilla 4.76 [en] (X11; U; Linux 2.2.12-20 i686) X-Accept-Language: en Path: chonsp.franklin.ch!pfaff.ethz.ch!news-zh.switch.ch!news.nextra.ch!news1.sunrise.ch!news.imp.ch!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!newsxfer.eecs.umich.edu!pln-w!spln!dex!extra.newsguy.com!newsp.newsguy.com!news2 Xref: chonsp.franklin.ch comp.arch.fpga:3155 Phil James-Roxby wrote: > > erika_uk@my-deja.com wrote: > > how can i control the use of BX?.can i direct the tool to get 0 or 1 > > from what you said above ? > > The mainstream tools will/should infer the use of this structure. If > you need total control and would enjoy messing with CLB resources like > this, the only tool that works at this level is JBits. > Phil And to be slightly more verbose about how to get the tool to infer this... attach a GND or VCC to the CI input of the first MUXCY in the chain, and the tools will infer that this is accomplished via the BX input. -- My real email is akamail.com@dclark (or something like that).